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  -02365"   -02365#@@ @ @ @@@@@-@@@@@@@@0A2A3A6A5A$BB B B BBBBB-BBBBBBBB0C2C3C6C5C%DD D D DDDDD-DDDDDDDD0E2E3E6E5E&  HHACE2ssssAsCsEmmmmAmCmE@DHLPTCGKOSW0  >?@0.-/kmlon.-/kmlon.-/kmlon.-/kmlon.-/kmlon.-/kmlon\\\\\\\9\;\<\?@AB<P`QRBCDE^_KH@A\]ILJMGQSYZ[\]^_=>?@AB<P`QRBCDE^_KH@A\]ILJMGQSYZ[\]^_=>?@AB<P`QRBCDE^_KH@A\]ILJMGQS@Y@Z@[@\@]@^@_@=@>@?@@@A@B@<@@@@@@@@@@@@@@@@@P@`@Q@R@@@BACADAEA^A_AKAHAAA@AAA\A]AIALAJAMAGA@QASABYBZB[B\B]B^B_B=B>B?B@BABBBD?D@DADBD\9\;\<\?@AB<P`QRBCDE^_KH@A\]ILJMGQSYZ[\]^_=>?@AB<P`QRBCDE^_KH@A\]ILJMGQSYZ[\]^_=>?@AB<P`QRBCDE^_KH@A\]ILJMGQS??0 nfjklmhig-./0~xyzXnfjklmhig-./0~xyzXnfjklmhig-./0~xyzX@"H H!HHTU/K9+*)QJ #H @    .&&((**dce110_opp_power_on_regamma_lut_vpower_on_lutset_bypass_input_gammaset_Denormalizationconfigure_graphics_mode_vprogram_input_cscprogram_color_matrix_v  , &  8 S3h%h%gh%@:e2  } a;O 9h%h%% h%C ```G/GI5 G G IO5dce110_timing_generator_v_program_blankingdce110_timing_generator_v_disable_crtcdce110_timing_generator_v_is_counter_movingdce110_timing_generator_v_get_vblank_counterdce110_timing_generator_v_set_early_controldce110_timing_generator_v_is_in_vertical_blankdce110_timing_generator_v_unblank_crtcdce110_timing_generator_v_blank_crtcdce110_timing_generator_v_program_blank_colordce110_tg_v_program_blank_colordce110_timing_generator_v_enable_advanced_requestdce110_allocate_mem_input_vprogram_stutter_watermarkprogram_nbp_watermarkprogram_urgency_watermarkprogram_pixel_formatenabledce_mem_input_v_program_pte_vmset_flip_controldce_mem_input_v_is_surface_pending @ @@@@@  @ set_coeff_update_completeprogram_multi_taps_filterdce110_xfmv_power_up_line_bufferdce110_xfmv_set_pixel_storage_depth@ 0    ;;;;;;??0  `     -02365!H   -02365"H   -02365#H@@ @ @ @@@@@-@@@@@@@0A2A3A6A5A$HBB B B BBBBB-BBBBBBB0C2C3C6C5C%HDD D D DDDDD-DDDDDDD0E2E3E6E5E&H  HHACE2ssssAsCsEmmmmAmCmE@DHLPT@"H H!HHTU/K9+*)QJ #H @    .0:819[?@0.-/kmlon.-/kmlon.-/kmlon.-/kmlon.-/kmlon.-/kmlon.-/kmlon\\\\\\\9\;\<\?@AB<P`QRBCDE^_KH@A\]ILJMGQSYZ[\]^_=>?@AB<P`QRBCDE^_KH@A\]ILJMGQSYZ[\]^_=>?@AB<P`QRBCDE^_KH@A\]ILJMGQS@Y@Z@[@\@]@^@_@=@>@?@@@A@B@<@@@@@@@@@@@@@@@@@P@`@Q@R@@@BACADAEA^A_AKAHAAA@AAA\A]AIALAJAMAGA@QASABYBZB[B\B]B^B_B=B>B?B@BABBBD?D@DADBD?@AB<P`QRBCDE^_KH@A\]ILJMGQSYZ[\]^_=>?@AB<P`QRBCDE^_KH@A\]ILJMGQS@Y@Z@[@\@]@^@_@=@>@?@@@A@B@<@A@@@@@@@@@@@@@@@@P@`@Q@R@@@BACADAEA^A_AKAHA@AAA\A]AIALAJAMAGA@QASACYCZC[C\C]C^C_C=C>C?C@CACBCF?F@FAFBFI?I@IAIBI failed %d 4[drm] ASIC reset failed with error, %d for drm dev, %ssuspend of IP block <%s> failed %d SMC failed to set mp1 state %d, %d 6[drm] virtual display string:%s, %s:virtual_display:%d, num_crtc:%d Failed to load gpu_info firmware "%s" Failed to validate gpu_info firmware "%s" Unsupported gpu_info table %d early_init of IP block <%s> failed %d hw_init of IP block <%s> failed %d sw_init of IP block <%s> failed %d amdgpu_vram_scratch_init failed %d amdgpu_device_wb_init failed %d IB initialization failed (%d). set_powergating_state(gate) of IP block <%s> failed %d set_clockgating_state(gate) of IP block <%s> failed %d 6[drm] Some block need full reset! 4[drm] Smu memory pool size not supported 4[drm] No enough system memory sched jobs (%d) must be at least 4 valid range is between 4 and 9 VM size (%d) too small, min is 1GB VM page table size (%d) too small invalid lockup_timeout parameter syntax sched jobs (%d) must be a power of 2 late_init of IP block <%s> failed %d enable mgpu fan boost failed (%d). 6[drm] recover vram bo from shadow start recover vram bo from shadow failed, r is %ld, tmo is %ld 6[drm] recover vram bo from shadow done reading beyond doorbell aperture: 0x%08x! writing beyond doorbell aperture: 0x%08x! 4[drm] System can't access extended configuration space,please check!! 6[drm] Not enough PCI address space for a large BAR.set_clockgating_state of IP block <%s> failed %d set_powergating_state of IP block <%s> failed %d 6[drm] add ip block number %d <%s> 6[drm] soft reset failed, will fallback to full reset! 6[drm] initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X). 6[drm] register mmio base: 0x%08X 6[drm] register mmio size: %u 6[drm] PCI I/O BAR is not found. 6[drm] PCIE atomic ops is not supported amdgpu_atomfirmware_get_clock_info failed amdgpu_atombios_get_clock_info failed amdgpu_fence_driver_init failed registering pm debugfs failed (%d). Creating firmware sysfs failed (%d). registering gem debugfs failed (%d). registering register debugfs failed (%d). registering firmware debugfs failed (%d). Creating debugfs files failed (%d). 6[drm] amdgpu: acceleration disabled, skipping move tests 6[drm] amdgpu: acceleration disabled, skipping benchmarks amdgpu_device_ip_late_init failed Could not create pcie_replay_count6[drm] amdgpu: finishing device. hw_fini of IP block <%s> failed %d sw_fini of IP block <%s> failed %d failed to release exclusive mode on fini amdgpu_device_ip_resume failed (%d). 6[drm] Timeout, but no hardware hang detected. 6[drm] GPU recovery disabled. 6[drm] Bailing on TDR for s_job:%llx, hive: %llx as another already in progress6[drm] Bailing on TDR for s_job:%llx, as another already in progressGuilty job already signaled, skipping HW resetGPU pre asic reset failed with err, %d for drm dev, %s ASIC reset failed with error, %d for drm dev, %s4[drm] asic atom init failed!GPU reset succeeded, trying to resume 6[drm] VRAM is lost due to GPU reset! Buffer overflow detected (%d < %lu)! VCE feature version: %u, firmware version: 0x%08x UVD feature version: %u, firmware version: 0x%08x MC feature version: %u, firmware version: 0x%08x ME feature version: %u, firmware version: 0x%08x PFP feature version: %u, firmware version: 0x%08x CE feature version: %u, firmware version: 0x%08x RLC feature version: %u, firmware version: 0x%08x RLC SRLC feature version: %u, firmware version: 0x%08x RLC SRLG feature version: %u, firmware version: 0x%08x RLC SRLS feature version: %u, firmware version: 0x%08x MEC feature version: %u, firmware version: 0x%08x MEC2 feature version: %u, firmware version: 0x%08x SOS feature version: %u, firmware version: 0x%08x ASD feature version: %u, firmware version: 0x%08x TA %s feature version: %u, firmware version: 0x%08x SMC feature version: %u, firmware version: 0x%08x SDMA%d feature version: %u, firmware version: 0x%08x VCN feature version: %u, firmware version: 0x%08x DMCU feature version: %u, firmware version: 0x%08x Cannot register more gpu instance Error during ACPI methods call drivers/gpu/drm/amd/amdgpu/amdgpu_kms.ccrtc %d: dist from vblank start %d NULL mode info! Returned count may be wrong. invalid con_obj_id %d for device tag 0x%04x Changing default dispclk from %dMhz to 600Mhz Changing default dispclk from %dMhz to 625Mhz Unsupported ASIC_InternalSS_Info table: %d %d PCI I/O BAR is not found. Using MMIO to access ATOM BIOS &adev->mode_info.atom_context->mutexatom firmware requested %08x %dkb Failed to create device file for VBIOS version Determined LVDS native mode details from EDID No LVDS native mode details, disabling RMX Adding cvt approximation of native panel mode %s %s: HDMI deep color %d bpc unsupported. Using 12 bpc. %s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz. %s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc. %s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc. %s: Required max tmds clock for HDMI deep color missing. Using 8 bpc. %s: Deep color disabled. Set amdgpu module param deep_color=1 to enable. %s: Display bpc=%d, returned bpc=%d %s: probed a monitor but no|invalid EDID Failed to assign router i2c bus! Check dmesg for i2c errors. DP: Failed to assign ddc bus! Check dmesg for i2c errors. VGA: Failed to assign ddc bus! Check dmesg for i2c errors. DVIA: Failed to assign ddc bus! Check dmesg for i2c errors. DVI: Failed to assign ddc bus! Check dmesg for i2c errors. HDMI: Failed to assign ddc bus! Check dmesg for i2c errors. LVDS: Failed to assign ddc bus! Check dmesg for i2c errors. 6PCI registers are not implemented 6SYSIO registers are not implemented 6Undefined indirect IO read method %d ATOM: fb read beyond scratch region: %d vs. %d 6Undefined indirect IO write method %d ATOM: fb write beyond scratch region: %d vs. %d atombios stuck in loop for more than 10secs aborting >> execute %04X (len %d, WS %d, PS %d) atombios stuck executing %04X (len %d, WS %d, PS %d) @ 0x%04X UpdateCRTC_DoubleBufferRegistersdrivers/gpu/drm/amd/amdgpu/amdgpu_fence.c4[drm] Fence fallback timer expired on ring %s Last signaled fence 0x%08x Last emitted 0x%08x Last signaled trailing fence 0x%08x Last preempted 0x%08x Last reset 0x%08x Last both 0x%08x fence driver on ring %s use gpu addr 0x%016llx, cpu addr 0x%p Failed to create scheduler on ring %s. fence debugfs file creation failed drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.hdrivers/gpu/drm/amd/amdgpu/amdgpu_ttm.cfailed to unbind %lu pages at 0x%08llX 3Page fault failed for pfn[%lu] = 0x%llx user_pages_done 0x%llx pages 0x%lx failed to bind %lu pages at 0x%08llX nothing to bind %lu pages for mreg %p back %p! 6[drm] amdgpu: ttm finalized Failed setting up TTM BO move entity (%d) failed initializing buffer object driver(%d). Failed initializing VRAM heap. 6[drm] amdgpu: %uM of VRAM memory ready Failed initializing GTT heap. 6[drm] amdgpu: %uM of GTT memory ready. Failed initializing GDS heap. Failed initializing gws heap. Trying to move memory with ring turned off. Trying to clear memory with ring turned off. 3Failed to find GTT space for blit to VRAM 3Failed to find GTT space for blit from VRAM 3Move buffer fallback to memcpy unavailable drivers/gpu/drm/amd/amdgpu/amdgpu_object.cBO size %lu > total memory in domain: %llu drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h6[drm] Detected VRAM RAM=%lluM, BAR=%lluM (%d) failed to allocate kernel bo (%d) failed to reserve kernel bo trying to unbind memory from uninitialized GART ! drivers/gpu/drm/amd/amdgpu/amdgpu_gart.ctrying to bind memory to uninitialized GART ! Failed to DMA MAP the dummy page 6[drm] GART: num cpu pages %u, num gpu pages %u setting active device to %08x from %08x %08x for encoder %d failed to unpin buffer after flip failed to reserve buffer after flip 6[drm] AMDGPU Display Connectors 6[drm] DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 6[drm] DDC Router 0x%x/0x%x 6[drm] Clock/Data Router 0x%x/0x%x 6[drm] DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org No GEM object associated to handle 0x%08X, can't create framebuffer Cannot create framebuffer from imported dma_buf crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p, failed to pin new abo buffer before flip failed to get fences for buffer flip queue: crtc already busy crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p, failed to unpin new abo in error path failed to reserve new abo in error path failed to reserve new abo buffer before flip i2c 0x%02x 0x%02x read failed i2c 0x%02x 0x%02x write failed Failed to register bit i2c %s drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c6[drm] hw_i2c forced on, you may experience display detection problems! 3failed to allocate framebuffer (%d) failed to create fbcon object %d failed to initialize framebuffer %d Failed to allocate GEM object (%ld, %d, %u, %d) Still active user space clients! drivers/gpu/drm/amd/amdgpu/amdgpu_gem.cleaking bo va because we fail to reserve bo (%ld) failed to clear page tables on GEM object close (%ld) va_address 0x%LX is in reserved area 0x%LX va_address 0x%LX is in VA hole 0x%LX-0x%LX va_address 0x%llx is in top reserved area 0x%llx invalid flags combination 0x%08X drivers/gpu/drm/amd/amdgpu/amdgpu_ring.camdgpu: writing more dwords to the ring than expected! (%d) ring rptr_offs wb alloc failed (%d) ring wptr_offs wb alloc failed (%d) ring fence_offs wb alloc failed (%d) ring trail_fence_offs wb alloc failed (%d) ring cond_exec_polling wb alloc failed failed initializing fences (%d). Failed to register debugfs file for rings ! *ERROR* ring %s test failed (%d) drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.hsyncobj %u failed to find fence @ %llu (%d)! ttm_eu_reserve_buffers failed. amdgpu_vm_validate_pt_bos() failed. IB va_start+ib_bytes is invalid drivers/gpu/drm/amd/amdgpu/amdgpu_cs.cFailed to initialize parser %d! Failed in the dependencies handling %d! Not enough memory for command submission! Failed to process the buffer list %d! 6[drm] vbios mem is null or mem size is wrong 6[drm] BIOS signature incorrect %x %x 6[drm] Can't locate bios header 6[drm] BIOS header is broken failed to evaluate ATRM got %s ACPI VFCT table present but broken (too short #1) ACPI VFCT image header truncated ACPI VFCT table present but broken (too short #2) no memory to allocate for BIOS 6[drm] amdgpu: %s %u bo moves of %u kB from %d to %d in %u ms, throughput: %u Mb/s or %u MB/s Error while benchmarking BO move. Failed to allocate %d pointers Failed to create GTT object %d Failed to wait for GTT->VRAM fence %d Failed to map VRAM object after copy %d Incorrect GTT->VRAM copy %d: Got 0x%p, expected 0x%p (GTT/VRAM offset 0x%16llx/0x%16llx) Failed to wait for VRAM->GTT fence %d Failed to map GTT object after copy %d Incorrect VRAM->GTT copy %d: Got 0x%p, expected 0x%p (VRAM/GTT offset 0x%16llx/0x%16llx) 6[drm] Tested GTT->VRAM and VRAM->GTT copy for GTT offset 0x%llx 4Error while testing BO move 3Currently not in any profile mode! 6manual fan speed control should be enabled first Graphics Medium Grain Clock GatingClock Gating Flags Mask: 0x%x Debugfs support not implemented for this asic [SW SMU]: dpm enable uvd failed, state = %s, ret = %d. [SW SMU]: dpm enable vce failed, state = %s, ret = %d. failed to create device file pp_dpm_sclk failed to create device file pp_dpm_mclk failed to create device file for dpm state 3smu firmware loading failed Unable to register hwmon device: %d failed to create device file pp_num_states failed to create device file pp_cur_state failed to create device file pp_force_state failed to create device file pp_table failed to create device file pp_dpm_socclk failed to create device file pp_dpm_dcefclk failed to create device file pp_dpm_fclk failed to create device file pp_dpm_pcie failed to create device file pp_sclk_od failed to create device file pp_mclk_od failed to create device file pp_power_profile_mode failed to create device file pp_od_clk_voltage failed to create device file gpu_busy_level failed to create device file mem_busy_percent failed to create device file pcie_bw failed to create device file unique_id Failed to register debugfs file for dpm! failed to create device file pp_features power_dpm_force_performance_leveldrivers/gpu/drm/amd/amdgpu/amdgpu_pm.cGraphics Medium Grain memory Light SleepGraphics Coarse Grain Clock GatingGraphics Coarse Grain memory Light SleepGraphics Coarse Grain Tree Shader Clock GatingGraphics Coarse Grain Tree Shader Light SleepGraphics Command Processor Light SleepGraphics Run List Controller Light SleepGraphics 3D Coarse Grain Clock GatingGraphics 3D Coarse Grain memory Light SleepMemory Controller Medium Grain Clock GatingSystem Direct Memory Access Light SleepSystem Direct Memory Access Medium Grain Clock GatingBus Interface Medium Grain Clock GatingUnified Video Decoder Medium Grain Clock GatingVideo Compression Engine Medium Grain Clock GatingHost Data Path Medium Grain Clock GatingDigital Right Management Medium Grain Clock GatingDigital Right Management Light SleepData Fabric Medium Grain Clock GatingAddress Translation Hub Medium Grain Clock GatingAddress Translation Hub Light Sleeprequested signal parameters: lane %d voltage %s pre_emph %s using signal parameters: voltage %s pre_emph %s drivers/gpu/drm/amd/amdgpu/atombios_dp.cdrm_dp_aux_register_i2c_bus() failed with error %d displayport link status failed clock recovery reached max voltage clock recovery at voltage %d pre-emphasis %d channel eq at voltage %d pre-emphasis %d 4Calculated ACR N value is too small. You may experience audio problems. 4Calculated ACR N value is too large. You may experience audio problems. Calculated ACR timing N=%d CTS=%d for frequency %d ih:%u client_id:%u src_id:%u ring:%u vmid:%u timestamp: %llu pasid:%u src_data: %08x %08x %08x %08x bo=%p, pages=%u, type=%d, preferred=%d, allowed=%d, visible=%d bo_list=%p, ring=%u, dw=%u, fences=%u sched_job=%llu, timeline=%s, context=%u, seqno=%u, ring_name=%s, num_ibs=%u pasid=%d, ring=%s, id=%u, hub=%u, pd_addr=%010Lx needs_flush=%u bo=%p, start=%lx, last=%lx, offset=%010llx, flags=%llx soffs=%010llx, eoffs=%010llx, flags=%llx pe=%010Lx, addr=%010Lx, incr=%u, flags=%llx, count=%u pe=%010Lx, src=%010Lx, count=%u ring=%s, id=%u, hub=%u, pd_addr=%010Lx total_bo_size=%Ld, total_bo_count=%Ld bo=%p, from=%d, to=%d, size=%Ld job ring=%s, id=%llu, need pipe sync to fence=%p, context=%llu, seq=%u Backlight registration failed 6[drm] amdgpu atom DIG backlight initialized 6[drm] amdgpu atom LVDS backlight unloaded Unknown table version: %d, %d encoder dpms %d to mode %d, devices %08x, active_devices %08x (%d) failed to allocate bo for manager sa_manager is not empty, clearing anyway drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c[0x%010llx 0x%010llx] size %8lld protected by 0x%016llx on context %lluhw i2c: tried to write too many bytes (%d vs 3) hw i2c: missing buf with num > 1 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.cbo %p va 0x%010Lx-0x%010Lx conflict with 0x%010Lx-0x%010Lx VM size (%d) too large, max is %u GB VMPT only supports 2~4+1 levels 6[drm] vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.hCPU update of VM recommended only for large BAR system Leaking page tables because BO reservation failed couldn't schedule ib on ring <%s> failed to register debugfs file for SA *ERROR* IB test failed on %s (%d). %d - %d, pll dividers - fb: %d.%d ref: %d, post %d io_debug_array_offset_bytes: %u Unknown MC ucode version: %u.%u Unknown SMC ucode version: %u.%u Unknown GFX ucode version: %u.%u clear_state_descriptor_offset: %u avail_scratch_ram_locations: %u master_pkt_description_offset: %u reg_list_format_separate_start: %u reg_list_format_size_bytes: %u reg_list_format_array_offset_bytes: %u reg_list_array_offset_bytes: %u reg_list_format_separate_size_bytes: %u reg_list_format_separate_array_offset_bytes: %u reg_list_separate_size_bytes: %u reg_list_separate_array_offset_bytes: %u reg_list_format_direct_reg_list_length: %u save_restore_list_cntl_ucode_ver: %u save_restore_list_cntl_feature_ver: %u save_restore_list_cntl_size_bytes %u save_restore_list_cntl_offset_bytes: %u save_restore_list_gpm_ucode_ver: %u save_restore_list_gpm_feature_ver: %u save_restore_list_gpm_size_bytes %u save_restore_list_gpm_offset_bytes: %u save_restore_list_srm_ucode_ver: %u save_restore_list_srm_feature_ver: %u save_restore_list_srm_size_bytes %u save_restore_list_srm_offset_bytes: %u Unknown RLC ucode version: %u.%u Unknown SDMA ucode version: %u.%u Unknown PSP ucode version: %u.%u Unknown gpu_info ucode version: %u.%u failed to create kernel buffer for firmware.fw_buf drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.cError (%ld) waiting for fence! Failed to create device file mem_info_gtt_total Failed to create device file mem_info_gtt_used man size:%llu pages, gtt available:%lld pages, usage:%lluMB Failed to create device file mem_info_vram_total Failed to create device file mem_info_vis_vram_total Failed to create device file mem_info_vram_used Failed to create device file mem_info_vis_vram_used man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.hdrivers/gpu/drm/amd/amdgpu/amdgpu_virt.c3failed to write reg %x wait reg %x failed to alloc mm table and error = %d. 6[drm] MM table gpu addr = 0x%llx, cpu addr = %p. atom firmware requested %08x %dkb fw %dkb drv drivers/gpu/drm/amd/amdgpu/amdgpu_sched.cInvalid sched op specified: %d 4[drm] failed to preempt ring %d 6[drm] ring %d was preempted Reached maximum number of debugfs components. Report so we increase AMDGPU_DEBUGFS_MAX_COMPONENTS. unable to create amdgpu_preempt_ib debugsfs file Over limitation of reserved vmid VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used) GART: %lluM 0x%016llX - 0x%016llX AGP: %lluM 0x%016llX - 0x%016llX 3xGMI error counters not enabled! drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.cXGMI: Failed to allocate sysfs entry! XGMI: Failed to create device file xgmi_hive_id XGMI: Set pstate failure on device %llx, hive %llx, ret %dXGMI: Set topology failure on device %llx, hive %llx, ret %dXGMI: node 0x%llx, can not match hive 0x%llx in the hive list. XGMI: Get topology failure on device %llx, hive %llx, ret %dXGMI: Failed to create device file xgmi_device_id 3failed to create xgmi_error XGMI: Failed to create link to hive infoXGMI: Add node %d, hive 0x%llx. XGMI: Failed to create link from hive infoXGMI: Failed to add node %d, hive 0x%llx ret: %d failed to reserve CSA,PD BOs: err=%d failed to create bo_va for static CSA failed to do bo_map on static CSA, err=%d RAS ERROR: Unbalance obj(%s) use drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c%*s %*s %*s 0x%x 0x%llx 0x%llxRAS ERROR: unexpected block id %d drivers/gpu/drm/amd/amdgpu/amdgpu_ras.hRAS ERROR: unexpected error type %d RAS ERROR: %s %s feature failed ret %d 6[drm] RAS INFO: %s setup object %ld correctable errors detected in %s block %ld uncorrectable errors detected in %s block 6[drm] %s error injection is not supported yet RAS ERROR: inject %s error failed ret %d RAS ERROR: reserve vram %llx fail 6[drm] RAS INFO: ras initialized successfully, hardware ability[%x] ras_mask[%x] drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.cinvalid ip discovery binary signature invalid ip discovery binary checksum invalid ip discovery data table signature invalid ip discovery data table checksum invalid gc data table checksum invalid die id %d, expected %d number of hardware IPs on die%d: %d 6[drm] set register base offset for %s Failed to write EEPROM table header, ret:%dFailed to init I2C controller, ret:%dFailed to read EEPROM table header, ret:%dFound existing EEPROM table with %d records6[drm] Creating new EEPROM table6[drm] Reached end of EEPROM memory, jumping to 0 and overriding old recordReached end of EEPROM memory page, jumping to next: %lxFailed to process EEPROM table records, ret:%d4[drm] Checksum mismatch, checksum: %u 4[drm] EEPROM Table checksum mismatch!Failed to unlock the bus from SMUFailed to lock the bus from SMUI2C_Transmit(), address = %x, bytes = %d , data: 6[drm] TX was terminated, IC_TX_ABRT_SOURCE val is:%xReceived I2C_NAK_TXDATA_NOACK !!!Received I2C_NAK_7B_ADDR_NOACK !!!This operation not supposed to run in atomic context!drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.cReadData() - I2C error occurred :%xWriteI2CData() - I2C error occurred :%xI2C_Receive(), address = %x, bytes = %d, data :I2C bus unlocked, stopping transaction!Failed to register hw i2c, err: %d drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c4Error initializing AMDGPU %s PMUs. 6Detected AMDGPU %s Counters. # of Counters = %d. 6[drm] PCIE gen 3 link speeds already enabled 6[drm] enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0 6[drm] PCIE gen 2 link speeds already enabled 6[drm] enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0 IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X) power level %d sclk: %u vddc: %u power level %d sclk: %u vddc: %u amdgpu_kv_smc_bapm_enable failed kv_calculate_ds_divider failed The htcTmpLmt should be larger than htcHystLmt. amdgpu: dpm initialization failed 6[drm] amdgpu: dpm initialized kv_program_bootup_state failed kv_upload_dpm_settings failed kv_populate_samu_table failed kv_enable_auto_thermal_throttling failed kv_enable_dpm_voltage_scaling failed kv_process_firmware_header failed %sabling AFMT interface @ 0x%04X for encoder 0x%x amdgpu_crtc->pflip_status = %d != AMDGPU_FLIP_SUBMITTED(%d) IH: IH event w/o asserted irq bit? No connected audio pins found! %s: Disabling hdmi deep color for %d bpc. %s: Enabling hdmi deep color 30 for 10 bpc. %s: Enabling hdmi deep color 36 for 12 bpc. Couldn't find encoder's connector Couldn't read Speaker Allocation Data Block: %d drivers/gpu/drm/amd/amdgpu/dce_v8_0.cfailed to setup AVI infoframe: %zd failed to pack AVI infoframe: %zd failed to reserve abo before unpin bad cursor width or height %d x %d Cannot find cursor object %x for crtc %d Failed to pin new cursor BO (%d) Bypassing hardware LUT due to 10 bit fb scanout. drivers/gpu/drm/amd/amdgpu/gfx_v7_0.cIllegal instruction in command stream Illegal register access in command stream 3gfx7: Failed to load firmware "%s" (%d) create, pin or map of HDP EOP bo failed amdgpu: writing more dwords to the ring than expected! amdgpu: cp failed to lock ring (%d). clamping sdma_phase_quantum to %uK clock cycles drivers/gpu/drm/amd/amdgpu/cik_sdma.cIllegal instruction in SDMA command stream 3cik_sdma: Failed to load firmware "%s" Failed to load sdma firmware! amdgpu: writing more dwords to the ring than expected! UVD not responding, giving up!!! UVD not responding, trying to reset the VCPU!!! drivers/gpu/drm/amd/amdgpu/uvd_v4_2.camdgpu: writing more dwords to the ring than expected! amdgpu: ring failed to lock UVD ring (%d). 6[drm] UVD initialized successfully. VCE not responding, trying to reset the ECPU!!! VCE not responding, giving up!!! 6[drm] VCE is busy, Can't set clock gating6[drm] VCE initialized successfully. 6[drm] PCIE gen 3 link speeds already enabled 6[drm] enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0 6[drm] PCIE gen 2 link speeds already enabled 6[drm] enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0 invalid pcie lane request: %d drivers/gpu/drm/amd/amdgpu/si.cDisabling VM faults because of PRT request! Wait for GMC idle timed out ! No VRAM object for PCIE GART. PCIE GART of %uM enabled (table at 0x%016llX). drivers/gpu/drm/amd/amdgpu/gmc_v6_0.cGPU fault detected: %d 0x%08x VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d) si_mc: Failed to load firmware "%s" gmc_v6_0 PCIE GART already initialized amdgpu: No suitable DMA available. drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c3gfx6: Failed to load firmware "%s" Illegal instruction in command stream Illegal register access in command stream amdgpu: writing more dwords to the ring than expected! amdgpu: cp failed to lock ring (%d). IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X) 6[drm] si_dma_soft_reset --- not implemented !!!!!!! amdgpu: writing more dwords to the ring than expected! 6[drm] xxxx: dce_v6_0_soft_reset --- no impl!! %sabling AFMT interface @ 0x%04X for encoder 0x%x amdgpu_crtc->pflip_status = %d != AMDGPU_FLIP_SUBMITTED(%d) IH: IH event w/o asserted irq bit? Couldn't find encoder's connector No connected audio pins found! Couldn't read Speaker Allocation Data Block: %d failed to setup AVI infoframe: %zd failed to pack AVI infoframe: %zd Out of memory allocating afmt table failed to reserve abo before unpin bad cursor width or height %d x %d Cannot find cursor object %x for crtc %d Failed to pin new cursor BO (%d) Bypassing hardware LUT due to 10 bit fb scanout. power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u 6[drm] uvd vclk: %d dclk: %d 6[drm] power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u Unknown SI asic revision, failed to initialize PowerTune! Invalid PL2! DTE will not be updated. Could not enable thermal interrupts. si_restrict_performance_levels_before_switch failed si_enable_power_containment failed si_upload_mc_reg_table failed si_program_memory_timing_parameters failed si_set_power_state_conditionally_enable_ulv failed si_power_control_set_level failed si_construct_voltage_tables failed si_init_smc_spll_table failed si_init_arb_table_index failed si_populate_mc_reg_table failed si_initialize_smc_cac_tables failed si_initialize_hardware_cac_manager failed si_initialize_smc_dte_tables failed si_populate_smc_tdp_limits failed si_populate_smc_tdp_limits_2 failed Failed to load fan table to the SMC.si_notify_smc_display_change failed si_process_firmware_header failed Could not patch vddc_on_sclk leakage table Could not patch vddc_on_mclk leakage table Could not patch vddci_on_mclk leakage table drivers/gpu/drm/amd/amdgpu/si_dpm.csi_smc: Failed to load firmware. err = %d"%s" amdgpu: dpm initialization failed 6[drm] amdgpu: dpm initialized 3RCV_MSG_VALID is not cleared 3Doesn't get ack from pf, give up drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c3timeout: rlcg program reg:0x%05x failed ! 3Doesn't get msg:%d from pf, error=%d 3trn=%x ACK should not assert! wait again ! 3Doesn't get TRN_MSG_ACK from pf in %d msec 3Doesn't get ack from pf, continue 3Doesn't get READY_TO_ACCESS_GPU from pf, give up 4[drm] failed to init reg base from ip discovery table, fallback to legacy init method config=%llx addr=%08x:%08x val=%08x:%08x[DF PMC] addressing not retrieved! Lo: %x, Hi: %xfailed to create file for available df counters Disabling VM faults because of PRT request! Wait for GMC idle timed out ! No VRAM object for PCIE GART. 6[drm] PCIE GART of %uM enabled (table at 0x%016llX). GPU fault detected: %d 0x%08x VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d) drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c3cik_mc: Failed to load firmware "%s" R600 PCIE GART already initialized 4amdgpu: No suitable DMA available Disabling VM faults because of PRT request! No VRAM object for PCIE GART. 6[drm] PCIE GART of %uM enabled (table at 0x%016llX). Wait for GMC idle timed out ! GPU fault detected: %d 0x%08x Can't decode VM fault info here on SRIOV VF GPU fault detected: %d 0x%08x for process %s pid %d thread %s pid %d VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d) drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c3mc: Failed to load firmware "%s" 6[drm] Probable bad vram size: 0x%08x R600 PCIE GART already initialized 4amdgpu: No suitable DMA available 3timeout: rlcg program reg:0x%05x failed ! drivers/gpu/drm/amd/amdgpu/gmc_v9_0.cTimeout waiting for VM flush ACK! Timeout waiting for sem acquire in VM flush! No VRAM object for PCIE GART. 6[drm] PCIE GART of %uM enabled (table at 0x%016llX). [%s] %s page fault (src_id:%u ring:%u vmid:%u pasid:%u, for process %s pid %d thread %s pid %d) in page starting at address 0x%016llx from client %d VM_L2_PROTECTION_FAULT_STATUS:0x%08X For SRIOV client, shouldn't do anything. ring %s uses VM inv eng %u on hub %u 6[drm] SRAM ECC is not present. VEGA10 PCIE GART already initialized 4amdgpu: No suitable DMA available. [%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, for process %s pid %d thread %s pid %d) in page starting at address 0x%016llx from client %d GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X For SRIOV client, shouldn't do anything. drivers/gpu/drm/amd/amdgpu/gmc_v10_0.cring %u(%s) uses VM inv eng %u on hub %u Timeout waiting for VM flush ACK! Timeout waiting for sem acquire in VM flush! Warning: pre-OS buffer uses most of vram, be aware of gart table overwrite NAVI10 PCIE GART already initialized 4amdgpu: No suitable DMA available. Error flushing GPU TLB using the SDMA (%d)! No VRAM object for PCIE GART. 6[drm] PCIE GART of %uM enabled (table at 0x%016llX). error disabling interrupt (%d) Unregistered interrupt client_id: %d src_id: %d error processing interrupt (%d) Unhandled interrupt src_id: %d drivers/gpu/drm/amd/amdgpu/amdgpu_irq.cIH ring buffer overflow (0x%08X, 0x%08X, 0x%08X) IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X) IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X) PSP program IH_RB_CNTL failed! program IH_RB_CNTL_RING1 failed! program IH_RB_CNTL_RING2 failed! drivers/gpu/drm/amd/amdgpu/vega10_ih.cIH ring buffer overflow (0x%08X, 0x%08X, 0x%08X) IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X) 4[drm] failed to load ucode id (%d) 4[drm] psp command failed and response status is (0x%X) 6[drm] reserve 0x%lx from 0x%llx for PSP TMR XGMI: Failed to initialize XGMI session RAS: Failed to initialize RAS 6[drm] psp is not working correctly before mode1 reset! 6[drm] psp mode 1 reset failed! 6[drm] psp mode1 reset succeed ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p write_frame is pointing to address out of bounds psp_v3_1_ring_stop_sriov failed! 4[drm] SOS version doesn't match drivers/gpu/drm/amd/amdgpu/psp_v3_1.cpsp v3.1: Failed to load firmware "%s" 6[drm] psp mode 1 reset not supported now! ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p write_frame is pointing to address out of bounds drivers/gpu/drm/amd/amdgpu/psp_v10_0.cpsp v10.0: Failed to load firmware "%s" 6[drm] psp is not working correctly before mode1 reset! 6[drm] psp mode 1 reset failed! 6[drm] psp mode1 reset succeed ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p write_frame is pointing to address out of bounds psp_v11_0_ring_stop_sriov failed! drivers/gpu/drm/amd/amdgpu/psp_v11_0.cpsp v11.0: Failed to load firmware "%s" 6[drm] psp is not working correctly before mode1 reset! 6[drm] psp mode 1 reset failed! 6[drm] psp mode1 reset succeed ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p write_frame is pointing to address out of bounds drivers/gpu/drm/amd/amdgpu/psp_v12_0.c6[drm] Internal thermal controller %s fan control 6[drm] External GPIO thermal controller %s fan control 6[drm] ADT7473 with internal thermal controller %s fan control 6[drm] EMC2103 with internal thermal controller %s fan control 6[drm] Possible %s thermal controller at 0x%02x %s fan control 6[drm] Unknown thermal controller type %d at 0x%02x %s fan control %sabling AFMT interface @ 0x%04X for encoder 0x%x amdgpu_crtc->pflip_status = %d != AMDGPU_FLIP_SUBMITTED(%d) IH: IH event w/o asserted irq bit? No connected audio pins found! %s: Disabling hdmi deep color for %d bpc. %s: Enabling hdmi deep color 30 for 10 bpc. %s: Enabling hdmi deep color 36 for 12 bpc. Couldn't find encoder's connector Couldn't read Speaker Allocation Data Block: %d drivers/gpu/drm/amd/amdgpu/dce_v10_0.cfailed to setup AVI infoframe: %zd failed to pack AVI infoframe: %zd failed to reserve abo before unpin bad cursor width or height %d x %d Cannot find cursor object %x for crtc %d Failed to pin new cursor BO (%d) Bypassing hardware LUT due to 10 bit fb scanout. %sabling AFMT interface @ 0x%04X for encoder 0x%x amdgpu_crtc->pflip_status = %d != AMDGPU_FLIP_SUBMITTED(%d) IH: IH event w/o asserted irq bit? No connected audio pins found! %s: Disabling hdmi deep color for %d bpc. %s: Enabling hdmi deep color 30 for 10 bpc. %s: Enabling hdmi deep color 36 for 12 bpc. Couldn't find encoder's connector Couldn't read Speaker Allocation Data Block: %d drivers/gpu/drm/amd/amdgpu/dce_v11_0.cfailed to setup AVI infoframe: %zd failed to pack AVI infoframe: %zd failed to reserve abo before unpin bad cursor width or height %d x %d Cannot find cursor object %x for crtc %d Failed to pin new cursor BO (%d) Bypassing hardware LUT due to 10 bit fb scanout. [FM]set crtc %d vblank interrupt state %d amdgpu_crtc->pflip_status = %d != AMDGPU_FLIP_SUBMITTED(%d) amdgpu: could not parse disable_cu 6[drm] amdgpu: disabling CU %u.%u.%u amdgpu: disable_cu %u.%u.%u is out of range 6[drm] amdgpu: forcing compute pipe policy %d drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.cFailed to find a queue for KIQ failed to create KIQ bo (%d). (%d) reserve kiq eop bo failed failed to create ring mqd ob (%d)no memory to create MQD backup for ring %s failed to create ring mqd bo (%d)6[drm] kiq ring mec %d pipe %d q %d (%d) failed to create rlc csb bo (%d) failed to create cp table bo 6[drm] Timeout wait for RLC serdes %u,%u Unknown chip type (%d) in function gfx_v8_0_tiling_mode_table_init() falling through to CHIP_CARRIZO 6[drm] SQ general purpose intr detected:se_id %d, immed_overflow %d, host_reg_overflow %d,host_cmd_overflow %d, cmd_timestamp %d,reg_timestamp %d, thread_trace_buff_full %d,wlt %d, thread_trace %d. 6[drm] SQ %s detected: se_id %d, sh_id %d, cu_id %d, simd_id %d, wave_id %d, vm_id %d trap %s, sq_ed_info.source %s. drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c6[drm] Chained IB support enabled! gfx8: Failed to load firmware "%s" Illegal instruction in command stream Illegal register access in command stream amdgpu: failed to get ib (%d). amdgpu: ib submit failed (%d). amdgpu: fence wait failed (%d). amdgpu_irq_get() failed to get IRQ for EDC, r: %d. amdgpu_irq_get() failed to get IRQ for SQ, r: %d. amdgpu_irq_add() for SQ failed: %d (%d) create HDP EOP bo failed amdgpu: writing more dwords to the ring than expected! For SRIOV client, shouldn't do anything. amdgpu: cp failed to lock ring (%d). SQ_EDC_INFO_SOURCE_INVALID: No EDC error has occurredSQ_EDC_INFO_SOURCE_INST: EDC source is Instruction FetchSQ_EDC_INFO_SOURCE_SGPR: EDC source is SGPR or SQC data returnSQ_EDC_INFO_SOURCE_VGPR: EDC source is VGPRSQ_EDC_INFO_SOURCE_LDS: EDC source is LDSSQ_EDC_INFO_SOURCE_GDS: EDC source is GDSSQ_EDC_INFO_SOURCE_TA: EDC source is TA6[drm] Timeout wait for RLC serdes %u,%u 3timeout: rlcg program reg:0x%05x failed ! 6[drm] Instance[%d][%d]: SubBlock %s, SEC %d 6[drm] Instance[%d][%d]: SubBlock %s, DED %d 4[drm] Warning: check cp_fw_version and update it to realize GRBM requires 1-cycle delay in cp firmware gfx9: Failed to load firmware "%s" GFX Subblock %s, hardware do not support type 0x%x GFX Subblock %s, driver do not support type 0x%x RAS ERROR: unexpected block id %d drivers/gpu/drm/amd/amdgpu/amdgpu_ras.hRAS ERROR: unexpected error type %d drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c(%d) failed to create NGG buffer Illegal instruction in command stream Illegal register access in command stream amdgpu: failed to get ib (%d). amdgpu: ib submit failed (%d). amdgpu: fence wait failed (%d). amdgpu: writing more dwords to the ring than expected! amdgpu: cp failed to lock ring (%d). amdgpu: GDS workarounds failed to lock ring %s (%d). (%d) create HDP EOP bo failed (%d) create mec firmware bo failed 6[drm] fix gfx.config for vega12 Failed to create Primitive Buffer Failed to create Position Buffer Failed to create Control Sideband Buffer Failed to create Parameter Cache amdgpu: NGG failed to lock ring %s (%d). GDS_OA_PIPE_ME1_PIPE0_PIPE_MEMGDS_OA_PIPE_ME1_PIPE1_PIPE_MEMGDS_OA_PIPE_ME1_PIPE2_PIPE_MEMGDS_OA_PIPE_ME1_PIPE3_PIPE_MEMSQC_INST_BANKA_UTCL1_MISS_FIFOSQC_INST_BANKB_UTCL1_MISS_FIFOGFX_SQC_DATA_CU0_WRITE_DATA_BUFGFX_SQC_DATA_CU1_WRITE_DATA_BUFGFX_SQC_DATA_CU2_WRITE_DATA_BUFGFX_SQC_INST_BANKA_UTCL1_MISS_FIFOGFX_SQC_DATA_BANKA_DIRTY_BIT_RAMGFX_SQC_INST_BANKB_UTCL1_MISS_FIFOGFX_SQC_DATA_BANKB_DIRTY_BIT_RAMGFX_TCC_WRRET_TAG_WRITE_RETURNdrivers/gpu/drm/amd/amdgpu/gfx_v10_0.cFor SRIOV client, shouldn't do anything. failed to invalidate instruction cache rlc autoload: gc ucode autoload timeout 4[drm] Warning: check cp_fw_version and update it to realize GRBM requires 1-cycle delay in cp firmware gfx10: Failed to load firmware "%s" IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set Illegal instruction in command stream Illegal register access in command stream amdgpu: failed to get scratch reg (%ld). amdgpu: failed to get ib (%ld). amdgpu: fence wait failed (%ld). 6[drm] ib test on ring %d succeeded amdgpu: ib test failed (scratch(0x%04X)=0x%08X) amdgpu: writing more dwords to the ring than expected! amdgpu: cp failed to get scratch reg (%d). amdgpu: cp failed to lock ring %d (%d). 6[drm] ring test on %d succeeded in %d msecs 6[drm] ring test on %d succeeded in %d usecs amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X) amdgpu: cp failed to lock ring (%d). (%d) create HDP EOP bo failed (%d) failed to create mec fw bo (%d) failed to create rlc toc bo (%d) failed to create fw autoload bo (%d) failed to create pfp fw bo (%d) failed to create ce fw bo (%d) failed to create me fw bo 6[drm] gfx %d ring me %d pipe %d q %d 6[drm] compute ring %d mec %d pipe %d q %d 3SMC firmware status is not correct drivers/gpu/drm/amd/amdgpu/sdma_v2_4.cFailed to load sdma firmware! 3sdma_v2_4: Failed to load firmware "%s" Illegal instruction in SDMA command stream amdgpu: writing more dwords to the ring than expected! clamping sdma_phase_quantum to %uK clock cycles drivers/gpu/drm/amd/amdgpu/sdma_v3_0.cFailed to load sdma firmware! 3sdma_v3_0: Failed to load firmware "%s" Illegal instruction in SDMA command stream amdgpu: writing more dwords to the ring than expected! clamping sdma_phase_quantum to %uK clock cycles drivers/gpu/drm/amd/amdgpu/sdma_v4_0.crptr before shift == 0x%016llx wptr/doorbell before shift == 0x%016llx wptr before shift [%i] wptr == 0x%016llx Using doorbell -- wptr_offs == 0x%08x lower_32_bits(ring->wptr) << 2 == 0x%08x upper_32_bits(ring->wptr) << 2 == 0x%08x calling WDOORBELL64(0x%08x, 0x%016llx) Not using doorbell -- mmSDMA%i_GFX_RB_WPTR == 0x%08x mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x 6[drm] use_doorbell being set to: [%s] Illegal instruction in SDMA command stream sdma_v4_0: Failed to load firmware "%s" Failed to load sdma firmware! amdgpu: writing more dwords to the ring than expected! clamping sdma_phase_quantum to %uK clock cycles drivers/gpu/drm/amd/amdgpu/sdma_v5_0.cwptr/doorbell before shift == 0x%016llx wptr before shift [%i] wptr == 0x%016llx rptr before shift == 0x%016llx Using doorbell -- wptr_offs == 0x%08x lower_32_bits(ring->wptr) << 2 == 0x%08x upper_32_bits(ring->wptr) << 2 == 0x%08x calling WDOORBELL64(0x%08x, 0x%016llx) Not using doorbell -- mmSDMA%i_GFX_RB_WPTR == 0x%08x mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x 6[drm] use_doorbell being set to: [%s] Failed to load sdma firmware! sdma_v5_0: Failed to load firmware "%s" (%ld) failed to allocate wb slot amdgpu: failed to get ib (%ld). amdgpu: fence wait failed (%ld). 6[drm] ib test on ring %d succeeded amdgpu: ib test failed (0x%08X) amdgpu: writing more dwords to the ring than expected! (%d) failed to allocate wb slot amdgpu: dma failed to lock ring %d (%d). 6[drm] ring test on %d succeeded in %d msecs 6[drm] ring test on %d succeeded in %d usecs amdgpu: ring %d test failed (0x%08X) ring %d failed to be preempted drivers/gpu/drm/amd/amdgpu/mes_v10_1.c(%d) failed to create mes fw bo (%d) failed to create mes data fw bo only support direct fw loading on MES Register command after end of CS! Can't find BO for addr 0x%08Lx buffer (%d) to small (%d / %d)! reloc %LX-%LX crossing 256MB boundary! msg/fb buffer %LX-%LX out of 256MB segment! UVD messages must be 64 byte aligned! Failed mapping the UVD) message (%ld)! Invalid UVD decoding target pitch! Invalid dpb_size in UVD message (%d / %d)! UVD handle collision detected! Illegal UVD message type (%d)! Message needed before other commands are send! amdgpu_uvd: Can't load firmware "%s" amdgpu_uvd: Can't validate firmware "%s" 6[drm] Found UVD firmware Version: %hu.%hu Family ID: %hu POLARIS10/11 UVD firmware version %u.%u is too old. 6[drm] Found UVD firmware ENC: %hu.%hu DEC: .%hu Family ID: %hu (%d) failed to allocate UVD bo Failed setting up UVD kernel entity. UVD IB length (%d) not 16 dwords aligned! 6[drm] Cannot get clockgating state when UVD is powergated. UVD not responding, giving up!!! UVD not responding, trying to reset the VCPU!!! drivers/gpu/drm/amd/amdgpu/uvd_v5_0.camdgpu: writing more dwords to the ring than expected! amdgpu: ring failed to lock UVD ring (%d). 6[drm] UVD initialized successfully. 6[drm] Cannot get clockgating state when UVD is powergated. UVD not responding, giving up!!! UVD not responding, trying to reset the VCPU!!! 6[drm] UVD is enabled in VM mode 6[drm] UVD is enabled in physical mode 6[drm] UVD ENC is enabled in VM mode drivers/gpu/drm/amd/amdgpu/uvd_v6_0.camdgpu: writing more dwords to the ring than expected! amdgpu: ring failed to lock UVD ring (%d). 6[drm] UVD and UVD ENC initialized successfully. 6[drm] UVD initialized successfully. For SRIOV client, shouldn't do anything. 6[drm] UVD(%d) is enabled in VM mode 6[drm] UVD(%d) ENC is enabled in VM mode 6[drm] PSP loading UVD firmware drivers/gpu/drm/amd/amdgpu/uvd_v7_0.camdgpu: writing more dwords to the ring than expected! failed to init MMSCH, mmVCE_MMSCH_VF_MAILBOX_RESP = %x UVD(%d) not responding, giving up!!! UVD(%d) not responding, trying to reset the VCPU!!! amdgpu: (%d)ring failed to lock UVD ring (%d). 6[drm] UVD and UVD ENC initialized successfully. Can't find BO for addr 0x%010Lx %d %d %d %d BO to small for addr 0x%010Lx %d %d VCE handle collision detected! amdgpu_vce: Can't load firmware "%s" amdgpu_vce: Can't validate firmware "%s" 6[drm] Found VCE firmware Version: %hhd.%hhd Binary ID: %hhd (%d) failed to allocate VCE bo Failed setting up VCE run queue. (%d) failed to reserve VCE bo Error destroying VCE handle (%d)! invalid VCE command length (%d)! no session command at start of IB New session without create command! amdgpu: writing more dwords to the ring than expected! drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c6[drm] VCE enabled in VM mode 6[drm] VCE enabled in physical mode 6[drm] Cannot get clockgating state when VCE is powergated. VCE not responding, trying to reset the ECPU!!! VCE not responding, giving up!!! 6[drm] VCE initialized successfully. amdgpu: writing more dwords to the ring than expected! VCE not responding, trying to reset the ECPU!!! VCE not responding, giving up!!! For SRIOV client, shouldn't do anything. 6[drm] PSP loading VCE firmware 6[drm] VCE enabled in VM mode amdgpu: writing more dwords to the ring than expected! drivers/gpu/drm/amd/amdgpu/vce_v4_0.cfailed to init MMSCH, mmVCE_MMSCH_VF_MAILBOX_RESP = %x 6[drm] VCE initialized successfully. amdgpu_vcn: Can't load firmware "%s" amdgpu_vcn: Can't validate firmware "%s" 6[drm] Found VCN firmware Version ENC: %hu.%hu DEC: %hu VEP: %hu Revision: %hu 6[drm] Found VCN firmware Version: %hu.%hu Family ID: %hu (%d) failed to allocate vcn bo (%d) failed to allocate DPG bo amdgpu: writing more dwords to the ring than expected! 4[drm] Register(%d) [%s] failed to reach value 0x%08x != 0x%08x 6[drm] PSP loading VCN firmware dpg pause state changed %d:%d -> %d:%d6[drm] VCN decode is enabled in VM mode 6[drm] VCN encode is enabled in VM mode 6[drm] VCN jpeg decode is enabled in VM mode 6[drm] VCN decode and encode initialized successfully(under %s). drivers/gpu/drm/amd/amdgpu/vcn_v1_0.camdgpu: writing more dwords to the ring than expected! VCN decode not responding, giving up!!! VCN decode not responding, trying to reset the VCPU!!! 4[drm] Register(%d) [%s] failed to reach value 0x%08x != 0x%08x 6[drm] VCN decode and encode initialized successfully(under %s). amdgpu: JPEG disable power gating failed 6[drm] PSP loading VCN firmware dpg pause state changed %d -> %d6[drm] VCN decode is enabled in VM mode 6[drm] VCN encode is enabled in VM mode 6[drm] VCN jpeg decode is enabled in VM mode amdgpu: JPEG enable power gating failed drivers/gpu/drm/amd/amdgpu/vcn_v2_0.camdgpu: writing more dwords to the ring than expected! VCN decode not responding, giving up!!! VCN decode not responding, trying to reset the VCPU!!! 4[drm] Register(%d) [%s] failed to reach value 0x%08x != 0x%08x 6[drm] VCN decode and encode initialized successfully. VCN decode not responding, giving up!!! VCN decode not responding, trying to reset the VCPU!!! 6[drm] PSP loading VCN firmware 6[drm] VCN(%d) decode is enabled in VM mode 6[drm] VCN(%d) encode is enabled in VM mode 6[drm] VCN(%d) jpeg decode is enabled in VM mode kfd not supported on this ASIC failed to allocate BO for amdkfd (%d) (%d) failed to pin bo for amdkfd (%d) failed to map bo to kernel for amdkfd (%d) failed to reserve bo for amdkfd failed to allocate gws BO for amdkfd (%d) Address base: %pap limit %pap public 0x%llx private 0x%llx amdgpu: failed to get xgmi hops count between node %d and %d. ret = %d 3Invalid engine in IB submission: %d amdgpu: failed to schedule IB. drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c3sched_policy has invalid value 3max_num_of_queues_per_device must be between 1 to KFD_MAX_NUM_OF_QUEUES_PER_DEVICE Failed to resume IOMMU for device %x:%x Error starting queue manager for device %x:%x drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device.cgtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p DID %04x is missing in supported_devices skipped device %x:%x, PCI rejects atomics Error initializing gtt sub-allocator Error initializing doorbell aperture Error initializing interrupts Error initializing queue manager Error adding device to topology Starting kfd with the following scheduling policy %d device %x:%x NOT added due to errors KFD suspend / resume ref. errorAllocated mem_obj = %p for size = %d range_start = %d, range_end = %d Allocation failed with mem_obj = %p Free mem_obj = %p, range_start = %d, range_end = %d Compute profile ref. count errorprocess %d opened, compat mode (32 bit) - %d Process %d (32-bit) failed to open /dev/kfd 32-bit processes are not supported by amdkfd 3Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE 3Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY 3Can't access ring base address 3Ring size must be a power of 2 or 0 Can't access ctx save restore bufferQueue Address: 0x%llX, 0x%llX 3Process device data doesn't exist kfd_ioctl_dbg_register not supported on CZ 3Getting device by id failed in %s 3Can't find BO, offset is 0x%llx 3Failed to map event page to kernel Updating queue id %d for pasid %d Destroying queue id %d for pasid %d Buffer overflow detected (%d < %lu)! kfd_ioctl_dbg_wave_control not supported on CZ size mismatch, computed : actual %u : %u Calling dbg manager process %p, operand %u, mode %u, trapId %u, message %u Returned status of dbg manager is %ld Creating queue for PASID %d on gpu 0x%x Queue id %d was created successfully Ring buffer address == 0x%016llX Read ptr address == 0x%016llX Write ptr address == 0x%016llX Process %d mapping mmio page target user address == 0x%08llX physical address == 0x%08llX vm_flags == 0x%04lX size == 0x%04lX ioctl cmd 0x%x (#%d), arg 0x%lx invalid ioctl: pid=%d, cmd=0x%02x, nr=0x%02x kfd_ioctl_dbg_unregister not supported on CZ num_cu_mask 0x%x must be a multiple of 32CU mask cannot be greater than 1024 bitsCould not copy CU mask from userspace3Failed to unmap from gpu %d/%d Getting device by id failed for 0x%x Sync memory failed, wait interrupted by user signal drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_chardev.cSimulate large-bar allocation on non large-bar machine 3Alloc host visible vram on small bar is not allowed AMDKFD_IOC_GET_PROCESS_APERTURESAMDKFD_IOC_SET_SCRATCH_BACKING_VAAMDKFD_IOC_GET_PROCESS_APERTURES_NEWAMDKFD_IOC_ALLOC_MEMORY_OF_GPUAMDKFD_IOC_UNMAP_MEMORY_FROM_GPUAMDKFD_IOC_GET_QUEUE_WAVE_STATE6Topology: Add APU node [0x%0x:0x%0x] 6Topology: Add dGPU node [0x%0x:0x%0x] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_topology.c6Creating topology SYSFS entries 3No memory to allocate a topology device6Ignoring ACPI CRAT on non-APU system 3Error creating VCRAT table for CPU 3Error parsing VCRAT table for CPU 6Finished initializing topology 3Failed to update topology in sysfs ret=%d Adding new GPU (ID: 0x%x) to topology 3Error creating VCRAT for GPU (ID: 0x%x) 3Error parsing VCRAT for GPU (ID: 0x%x) 3Failed to update GPU (ID: 0x%x) to sysfs topology. res=%d Adding doorbell packet type capability 4Invalid NUMA Node. Use online CPU mask doorbell base == 0x%08lX doorbell_id_offset == 0x%08lX doorbell_process_limit == 0x%08lX doorbell_kernel_offset == 0x%08lX doorbell aperture size == 0x%08lX doorbell kernel address == %p Mapping doorbell page target user address == 0x%08llX physical address == 0x%08llX vm_flags == 0x%04lX size == 0x%04lX Get kernel queue doorbell doorbell offset == 0x%08X doorbell index == 0x%x Writing %d to doorbell address %p drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_doorbell.cwriting %llu to doorbell address %p 3Failed to create process device data drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_flat_memory.cdrivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_process.cReleasing pdd (topology id %d) for process (pasid %d) Sync memory failed, wait interrupted by user signal 3Failed to create process VM object set tba :0x%llx, tma:0x%llx, cwsr_kaddr:%p for pqm. 4Could not create procfs proc folder3Failure to set tba address. error %d. 4Creating procfs kobject failed4Creating procfs pid directory failed4Creating pasid for pid %d failed3Failed to init doorbell for process reserved doorbell 0x%03x and 0x%03x 3Process device data doesn't exist 3Failed to evict process queues 3Failed to evict queues of pasid %d 3Failed to restore process queues Failed to restore BOs of pasid %d, retry after %d ms reschedule restore work failed 3Failed to restore queues of pasid %d 3Failed to suspend process %d 3Restore process %d failed during resume 3Incorrect CWSR mapping size. 3Error allocating per process CWSR buffer. drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_queue.cdrivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager.c3Exceeded KFD_MAX_NUM_SE, chip reports %d 3Exceeded KFD_MAX_NUM_SH, chip reports %d Update cu mask to %#x %#x %#x %#x drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_cik.ccp_hqd_pq_doorbell_control 0x%x Update cu mask to %#x %#x %#x %#x drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_vi.ccp_hqd_pq_doorbell_control 0x%x update cu mask to %#x %#x %#x %#x %#x %#x %#x %#x drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_v9.ccp_hqd_pq_doorbell_control 0x%x update cu mask to %#x %#x %#x %#x drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_v10.cdrivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_kernel_queue.cInitializing queue type %d size %d 3Failed to initialize doorbell3Failed to init pq queues size %d 3Failed to init kernel queue drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_kernel_queue_vi.cdrivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_kernel_queue_v9.cdrivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_kernel_queue_v10.cdrivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_packet_manager.c3Failed to allocate buffer on kernel queue 3Failed to allocate runlist IB Building runlist ib process count: %d queues count %d Not enough space left in runlist IB static_queue, mapping kernel q %d, is debug status %d static_queue, mapping user queue %d, is debug status %d Finished map process and queues to runlist 4Runlist is getting oversubscribed. Expect reduced ROCm performance. 6Submitting %x %x %x %x %x %x %x to HIQ to hang the HWS.3Queue id does not match any known queue drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_process_queue_manager.c3Process device data doesn't exist 6Cannot open more queues for process with pasid %d Over-subscription is not allowed for SDMA. DQM returned %d for create_queue Over-subscription is not allowed when amdkfd.sched_policy == 1 3Pasid %d DQM create queue %d failed. ret %d 3Pasid %d destroy queue %d failed, ret %d No queue %d exists for update operation amdkfd: No queue %d exists for operation Bad user queue type %d on device %x Bad kernel queue type %d on device %x Weird: Queue node with neither kernel nor user queue drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager.cq->properties.type %d is invalid 4Resetting wave fronts (nocpsch) on dev %p sh_mem_config: 0x%x, ape1_base: 0x%x, ape1_limit: 0x%x 4Can't create new usermode queue because %d queues were already created Loading mqd to hqd on pipe %d, queue %d should only run in user threadTotal of %d queues are accountable so far 3qcm fence wait loop timeout expired Before destroying queues, sdma queue count is : %u, xgmi sdma queue count is : %u 3The cp might be in an unrecoverable state due to an unsuccessful queues preemption 3Invalid queue enabled by amdgpu: %d Scheduling resources: vmid mask: 0x%8X queue mask: 0x%8llX 4Can't create new kernel queue because %d queues were already created 4Resetting wave fronts (cpsch) on dev %p 3Invalid scheduling policy %d 3mqd manager [%d] initialization failed 3Failed to allocate hiq sdma mqd trunk buffer HIQ on MEC %d Pipe %d Queue %d drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_cik.cis32bit process: %d sh_mem_bases nybble: 0x%X and register 0x%X drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_vi.cis32bit process: %d sh_mem_bases nybble: 0x%X and register 0x%X sh_mem_bases nybble: 0x%X and register 0x%X drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_v9.cdrivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_v10.cdrivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_interrupt.cFailed to allocate KFD IH workqueue Interrupt ring overflow, dropping interrupt %d Sending SIGSEGV to HSA Process with PID %d Sending SIGTERM to HSA Process with PID %d HSA Process (PID %d) got unhandled exception4Signal event wasn't created because limit was reached 4Signal event wasn't created because out of kernel memory Allocated new event signal page at %p, for process %p Signal event number %zu created with id %d, address %p Partial ID invalid: %u (%u valid bits) drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_events.c3Event page mmap requested illegal size Signal page could not be found start user address == 0x%08lx end user address == 0x%08lx pfn == 0x%016lX vm_flags == 0x%08lX size == 0x%08lX notpresent %d, noexecute %d, readonly %d FW bug: No PASID in KFD interruptdrivers/gpu/drm/amd/amdgpu/../amdkfd/cik_event_interrupt.cclient id 0x%x, source id %d, vmid %d, pasid 0x%x. raw data: %8X, %8X, %8X, %8X, %8X, %8X, %8X, %8X. Bug: No PASID in KFD interruptdrivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v9.c3Failed to get pdd for wave control no DIQ 3num_watch_points is invalid 3adw_info fields are not valid * * * * * * * * * * * * * * * * * *DIQ Created with queue id: %d 3Failed to set wave control registers drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_dbgdev.c3acquire_packet_buffer failed 3Failed to allocate GART memory Killing all process wavefronts Killing wave fronts of vmid %d and pasid %d 3Didn't find vmid for pasid %d drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_dbgmgr.c3Failed to allocate dbgmgr instance 3Failed to allocate dbgdev instance H/W debugger is already active using pasid %d H/W debugger is not registered by calling pasid %d H/W debugger support was not registered for requester pasid %d Found CU entry in CRAT table with proximity_domain=%d caps=%x Found memory entry in CRAT table with proximity_domain=%d Found cache entry in CRAT table with processor_id=%d Found TLB entry in CRAT table (not processing) Found CCOMPUTE entry in CRAT table (not processing) Found IO link entry in CRAT table with id_from=%d, id_to %d 4DSDT table not found for OEM information 6Virtual CRAT table created for CPU Fill gpu memory affinity - type 0x%x size 0x%llx 6Virtual CRAT table created for GPU 4Error device list should be empty 6Parsing CRAT table with %d nodes 6CRAT table disabled by module option 3VCRAT not implemented for APU drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_crat.cInvalid PPR device %x:%x.%x pasid %d address 0x%lX flags 0x%Xdrivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_iommu.cUnbinding process %d from IOMMU error getting iommu info. is the iommu enabled? error required iommu flags ats %i, pri %i, pasid %i 3Binding PDD_BOUND_SUSPENDED pdd is unexpected! 3Unexpected pasid %d binding failure drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.cdrivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c3kfd2kgd: amdgpu: failed to validate PT BOs 3kfd2kgd: amdgpu: failed to validate PD 3kfd2kgd: amdgpu: failed to kmap PD, ret=%d kfd2kgd: remove VA 0x%llx - 0x%llx in entry %p 3kfd2kgd: Invalid VA when adding BO to VM kfd2kgd: add VA 0x%llx - 0x%llx to vm %p 3kfd2kgd: Failed to add BO object to VM. ret == %d 3kfd2kgd: validate_pt_pd_bos() failed 3kfd2kgd: amdgpu_vm_bo_update failed 3kfd2kgd: Failed to reserve buffers in ttm. kfd system memory accounting unbalancedkfd TTM memory accounting unbalanced3kfd2kgd: Failed to create eviction fence 3kfd2kgd: %s: Failed to allocate PD BO list entries 3kfd2kgd: %s: failed to validate BO 3kfd2kgd: %s: update PTE failed 3kfd2kgd: %s: Failed to invalidate userptr BO kfd2kgd: %s: Failed to get user pages: %d 3kfd2kgd: %s: Failed to resume KFD kfd2kgd: Kernel memory limit %lluM, TTM limit %lluM 3kfd2kgd: Failed init vm ret %d kfd2kgd: Destroying process vm %p kfd2kgd: Releasing process vm %p kfd2kgd: Insufficient system memory kfd2kgd: create BO VA 0x%llx size 0x%llx domain %s kfd2kgd: Failed to create BO on domain %s. ret %d 3kfd2kgd: %s: Failed to set userptr: %d 3kfd2kgd: %s: Failed to register MMU notifier: %d 3kfd2kgd: %s: Failed to get user pages: %d 3kfd2kgd: %s: Failed to reserve BO kfd2kgd: BO VA 0x%llx size 0x%lx is still mapped. kfd2kgd: Release VA 0x%llx - 0x%llx 3kfd2kgd: Invalid BO when mapping memory to GPU kfd2kgd: Map VA 0x%llx - 0x%llx to vm %p domain %s 3kfd2kgd: Failed to reserve buffers in ttm kfd2kgd: map VA 0x%llx - 0x%llx in entry %p 3kfd2kgd: Failed to map VA 0x%llx in vm. ret %d 3kfd2kgd: update_gpuvm_pte() failed 3kfd2kgd: Failed to update page directories kfd2kgd: INC mapping count %d 3kfd2kgd: Failed to map bo to gpuvm kfd2kgd: Unmap VA 0x%llx - 0x%llx from vm %p kfd2kgd: unmap VA 0x%llx - 0x%llx from entry %p kfd2kgd: DEC mapping count %d 3kfd2kgd: userptr can't be mapped to kernel 3kfd2kgd: Failed to pin bo. ret %d 3kfd2kgd: Failed to map bo to kernel. ret %d 3kfd2kgd: Failed to reserve bo. ret %d 3kfd2kgd: Failed to quiesce KFD kfd2kgd: Memory eviction: TTM Reserve Failed. Try again kfd2kgd: Memory eviction: Failed to sync to PD BO moving fence. Try again kfd2kgd: Memory eviction: Validate BOs failed. Try again kfd2kgd: Memory eviction: Sync BO fence failed. Try again kfd2kgd: Memory eviction: update PTE failed. Try again kfd2kgd: Memory eviction: update PDs failed. Try again 3kfd2kgd: GWS BO validate failed %d 3kfd2kgd: Reserve gws bo failed %d Memory eviction: update PDs failed. Try again Memory eviction: update PTE failed. Try again Memory eviction: Sync BO fence failed. Try again Memory eviction: Validate BOs failed. Try again Memory eviction: Failed to sync to PD BO moving fence. Try again Memory eviction: TTM Reserve Failed. Try again %s: Failed to get user pages: %d unmap VA 0x%llx - 0x%llx from entry %p Unmap VA 0x%llx - 0x%llx from vm %p map VA 0x%llx - 0x%llx in entry %p Map VA 0x%llx - 0x%llx to vm %p domain %s BO VA 0x%llx size 0x%lx is still mapped. Failed to create BO on domain %s. ret %d create BO VA 0x%llx size 0x%llx domain %s remove VA 0x%llx - 0x%llx in entry %p add VA 0x%llx - 0x%llx to vm %p Kernel memory limit %lluM, TTM limit %lluM 3trying to set page table base for wrong VMID kfd: set HIQ, mec:%d, pipe:%d, queue:%d. 3CP HQD IQ timer status time out 3CP HQD dequeue request time out 3cp queue preemption time out. drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c3kfd2kgd: timeout: rlcg program reg:0x%05x failed ! kfd2kgd: kfd: set HIQ, mec:%d, pipe:%d, queue:%d. 3kfd2kgd: cp queue preemption time out. 3kfd2kgd: trying to set page table base for wrong VMID %u kfd2kgd: sdma base address: 0x%x drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.camdgpu: writing more dwords to the ring than expected! wait for kiq fence error: %ld. kfd: set HIQ, mec:%d, pipe:%d, queue:%d. kfd2kgd: sdma base address: 0x%x drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c3kfd2kgd: trying to set page table base for wrong VMID %u kfd2kgd: pasid 0x%x vmid %d, reg value %x kfd2kgd: update mapping for IH block and mmhub3kfd2kgd: cp queue preemption time out. kfd2kgd: Load hqd of pipe %d queue %d kfd2kgd: kfd: set HIQ, mec:%d, pipe:%d, queue:%d. kfd2kgd: %s setting CP_PQ_WPTR_POLL_CNTL1 to %x drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.ckfd2kgd: sdma base address: 0x%x kfd2kgd: sdma dump engine id %d queue_id %d kfd2kgd: sdma load base addr %x for engine %d, queue %d amdgpu: writing more dwords to the ring than expected! wait for kiq fence error: %ld. sdma dump engine id %d queue_id %d sdma load base addr %x for engine %d, queue %d %s setting CP_PQ_WPTR_POLL_CNTL1 to %x kfd: set HIQ, mec:%d, pipe:%d, queue:%d. update mapping for IH block and mmhubpasid 0x%x vmid %d, reg value %x 3trying to set page table base for wrong VMID 3CP HQD IQ timer status time out 3CP HQD dequeue request time out 3cp queue preemption time out drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.cfirmware type %d do not have version audio endpt register access not implemented. Invalid indirect register spacedrivers/gpu/drm/amd/amdgpu/amdgpu_cgs.cCouldn't allocate CGS device structure ring %s timeout, but soft recovered ring %s timeout, signaled seq=%u, emitted seq=%u Process information: process %s pid %d thread %s pid %d drivers/gpu/drm/amd/amdgpu/amdgpu_job.cFailed to remove dev from genpd %d Failed to add dev to genpd %d failed to evaluate ATPX got %s 6vga_switcheroo: detected switching method %s handle ATPX buffer is too small: %zu ATPX version %u, functions 0x%08x ATPX Hybrid Graphics, forcing to ATPX failed to evaluate ATCS got %s failed to evaluate ATIF got %s bad object returned from ATIF: %d event, device_class = %s, type = %#x ATIF: %d pending SBIOS requests 6[drm] ATCS buffer is too small: %zu Call to ATCS verify_interface failed: %d 4[drm] Not enough memory to initialize ATIF 6[drm] ATIF buffer is too small: %zu Call to ATIF verify_interface failed: %d SYSTEM_PARAMS: mask = %#x, flags = %#x Notification %s, command code = %#x Call to GET_SYSTEM_PARAMS failed: %d Call to QUERY_BACKLIGHT_TRANSFER_CHARACTERISTICS failed: %d (%ld) failed to wait for user bo 3%s(0x%04x) aborted; SMU still servicing msg (0x%04x) %s(0x%04x, %#x) timed out after %lld us drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/smu8_smumgr.c3SMU check loaded firmware failed. 4amdgpu: [powerplay] can't get the mac value %x 4amdgpu: [powerplay] can't get the offset of type %x member %x Stretch Amount in PPTable not supportedError calling VBIOS to set DRAM_TIMING.3amdgpu: [powerplay] SMU Firmware start failed Error retrieving Engine Clock dividers from VBIOS.can not find VDDC voltage value for VDDC engine clock dependency tableThere must be 1 or more PCIE levels defined in PPTable.3amdgpu: [powerplay] Pcie Dpm Enablemask is 0 !Failed to upload MC reg table !Failed to program memory timing parameters !can not populate memory level as memory clock is zerocan not find MinVddc voltage value from memory VDDC voltage dependency tableError retrieving Memory Clock Parameters from VBIOS.Failed to initialize Graphics Level !Failed to initialize Memory Level !Failed to initialize ACPI Level !can not find divide id for VCE engine clockFailed to initialize VCE Level !can not find divide id for engine clockFailed to initialize ACP Level !Failed to Write ARB settings for the initial state.can not find divide id for Vclk clockcan not find divide id for Dclk clock3amdgpu: [powerplay] [powerplay] VBIOS did not find boot engine clock value in dependency table. Using Graphics DPM level 0 !3amdgpu: [powerplay] [powerplay] VBIOS did not find boot engine clock value in dependency table.Using Memory DPM level 0 !Target Operating Temp is out of Range !Failed to populate Clock Stretcher Data Table !3amdgpu: [powerplay] VDDC and VDDGFX should be both on SVI2 control in splitted mode ! 3amdgpu: [powerplay] VDDC should be on SVI2 control in merged mode ! Failed to upload dpm data to SMC memory !Failed to upload arb data to SMC memory !Attempt to get pm_fuse_table_offset Failed !Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed !Attempt to populate TdcWaterfallCtl Failed !Attempt to download PmFuseTable Failed !Index of mc_reg_table->address[] array out of boundaryFailed to initialize MCRegTable for the MC register addresses !Failed to initialize MCRegTable for driver state !Failed to populate initialize MC Reg table !Failed to initialize UVD Level !MVDD Voltage is outside the supported range.4amdgpu: [powerplay] can't get the mac of %x 4amdgpu: [powerplay] can't get the offset of type %x member %x Stretch Amount in PPTable not supportedError calling VBIOS to set DRAM_TIMING.[AVFS][Fiji_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table[AVFS][Fiji_SetupGfxLvlStruct] Problems copying vr_config value over to SMC[AVFS][Fiji_SetupGfxLvlStruct] Copying of DPM table failed![AVFS][fiji_avfs_event_mgr] Could not Copy Graphics Level table over to SMU[AVFS][fiji_avfs_event_mgr] Could not setup Pwr Virus for AVFS 6amdgpu: [powerplay] [AVFS][Fiji_PerformBtc] PerformBTC SMU msg failed[AVFS][fiji_avfs_event_mgr] Failure at fiji_start_avfs_btc. AVFS Disabledcan not populate memory level as memory clock is zerocan not find MinVddc voltage value from memory VDDC voltage dependency tableFailed to get Memory PLL Dividers.Error retrieving Engine Clock dividers from VBIOS.There must be 1 or more PCIE levels defined in PPTable.can not find VDDC voltage value for VDDC engine clock dependency tableFailed to program memory timing parameters!Failed to initialize Graphics Level!Failed to initialize Memory Level!Cannot find ACPI VDDC voltage value in Clock Dependency TableCannot find ACPI VDDCI voltage value in Clock Dependency TableMVDD Voltage is outside the supported range.Failed to initialize ACPI Level!can not find divide id for VCE engine clockFailed to initialize VCE Level!can not find divide id for engine clockFailed to initialize ACP Level!Failed to Write ARB settings for the initial state.can not find divide id for Vclk clockcan not find divide id for Dclk clockFailed to initialize UVD Level!Target Operating Temp is out of Range!Failed to populate Clock Stretcher Data Table!VDDC should be on SVI2 control in merged mode!Failed to upload dpm data to SMC memory!Failed to upload arb data to SMC memory!Attempt to get pm_fuse_table_offset Failed!Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!Attempt to populate TdcWaterfallCtl, LPMLTemperature Min and Max Failed!Attempt to download PmFuseTable Failed!Failed to populate PM fuses to SMC memory!Failed to setup dpm led config4amdgpu: [powerplay] can't get the mac of %x 4amdgpu: [powerplay] can't get the offset of type %x member %x Error calling VBIOS to set DRAM_TIMING.[AVFS][Polaris10_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table[AVFS][Polaris10_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC[AVFS][Polaris10_SetupGfxLvlStruct] Copying of SCLK DPM table failed![AVFS][Polaris10_SetupGfxLvlStruct] Copying of MCLK DPM table failed![AVFS][Polaris10_SetupGfxLvlStruct] Copying of DPM table failed![AVFS][Polaris10_AVFSEventMgr] Could not Copy Graphics Level table over to SMU6amdgpu: [powerplay] [AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting.[AVFS][Polaris10_AVFSEventMgr] Could not setup Pwr Virus for AVFS 6amdgpu: [powerplay] [AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed[AVFS][Polaris10_AVFSEventMgr] Failure at SmuPolaris10_PerformBTC. AVFS DisabledMVDD Voltage is outside the supported range.can not populate memory level as memory clock is zerocan not find MinVddc voltage value from memory VDDC voltage dependency tableThere must be 1 or more PCIE levels defined in PPTable.can not find VDDC voltage value for VDDC engine clock dependency tableFailed to update SCLK threshold!Failed to program memory timing parameters!Failed to initialize Graphics Level!Failed to initialize Memory Level!Cannot find ACPI VDDC voltage value in Clock Dependency TableError retrieving Engine Clock dividers from VBIOS.Cannot find ACPI VDDCI voltage value in Clock Dependency TableFailed to initialize ACPI Level!can not find divide id for VCE engine clockFailed to initialize VCE Level!Failed to Write ARB settings for the initial state.can not find divide id for Vclk clockcan not find divide id for Dclk clockFailed to initialize UVD Level!Target Operating Temp is out of Range!Stretch Amount in PPTable not supportedFailed to populate Clock Stretcher Data Table!Failed to populate AVFS Parameters!VDDC should be on SVI2 control in merged mode!Can not find DFS divide id for SclkFailed to upload dpm data to SMC memory!Failed to upload arb data to SMC memory!Attempt to get pm_fuse_table_offset Failed!Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!Attempt to populate TdcWaterfallCtl, LPMLTemperature Min and Max Failed!Attempt to download PmFuseTable Failed!Failed to populate PM fuses to SMC memory!4amdgpu: [powerplay] can't get the mac of %x 4amdgpu: [powerplay] can't get the offset of type %x member %x Error retrieving Engine Clock dividers from VBIOS.can not find VDDC voltage value for VDDC engine clock dependency tableError calling VBIOS to set DRAM_TIMING.The SCLK/VDDC Dependency Table does not exist.4amdgpu: [powerplay] CAC Leakage Table does not exist, using vddc. 4amdgpu: [powerplay] Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index, using maximum index from CAC table. 4amdgpu: [powerplay] Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index in second look up, using maximum index from CAC table.4amdgpu: [powerplay] Unable to get std_vddc from SCLK/VDDC Dependency Table, using vddc. Failed to upload MC reg table!Failed to program memory timing parameters!3amdgpu: [powerplay] [ powerplay ] SMC ucode is not 4 bytes aligned 3amdgpu: [powerplay] [ powerplay ] SMC address is beyond the SMC RAM area SMC address is beyond the SMC RAM area.SMC size must be divisible by 4.can not populate memory level as memory clock is zerocan not find MinVddc voltage value from memory VDDC voltage dependency tablecan not find MinVddci voltage value from memory VDDCI voltage dependency tableError retrieving Memory Clock Parameters from VBIOS.4amdgpu: [powerplay] Unknown V.I. Device ID. do not populate SMC VDDC voltage tablecan not populate VDDC voltage table to SMCdo not populate SMC VDDCI voltage tablecan not populate VDDCI voltage table to SMCdo not populate SMC mvdd voltage tablecan not populate MVDD voltage table to SMCFailed to initialize ULV state!Failed to initialize Graphics Level!Failed to initialize Memory Level!Failed to initialize ACPI Level!Failed to Write ARB settings for the initial state.3amdgpu: [powerplay] VBIOS did not find boot engine clock value in dependency table. Using Graphics DPM level 0! 3amdgpu: [powerplay] VBIOS did not find boot engine clock value in dependency table. Using Memory DPM level 0! SVI2 domain configuration is incorrect!Failed to populate SVI2 setting!Failed to upload dpm data to SMC memory!Index of mc_reg_table->address[] array out of boundaryFailed to initialize MCRegTable for the MC register addresses!Failed to initialize MCRegTable for driver state!Failed to populate initialize MC Reg table!Attempt to get pm_fuse_table_offset Failed!The CAC Leakage table does not exist!There should never be more than 8 entries for BapmVddcVid!!!CACLeakageTable->count and VddcDependencyOnSCLk->count not equalIceland should always support EVVAttempt to populate bapm vddc vid Failed!There should never be more than 8 entries for VddcVid!!!Attempt to populate vddc vid Failed!Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!Attempt to populate TdcWaterfallCtl, LPMLTemperature Min and Max Failed!Attempt to download PmFuseTable Failed!Failed to populate PM fuses to SMC memory!MVDD Voltage is outside the supported range.SMC address must be 4 byte aligned.SMC addr is beyond the SMC RAM area.SMC address is beyond the SMC RAM area.amdgpu: [powerplay] last message was not supported 6amdgpu: [powerplay] last message was failed ret is %d amdgpu: [powerplay] message %x was not supported 6amdgpu: [powerplay] failed to send message %x ret is %d 6amdgpu: [powerplay] Failed to send Message. 3amdgpu: [powerplay] SMU load firmware failed SMC size must be divisible by 4.drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/smu7_smumgr.clast message was not supported Attempt to get SMC IF Version Number Failed!3amdgpu: [powerplay] Your firmware(0x%x) doesn't match SMU9_DRIVER_IF_VERSION(0x%x). Please update your firmware! Failed to verify SMC interface!3amdgpu: [powerplay] Attempt to read SMC IF Version Number Failed! 6amdgpu: [powerplay] failed to send message %x ret is %d amdgpu: [powerplay] can't get the mac of %x amdgpu: [powerplay] can't get the offset of type %x member %x 3amdgpu: [powerplay] smc_addr invalid 3amdgpu: [powerplay] smc_start_address invalid Error retrieving Engine Clock dividers from VBIOS.3amdgpu: [powerplay] vdd_dep_on_sclk table is NULL 6amdgpu: [powerplay] Engine clock can't satisfy stutter requirement! Error calling VBIOS to set DRAM_TIMING.The SCLK/VDDC Dependency Table does not exist. 4amdgpu: [powerplay] CAC Leakage Table does not exist, using vddc. 4amdgpu: [powerplay] Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index, using maximum index from CAC table. 4amdgpu: [powerplay] Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index in second look up, using maximum index from CAC table.4amdgpu: [powerplay] Unable to get std_vddc from SCLK/VDDC Dependency Table, using vddc. Failed to upload MC reg table!Failed to program memory timing parameters!can not populate memory level as memory clock is zerocan not find MinVddc voltage value from memory VDDC voltage dependency tablecan not find MinVddci voltage value from memory VDDCI voltage dependency tablecan not find MinVddci voltage value from memory MVDD voltage dependency tableError retrieving Memory Clock Parameters from VBIOS.do not populate SMC VDDC voltage tablecan not populate VDDC voltage table to SMCdo not populate SMC VDDCI voltage tablecan not populate VDDCI voltage table to SMCdo not populate SMC mvdd voltage tablecan not populate MVDD voltage table to SMCFailed to initialize ULV state!Failed to initialize Graphics Level!Failed to initialize Memory Level!Failed to initialize ACPI Level!can not find divide id for VCE engine clockFailed to initialize VCE Level!can not find divide id for engine clockFailed to initialize ACP Level!Failed to Write ARB settings for the initial state.can not find divide id for Vclk clockcan not find divide id for Dclk clock3amdgpu: [powerplay] VBIOS did not find boot engine clock value in dependency table. Using Graphics DPM level 0! 3amdgpu: [powerplay] VBIOS did not find boot engine clock value in dependency table. Using Memory DPM level 0! There must be 1 or more PCIE levels defined in PPTable.6amdgpu: [powerplay] VDDCshould be on SVI2 controller!Failed to upload dpm data to SMC memory!Index of mc_reg_table->address[] array out of boundaryFailed to initialize MCRegTable for the MC register addresses!Failed to initialize MCRegTable for driver state!Failed to populate initialize MC Reg table!3amdgpu: [powerplay] Attempt to get pm_fuse_table_offset Failed! The CAC Leakage table does not exist!There should never be more than 8 entries for BapmVddcVid!!!CACLeakageTable->count and VddcDependencyOnSCLk->count not equalThere should never be more than 8 entries for VddcVid!!!Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!Failed to populate PM fuses to SMC memory!Failed to initialize UVD Level!MVDD Voltage is outside the supported range.6amdgpu: [powerplay] smc is running, no need to load smc firmware 3amdgpu: [powerplay] SMC address is beyond the SMC RAM area. 3amdgpu: [powerplay] SMC size must be divisible by 4 drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/ci_smumgr.ccan't get the offset of type %x member %x [CopyTableFromSMC] Attempt to Set Dram Addr High Failed![CopyTableFromSMC] Attempt to Set Dram Addr Low Failed![CopyTableFromSMC] Attempt to Transfer Table From SMU Failed![CopyTableToSMC] Attempt to Set Dram Addr High Failed![CopyTableToSMC] Attempt to Set Dram Addr Low Failed![CopyTableToSMC] Attempt to Transfer Table To SMU Failed![EnableDisableSMCFeatures] Attemp to enable SMU features Low failed![EnableDisableSMCFeatures] Attemp to enable SMU features High failed![EnableDisableSMCFeatures] Attemp to disable SMU features Low failed![EnableDisableSMCFeatures] Attemp to disable SMU features High failed![GetEnabledSMCFeatures] Attemp to get SMU features Low failed![GetEnabledSMCFeatures] Attemp to get SMU features High failed!4amdgpu: [powerplay] can't get the mac of %x 4amdgpu: [powerplay] can't get the offset of type %x member %x VBIOS fan info is not correct!Error calling VBIOS to set DRAM_TIMING.MVDD Voltage is outside the supported range.can not populate memory level as memory clock is zerocan not find MinVddc voltage value from memory VDDC voltage dependency tableFailed to retrieve memory pll parameter.Failed to calculate mclk params.can not find VDDC voltage value for VDDC engine clock dependency tableEngine clock can't satisfy stutter requirement!There must be 1 or more PCIE levels defined in PPTable.Failed to update SCLK threshold!Failed to program memory timing parameters!Failed to initialize Graphics Level!Failed to initialize Memory Level!Cannot find ACPI VDDC voltage value in Clock Dependency TableError retrieving Engine Clock dividers from VBIOS.Cannot find ACPI VDDCI voltage value in Clock Dependency TableFailed to initialize ACPI Level!can not find divide id for VCE engine clockFailed to initialize VCE Level!Failed to Write ARB settings for the initial state.can not find divide id for Vclk clockcan not find divide id for Dclk clockFailed to initialize UVD Level!Target Operating Temp is out of Range!Stretch Amount in PPTable not supported Failed to populate Clock Stretcher Data Table!Failed to populate AVFS Parameters!VDDC should be on SVI2 control in merged mode!SVI2 Plane 2 is already taken, set MVDD as StaticCan not find DFS divide id for SclkFailed to upload dpm data to SMC memory!Attempt to get pm_fuse_table_offset Failed!Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!Attempt to populate TdcWaterfallCtl, LPMLTemperature Min and Max Failed!Attempt to download PmFuseTable Failed!Failed to populate PM fuses to SMC memory!3amdgpu: [powerplay] No response from smu 3amdgpu: [powerplay] Failed to send message: 0x%x, ret value: 0x%x 3amdgpu: [powerplay] Failed message: 0x%x, input parameter: 0x%x, error code: 0x%x 3amdgpu: [powerplay] Failed to send message 0x%x, response 0x%x [CopyTableFromSMC] Attempt to Set Dram Addr High Failed![CopyTableFromSMC] Attempt to Set Dram Addr Low Failed![CopyTableFromSMC] Attempt to Transfer Table From SMU Failed![CopyTableToSMC] Attempt to Set Dram Addr High Failed![CopyTableToSMC] Attempt to Set Dram Addr Low Failed![CopyTableToSMC] Attempt to Transfer Table To SMU Failed![Vega20StartSmu] SMC is not running![Vega20StartSmu] Failed to set tools address![SetActivityMonitor] Attempt to Set Dram Addr High Failed![SetActivityMonitor] Attempt to Set Dram Addr Low Failed![SetActivityMonitor] Attempt to Transfer Table To SMU Failed![GetActivityMonitor] Attempt to Set Dram Addr High Failed![GetActivityMonitor] Attempt to Set Dram Addr Low Failed![GetActivityMonitor] Attempt to Transfer Table From SMU Failed![EnableDisableSMCFeatures] Attemp to enable SMU features Low failed![EnableDisableSMCFeatures] Attemp to enable SMU features High failed![EnableDisableSMCFeatures] Attemp to disable SMU features Low failed![EnableDisableSMCFeatures] Attemp to disable SMU features High failed![GetEnabledSMCFeatures] Attemp to get SMU features Low failed![GetEnabledSMCFeatures] Attemp to get SMU features High failed![SetPPtabeDriverAddress] Attempt to Set Dram Addr High Failed![SetPPtabeDriverAddress] Attempt to Set Dram Addr Low Failed!6amdgpu: [powerplay] hwmgr_sw_init smu backed is %s 6amdgpu: [powerplay] dpm not supported init_clock_voltage_dependency failedinit_phase_shedding_table failed6amdgpu: [powerplay] dpm has been enabled 6amdgpu: [powerplay] dpm has been disabled Failed to retrieve minimum clocks.Failed to retrieve maximum clocks.amdgpu: [powerplay] New Display Configuration: amdgpu: [powerplay] cpu_cc6_disable: %d amdgpu: [powerplay] cpu_pstate_disable: %d amdgpu: [powerplay] nb_pstate_switch_disable: %d amdgpu: [powerplay] cpu_pstate_separation_time: %d amdgpu: [powerplay] SetDisplaySizePowerParams data: 0x%X amdgpu: [powerplay] enable Low Memory PState. amdgpu: [powerplay] disable Low Memory PState. amdgpu: [powerplay] min_core_set_clock not set amdgpu: [powerplay] Setting Deep Sleep Clock: %d amdgpu: [powerplay] enabling ALL SMU features. Fail to get clock table from SMU!Dependency table entry exceeds max limit!3amdgpu: [powerplay] Could not retrieve the Integrated System Info Table! 3amdgpu: [powerplay] Unsupported IGP table: %d %d 3amdgpu: [powerplay] The htcTmpLmt should be larger than htcHystLmt. 3amdgpu: [powerplay] Can not allocate memory! 3amdgpu: [powerplay] smu8_get_system_info_data failed drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/smu8_hwmgr.cSetDisplaySizePowerParams data: 0x%X cpu_pstate_separation_time: %d nb_pstate_switch_disable: %d Invalid CAC Leakage PowerPlay Table!3amdgpu: [powerplay] Number of Pcie Entries exceed the number of SCLK Dpm Levels! Disregarding the excess entries... SCLK DPM index for VRHot cannot exceed the total sclk level count!Failed to allocate hwmgr->pptable!ATOM_PP_PLATFORM_CAP_ASPM_L1 is not supported!ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY is not supported!ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL is not supported!ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 is not supported!ATOM_PP_PLATFORM_CAP_HTLINKCONTROL is not supported!Thermal controller table not set!init_thermal_controller failedinit_clock_voltage_dependency failedIncorrect PowerPlay table revision!Invalid PowerPlay Table State Array Offset.Invalid PowerPlay Table State Array.Invalid PowerPlay Table State Array Entry.Requested state entry ID is out of range!3amdgpu: [powerplay] Invalid VramInfo table.Could not find Voltage Table in BIOS.Error retrieving BIOS Table Address!Could not find GPIO lookup Table in BIOS.3amdgpu: [powerplay] DPM Level not supported amdgpu: [powerplay] Can't find requested voltage id in vddc_dependency_on_sclk table! drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/ppatomctrl.cCan't find requested voltage id in vddc_dependency_on_sclk table! Error retrieving BIOS Table Address!Could not find Voltage Table in BIOS.Unsupported Voltage Object Mode!Could not find GPIO lookup Table in BIOS.6amdgpu: [powerplay] Invalid VBIOS AVFS ProfilingInfo Revision! 6amdgpu: [powerplay] Error retrieving BIOS smu_info Table Address!6amdgpu: [powerplay] Error retrieving BIOS firmwareinfo!6amdgpu: [powerplay] Fw info table revision does not match!6amdgpu: [powerplay] Error retrieving BIOS Table Address!3amdgpu: [powerplay] Unknown throttling event sources.%s %16s %16s %16s %16s %16s %16s %16s %3d %14s %s: %8d %16d %16d %16d %16d %16d amdgpu: [powerplay] %s: enforce minimal VBITimeout: %d -> 280 amdgpu: [powerplay] Single MCLK entry VDDCI/MCLK dependency table does not match VBIOS boot MCLK levelamdgpu: [powerplay] Single VDDCI entry VDDCI/MCLK dependency table does not match VBIOS boot VDDCI levelFailed to enable SCLK DPM during DPM Start Function!Failed to enable MCLK DPM during DPM Start Function!VI should always have 2 performance levels3amdgpu: [powerplay] Voltage value looks like a Leakage ID but it's not patched Failed to disable power containment!Failed to disable pcie DPM during DPM Stop Function!Trying to disable SCLK DPM when DPM is disabledTrying to disable MCLK DPM when DPM is disabledTrying to disable voltage DPM when DPM is disabledAttempt to disable Master Deep Sleep switch failed!Failed to disable deep sleep master switch!Failed to force to switch arbf0![disable_dpm_tasks] Failed to disable DPM!NULL user input for clock and voltage6amdgpu: [powerplay] OverDrive feature not enabled Failed to get ODN SCLK and Voltage tablesFailed to get ODN MCLK and Voltage tables6amdgpu: [powerplay] invalid clock voltage input 6amdgpu: [powerplay] OD voltage is out of range [%d - %d] mV 6amdgpu: [powerplay] OD engine clock is out of range [%d - %d] MHz 6amdgpu: [powerplay] OD memory clock is out of range [%d - %d] MHz Trying to freeze SCLK DPM when DPM is disabledFailed to freeze SCLK DPM during FreezeSclkMclkDPM Function!Trying to freeze MCLK DPM when DPM is disabledFailed to freeze MCLK DPM during FreezeSclkMclkDPM Function!Failed to freeze SCLK MCLK DPM!Failed to populate SCLK during PopulateNewDPMClocksStates Function!Failed to populate MCLK during PopulateNewDPMClocksStates Function!power state did not have any performance levelFailed to generate DPM level enabled mask!Failed to update SCLK threshold!Failed to notify smc display settings!Trying to Unfreeze SCLK DPM when DPM is disabledFailed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!Trying to Unfreeze MCLK DPM when DPM is disabledFailed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!Failed to unfreeze SCLK MCLK DPM!Failed to upload DPM level enabled mask!6amdgpu: [powerplay] PSPP request to switch to Gen2 from Gen3 Failed!6amdgpu: [powerplay] PSPP request to switch to Gen1 from Gen2 Failed!Failed to populate and upload SCLK MCLK DPM levels!6amdgpu: [powerplay] Error retrieving EVV voltage value! amdgpu: [powerplay] failed to retrieving EVV voltage! 6amdgpu: [powerplay] Get EVV Voltage Failed. Abort Driver loading! VDD dependency on SCLK table is missing.VDD dependency on SCLK table has to have is missing.VDD dependency on MCLK table is missingVDD dependency on MCLK table has to have is missing.VDDC dependency on SCLK table is missing. This table is mandatoryVDDC dependency on SCLK table has to have is missing. This table is mandatoryVDDC dependency on MCLK table is missing. This table is mandatoryVDD dependency on MCLK table has to have is missing. This table is mandatoryFailed to retrieve MVDD table.Voltage Dependency Table empty.Failed to retrieve SVI2 MVDD table from dependency table.Failed to retrieve VDDCI table.Failed to retrieve SVI2 VDDCI table from dependency table.Failed to retrieve SVI2 VDDGFX table from lookup table.Failed to retrieve VDDC table.Failed to retrieve SVI2 VDDC table from dependency table.Too many voltage values for VDDC. Trimming to fit state table.Too many voltage values for VDDCI. Trimming to fit state table.Too many voltage values for MVDD. Trimming to fit state table.Performance levels exceeds SMC limit!Performance levels exceeds Driver limit, Skip!3amdgpu: [powerplay] No valid PCIE lane width reported Performance levels exceeds Driver limit!Failed to construct voltage tables!Failed to process firmware header!Failed to initialize switch from ArbF0 to F1!SCLK dependency table is missing.SCLK dependency table count is 0.MCLK dependency table is missing.MCLK dependency table count is 0SCLK dependency table is missing. This table is mandatorySCLK dependency table has to have is missing. This table is mandatoryMCLK dependency table is missing. This table is mandatoryVMCLK dependency table has to have is missing. This table is mandatoryFailed to initialize SMC table!Failed to enable VR hot GPIO interrupt!Attempt to enable Master Deep Sleep switch failed!Failed to enable deep sleep master switch!3amdgpu: [powerplay] Failed to enable Sclk DPM and Mclk DPM!Failed to enable pcie DPM during DPM Start Function!Failed to enable AC DC GPIO Interrupt!Failed to enable power containment!Failed to power control set level!Engine clock can't satisfy stutter requirement!drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/smu7_hwmgr.c%s: enforce minimal VBITimeout: %d -> 280 Single VDDCI entry VDDCI/MCLK dependency table does not match VBIOS boot VDDCI levelSingle MCLK entry VDDCI/MCLK dependency table does not match VBIOS boot MCLK levelfailed to retrieving EVV voltage! Invalid config register table.Post DIDT enable clock gating failed.Failed to enable TDCLimit in SMC.Failed to enable PkgPwrTracking in SMC.3amdgpu: [powerplay] Failed to set Default Power Limit in SMC!Failed to disable TDCLimit in SMC.Failed to disable PkgPwrTracking in SMC.Unsupported GFXClockDependencyTable Revision!6amdgpu: [powerplay] Number of Pcie Entries exceed the number of GFXCLK Dpm Levels! Disregarding the excess entries... Invalid SOC_VDDD Lookup Table!Failed to allocate hwmgr->pptable!Thermal controller table not set!init_thermal_controller failedinit_powerplay_extended_tables failedIncorrect PowerPlay table revision!Invalid PowerPlay Table State Array Offset.Invalid PowerPlay Table State Array.Invalid PowerPlay Table State Array Entry.6amdgpu: [powerplay] [DisplayClockVoltageRequest]Invalid Clock Type!Failed to upload boot level to lowest!Failed to upload dpm max level to highest!6amdgpu: [powerplay] Setting DCEFCLK min/max dpm level is not supported! amdgpu: [powerplay] features_to_disable 0x%llx amdgpu: [powerplay] features_to_enable 0x%llx 6amdgpu: [powerplay] Attempt to set Hard Min for DCEFCLK Failed!amdgpu: [powerplay] Cannot find requested DCEFCLK![EnableAllSmuFeatures] Failed to get enabled smc features!Current ppfeatures: 0x%016llx %3d %14s%s: %14d %3d %10d %14d 6amdgpu: [powerplay] DPM Table Has Too Many Entries!Failed to upload boot level to highest!Failed to upload DPM Bootup Levels!Failed to upload DPM Max Levels!Invalid SOC_VDD-GFX_CLK Dependency Table!Failed to get GFX Clock settings from VBIOS!Cannot find gfx_clk in SOC_VDD-GFX_CLK!Cannot find SOC_CLK in SOC_VDD-SOC_CLK Dependency TableFailed to get SOC Clock settings from VBIOS![avfs_control] Attempt to Enable AVFS feature Failed![avfs_control] Attempt to Disable AVFS feature Failed!6amdgpu: [powerplay] GNLD_PCC_LIMIT has been %s Attempt to Enable PCC Limit feature Failed!Failed to get ECLK clock settings from VBIOS!Invalid SOC_VDD-UCLK Dependency Table!Failed to get UCLK settings from VBIOS!Cannot find UCLK in SOC_VDD-UCLK Dependency Table!Failed to set up led dpm config!SOCCLK dependency table is missing. This table is mandatorySOCCLK dependency table is empty. This table is mandatoryGFXCLK dependency table is missing. This table is mandatoryGFXCLK dependency table is empty. This table is mandatoryMCLK dependency table is missing. This table is mandatoryMCLK dependency table has to have is missing. This table is mandatoryIncorrect number of PCIE States from VBIOS!NULL user input for clock and voltage6amdgpu: [powerplay] OverDrive feature not enabled 6amdgpu: [powerplay] invalid clock voltage input 6amdgpu: [powerplay] OD voltage is out of range [%d - %d] mV 6amdgpu: [powerplay] OD engine clock is out of range [%d - %d] MHz 6amdgpu: [powerplay] OD memory clock is out of range [%d - %d] MHz 4amdgpu: [powerplay] max mclk supported by vbios is %d 4amdgpu: [powerplay] max sclk supported by vbios is %d Performance levels exceeds SMC limit!Performance levels exceeds Driver limit!6amdgpu: [powerplay] VI should always have 2 performance levelspercent sclk value must range from 1% to 100%, setting default value6amdgpu: [powerplay] THERMAL Feature Already disabled!disable THERMAL Feature Failed!Failed to disable power containment!Failed to disable didt config!Attempt to disable LED DPM feature failed!Attempt to disable DS_GFXCLK Feature Failed!Attempt to disable DS_ Feature Failed!Attempt to disable DS_LCLK Feature Failed!Attempt to disable DS_DCEFCLK Feature Failed![disable_dpm_tasks] Failed to disable DPM!VDD dependency on SCLK table is missing. This table is mandatoryVDD dependency on SCLK table is empty. This table is mandatoryVDD dependency on MCLK table is missing. This table is mandatoryVDD dependency on MCLK table is empty. This table is mandatoryMem Channel Index Exceeded maximum!Failed to populate SCLK during PopulateNewDPMClocksStates Function!Failed to populate MCLK during PopulateNewDPMClocksStates Function!power state did not have any performance levelAttempt to Trim DPM States Failed!Attempt to upload DPM Bootup Levels Failed!Attempt to upload DPM Max Levels Failed!Failed to generate DPM level enabled mask!Failed to populate and upload SCLK MCLK DPM levels!Failed to setup default DPM tables!Failed to get LCLK clock settings from VBIOS!6amdgpu: [powerplay] Populate LClock Level %d Failed! Failed to initialize Link Level!Failed to initialize Graphics Level!Failed to initialize Memory Level!Number Of Entries Exceeded maximum!Failed to populate Clock in DisplayClockTable!Failed to initialize Display Level!Failed to initialize VCE Level!Failed to get VCLK clock settings from VBIOS!Failed to get DCLK clock settings from VBIOS!Failed to initialize AVFS Parameters!Failed to upload FuseOVerride!Attempt to enable AVFS feature Failed!6amdgpu: [powerplay] [ACG_Enable] ACG BTC Returned Failed Status! Failed to initialize GPIO Parameters!Failed to initialize UVD Level!Voltage Dependency Table empty.Failed to retrieve MVDDC table!Failed to retrieve VDDCI_MEM table!Failed to retrieve VDDCR_SOC table!Too many voltage values for VDDC. Trimming to fit state table.Too many voltage values for VDDCI. Trimming to fit state table.Too many voltage values for MVDD. Trimming to fit state table.Failed to construct voltage tables!Failed to initialize SMC table!6amdgpu: [powerplay] THERMAL Feature Already enabled!Enable THERMAL Feature Failed!Failed to enable thermal protection!Attempt to Enable VR0 Hot feature Failed!Failed to enable VR hot feature!Attempt to Enable DS_GFXCLK Feature Failed!Attempt to Enable DS_SOCCLK Feature Failed!Attempt to Enable DS_LCLK Feature Failed!Attempt to Enable DS_DCEFCLK Feature Failed!Failed to enable deep sleep master switch!Attempt to Enable LED DPM feature Failed!Failed to enable power containment!Failed to power control set level!Attempt to Enable/Disable DPM VCE Failed!Attempt to Enable/Disable DPM UVD Failed!drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/vega10_hwmgr.cCannot find requested DCEFCLK![vega10_program_didt_config_registers] Invalid config register table!amdgpu: [powerplay] [EnableDiDtConfig] Feature DiDt Already enabled! [EnableDiDt] Attempt to enable DiDt Mode 6 Failed![EnableDiDtConfig] Attempt to Enable DiDt feature Failed!amdgpu: [powerplay] [DisableDiDtConfig] Feature DiDt Already Disabled! [DisableDiDtConfig] Attempt to Disable DiDt feature Failed!Attempt to enable PPT feature Failed!Attempt to disable PPT feature Failed!drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/vega10_powertune.c[DisableDiDtConfig] Feature DiDt Already Disabled! [EnableDiDtConfig] Feature DiDt Already enabled! Attempt to Enable FAN CONTROL feature Failed!Attempt to Enable SMC FAN CONTROL Feature Failed!Attempt to Disable SMC FAN CONTROL Feature Failed![Thermal_EnableAlert] FW CTF Already disabled! Attempt to disable FW CTF feature Failed!6amdgpu: [powerplay] Failed to update Fan Control Table in PPTable!6amdgpu: [powerplay] Failed to update fan control table in pptable!6amdgpu: [powerplay] Attempt to disable SMC fan control feature failed!6amdgpu: [powerplay] Attempt to enable SMC fan control feature failed![Thermal_EnableAlert] FW CTF Already Enabled! Attempt to Enable FW CTF feature Failed!6amdgpu: [powerplay] Currently sclk only support 3 levels on RV 6amdgpu: [powerplay] [DisplayClockVoltageRequest]Invalid Clock Type!6amdgpu: [powerplay] smu firmware version too old, can not set dpm level %3d %14s%s: %14d %3d %10d %14d Attempt to set DCF Clock Failed!3amdgpu: [powerplay] Invalid power profile mode %ld Attempt to copy clock table from smc failed3amdgpu: [powerplay] Can not allocate memory! 4Please check whether power state management is supported on this asic Failed to allocate hwmgr->pptable![appendVbiosPPTable] Failed to retrieve Smc Dpm Table from VBIOS!init_powerplay_table_information failed6amdgpu: [powerplay] [DisplayClockVoltageRequest]Invalid Clock Type!Failed to set soft max gfxclk!Failed to set soft max memclk!Failed to set soft max socclk!Failed to set soft min gfxclk !Failed to set soft min memclk !Failed to set hard min memclk !Failed to set soft min socclk!Failed to set hard min dcefclk!Failed to upload boot level to lowest!Failed to upload dpm max level to highest!3amdgpu: [powerplay] Clock level specified %d is over max allowed %d [SetUclkToHightestDpmLevel] Dpm table has no entry![SetUclkToHightestDpmLevel] Dpm table has too many entries![SetUclkToHightestDpmLevel] Set hard min uclk failed![DisableAllSMUFeatures] Failed to disable all smu features!Failed to disable all smu features![disable_dpm_tasks] Failed to disable DPM!amdgpu: [powerplay] features_to_disable 0x%llx amdgpu: [powerplay] features_to_enable 0x%llx [EnableAllSmuFeatures] Failed to get enabled smc features!Current ppfeatures: 0x%016llx [GetNumOfDpmLevel] failed to get dpm levels![GetNumOfDpmLevel] number of clk levels is invalid![SetupSingleDpmTable] failed to get clk levels![GetDpmFrequencyByIndex] Failed to get dpm frequency from SMU![SetupSingleDpmTable] failed to get clk of specific level!6amdgpu: [powerplay] Failed to export SMU metrics table! 3amdgpu: [powerplay] Invalid index for retrieving clock activity [SetupDefaultDpmTable] failed to get socclk dpm levels![SetupDefaultDpmTable] failed to get gfxclk dpm levels![SetupDefaultDpmTable] failed to get memclk dpm levels![SetupDefaultDpmTable] failed to get eclk dpm levels![SetupDefaultDpmTable] failed to get vclk dpm levels![SetupDefaultDpmTable] failed to get dclk dpm levels![SetupDefaultDpmTable] failed to get dcefclk dpm levels![SetupDefaultDpmTable] failed to get pixclk dpm levels![SetupDefaultDpmTable] failed to get dispclk dpm levels![SetupDefaultDpmTable] failed to get phyclk dpm levels![SetAllowedFeaturesMask] Attempt to set allowed features mask (high) failed![SetAllowedFeaturesMask] Attempt to set allowed features mask (low) failed![EnableDPMTasks] Failed to set allowed featuresmask! [Run_ACG_BTC] Attempt to run ACG BTC failed![EnableAllSMUFeatures] Failed to enable all smu features!Failed to enable all smu features!Failed to power control set level![GetClockRanges] Failed to get max ac clock from SMC![GetClockRanges] Failed to get min ac clock from SMC![GetClockRanges] Failed to get max dc clock from SMC!Failed to get clk range from SMC!Failed to get all clock ranges!Failed to setup default DPM tables!Failed to initialize SMC table![FindHighestDPMLevel] DPM Table has too many entries!Failed to upload boot level to highest!Failed to upload DPM Bootup Levels!Failed to upload DPM Max Levels![GetCurrentGfxClkFreq] Attempt to get Current GFXCLK Frequency Failed![GetCurrentMClkFreq] Attempt to get Current MCLK Frequency Failed!Attempt to get current gfx clk Failed!Attempt to get gfx clk levels Failed!Attempt to get current mclk freq Failed!Attempt to get memory clk levels Failed!Attempt to get Current SOCCLK Frequency Failed!Attempt to get soc clk levels Failed!Attempt to get Current DCEFCLK Frequency Failed!Attempt to get dcef clk levels Failed!Attempt to set divider for DCEFCLK Failed!6amdgpu: [powerplay] Attempt to set Hard Min for DCEFCLK Failed!Attempt to Enable/Disable DPM VCE Failed!Attempt to Enable/Disable DPM UVD Failed!drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/vega12_hwmgr.cAttempt to get current RPM from SMC Failed!4amdgpu: [powerplay] GPU over temperature range detected on PCIe %d:%d.%d! 4amdgpu: [powerplay] GPU under temperature range detected on PCIe %d:%d.%d! 4amdgpu: [powerplay] GPU Critical Temperature Fault detected on PCIe %d:%d.%d! 3amdgpu: [powerplay] Invalid Hardware Manager!Voltage Dependency Table empty.amdgpu: [powerplay] vddci is larger than max value in vddci_table amdgpu: [powerplay] Can't find requested voltage id in vdd_dep_on_sclk table 3amdgpu: [powerplay] Can not allocate space for vddc_dep_on_dal_pwrl! 3amdgpu: [powerplay] DAL requested level can not found a available voltage in VDDC DPM Table drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/smu_helper.cCan't find requested voltage id in vdd_dep_on_sclk table vddci is larger than max value in vddci_table Failed to allocate hwmgr->pptable!6amdgpu: [powerplay] Unmatch PPTable version: pptable from VBIOS is V%d while driver supported is V%d![appendVbiosPPTable] Failed to retrieve Smc Dpm Table from VBIOS!init_powerplay_table_information failed6amdgpu: [powerplay] [DisplayClockVoltageRequest]Invalid Clock Type!Failed to set soft max gfxclk!Failed to set soft max memclk!Failed to set soft max socclk!Failed to set soft min gfxclk !Failed to set soft min memclk !Failed to set soft min socclk!Failed to set hard min dcefclk!3amdgpu: [powerplay] Clock level specified %d is over max allowed %d Failed to upload boot level to lowest!Failed to upload dpm max level to highest!Failed to set min link dpm level![SetUclkToHightestDpmLevel] Dpm table has no entry![SetUclkToHightestDpmLevel] Dpm table has too many entries![SetUclkToHightestDpmLevel] Set hard min uclk failed![SetFclkToHightestDpmLevel] Dpm table has no entry![SetFclkToHightestDpmLevel] Dpm table has too many entries![SetFclkToHightestDpmLevel] Set soft min fclk failed!Attempt to set divider for DCEFCLK Failed!6amdgpu: [powerplay] Attempt to set Hard Min for DCEFCLK Failed![SetHardMinFreq] Set hard min uclk failed![EnableMgpuFan] Failed to enable mgpu fan boost![DisableAllSMUFeatures] Failed to disable all smu features![DisableDpmTasks] Failed to disable all smu features![PowerOffAsic] Failed to disable DPM!amdgpu: [powerplay] features_to_disable 0x%llx amdgpu: [powerplay] features_to_enable 0x%llx [EnableAllSmuFeatures] Failed to get enabled smc features!Current ppfeatures: 0x%016llx [GetNumOfDpmLevel] failed to get dpm levels![GetNumOfDpmLevel] number of clk levels is invalid![SetupSingleDpmTable] failed to get clk levels![GetDpmFreqByIndex] failed to get dpm freq by index![GetDpmFreqByIndex] clk value is invalid![SetupSingleDpmTable] failed to get clk of specific level![SetupDefaultDpmTable] failed to get gfxclk dpm levels![SetupDefaultDpmTable] failed to get memclk dpm levels!NULL user input for clock and voltage6amdgpu: [powerplay] invalid number of input parameters %d 6amdgpu: [powerplay] Sclk min/max frequency overdrive not supported 6amdgpu: [powerplay] Invalid index %d 6amdgpu: [powerplay] Support min/max sclk frequency setting only which index by 0/1 6amdgpu: [powerplay] clock freq %d is not within allowed range [%d - %d] 6amdgpu: [powerplay] Mclk max frequency overdrive not supported 6amdgpu: [powerplay] Support max Mclk frequency setting only which index by 1 6amdgpu: [powerplay] Voltage curve calibrate not supported 6amdgpu: [powerplay] Setting for point %d is not supported 6amdgpu: [powerplay] Three supported points index by 0, 1, 2 6amdgpu: [powerplay] clock voltage %d is not within allowed range [%d - %d] Failed to export overdrive table!Failed to import overdrive table!Failed to export over drive table!Failed to import over drive table![SetMclkOD] failed to set od memclk![SetMclkOD] failed to refresh memclk table![GetCurrentClkFreq] Attempt to get Current Frequency Failed!Attempt to get current gfx clk Failed!Attempt to get current mclk freq Failed!Attempt to get current socclk freq Failed!Attempt to get current fclk freq Failed!Attempt to get current dcefclk freq Failed!VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz VDDC_CURVE_VOLT[0]: %7dmV %11dmV VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz VDDC_CURVE_VOLT[1]: %7dmV %11dmV VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz VDDC_CURVE_VOLT[2]: %7dmV %11dmV [GetMaxSustainableClock] Failed to get max DC clock from SMC![GetMaxSustainableClock] failed to get max AC clock from SMC![GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!%16s %s %s %s %s %s %s %s %s %s %s [GetPowerProfile] Failed to get activity monitor!%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d 3amdgpu: [powerplay] Invalid power profile mode %d [SetPowerProfile] Failed to get activity monitor![SetPowerProfile] Failed to set activity monitor!6amdgpu: [powerplay] Failed to export SMU metrics table! 3amdgpu: [powerplay] Invalid index for retrieving clock activity [SetupDefaultDpmTable] failed to get socclk dpm levels![SetupDefaultDpmTable] failed to get eclk dpm levels![SetupDefaultDpmTable] failed to get vclk dpm levels![SetupDefaultDpmTable] failed to get dclk dpm levels![SetupDefaultDpmTable] failed to get dcefclk dpm levels![SetupDefaultDpmTable] failed to get pixclk dpm levels![SetupDefaultDpmTable] failed to get dispclk dpm levels![SetupDefaultDpmTable] failed to get phyclk dpm levels![SetupDefaultDpmTable] failed to get fclk dpm levels!3amdgpu: [powerplay] Failed to apply vega20 baco workaround! [SetAllowedFeaturesMask] Attempt to set allowed features mask(high) failed![SetAllowedFeaturesMask] Attempt to set allowed features mask (low) failed![InitSMCTable] Failed to get vbios bootup values![InitSMCTable] Failed to upload PPtable![EnableDPMTasks] Failed to run btc![EnableDPMTasks] Failed to run btc afll![EnableAllSMUFeatures] Failed to enable all smu features![EnableDPMTasks] Failed to notify smc display change![EnableDPMTasks] Failed to send clock ratio![EnableDPMTasks] Failed to setup default DPM tables![InitMaxSustainableClocks] failed to get max UCLK from SMC![InitMaxSustainableClocks] failed to get max SOCCLK from SMC![InitMaxSustainableClocks] failed to get max DCEFCLK from SMC![InitMaxSustainableClocks] failed to get max DISPCLK from SMC![InitMaxSustainableClocks] failed to get max PHYCLK from SMC![InitMaxSustainableClocks] failed to get max PIXCLK from SMC![EnableDPMTasks] Failed to power control set level![PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU![GetPptLimit] get default PPT limit failed![EnableDPMTasks] Failed to initialize odn settings![EnableDPMTasks] Failed to get maximum sustainable clocks![OverridePcieParameters] Attempt to override pcie params failed![EnableDPMTasks] Failed to override pcie parameters![EnableDPMTasks] Failed to enable all smu features![EnableDPMTasks] Failed to initialize SMC table![EnableDPMTasks] Failed to set allowed featuresmask! [FindHighestDPMLevel] DPM Table does not exist![FindHighestDPMLevel] DPM Table has no entry![FindHighestDPMLevel] DPM Table has too many entries!Failed to upload boot level to highest!Failed to upload DPM Bootup Levels!Failed to upload DPM Max Levels![SmuI2CAccessBus] Failed to access bus![GetClockRanges] Failed to get max clock from SMC![GetClockRanges] Failed to get min clock from SMC![GetSclks]: gfxclk dpm not enabled! [GetSclks]: fail to get min PPCLK_GFXCLK [GetSclks]: fail to get max PPCLK_GFXCLK [MemMclks]: memclk dpm not enabled! [GetMclks]: fail to get min PPCLK_UCLK [GetMclks]: fail to get max PPCLK_UCLK [SetSclkOD] failed to set od gfxclk![SetSclkOD] failed to refresh gfxclk table!amdgpu: [powerplay] [EnableDisableVCEDPM] feature VCE DPM already enabled! amdgpu: [powerplay] [EnableDisableVCEDPM] feature VCE DPM already disabled! Attempt to Enable/Disable DPM VCE Failed!amdgpu: [powerplay] [EnableDisableUVDDPM] feature DPM UVD already enabled! amdgpu: [powerplay] [EnableDisableUVDDPM] feature DPM UVD already disabled! [EnableDisableUVDDPM] Attempt to Enable/Disable DPM UVD Failed!drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/vega20_hwmgr.c[EnableDisableUVDDPM] feature DPM UVD already disabled! [EnableDisableUVDDPM] feature DPM UVD already enabled! [EnableDisableVCEDPM] feature VCE DPM already disabled! [EnableDisableVCEDPM] feature VCE DPM already enabled! Disable FAN CONTROL feature Failed!Attempt to get current RPM from SMC Failed!Enable FAN CONTROL feature Failed!3amdgpu: [powerplay] powerplay hw init failed 3amdgpu: [powerplay] fw load failed amdgpu: [powerplay] powerplay sw init %s amdgpu: failed to create smu prv buffer amdgpu: failed to notify SMU buffer address 6amdgpu: [powerplay] %s was not implemented. amdgpu: [powerplay] Error in phm_get_clock_info amdgpu: [powerplay] %s was not implemented. amdgpu: [powerplay] power profile setting is for manual dpm mode only. amdgpu: [powerplay] force clock level is for dpm manual mode only. drivers/gpu/drm/amd/amdgpu/../powerplay/amd_powerplay.cpower profile setting is for manual dpm mode only. force clock level is for dpm manual mode only. 3amdgpu: [powerplay] Failed to smu_fini_smc_tables! 3amdgpu: [powerplay] Failed to sw fini smc table! 3amdgpu: [powerplay] Failed to init smu_fini_power! 6amdgpu: [powerplay] dpm has been enabled 3amdgpu: [powerplay] [%s] Attempt to override pcie params failed! 6amdgpu: [powerplay] dpm has been disabled 6amdgpu: [powerplay] SMU is resuming... 6amdgpu: [powerplay] SMU is resumed successfully! drivers/gpu/drm/amd/amdgpu/../powerplay/amdgpu_smu.c3amdgpu: [powerplay] SMC firmware status is not correct 6amdgpu: [powerplay] SMU is initialized successfully! 3amdgpu: [powerplay] Failed to load smu firmware! 3amdgpu: [powerplay] Failed to init smc tables! 3amdgpu: [powerplay] Failed to init smu_init_power! 3amdgpu: [powerplay] Failed to register smc irq handler! 3amdgpu: [powerplay] Failed to sw init smc table! features high: 0x%08x low: 0x%08x 4amdgpu: [powerplay] set BACO feature enabled failed, return %d 3amdgpu: [powerplay] pp table size not matched ! 6amdgpu: [powerplay] smu reset failed, ret = %d 3amdgpu: [powerplay] Error in smu_get_clock_info 3amdgpu: [powerplay] Failed to change display config!3amdgpu: [powerplay] Failed to apply clocks adjust rules!3amdgpu: [powerplay] Failed to notify smc display config!3amdgpu: [powerplay] Failed to set performance level!3amdgpu: [powerplay] unknown atom_firmware_info version! for smu11 3amdgpu: [powerplay] SMU11 attempt to set divider for DCEFCLK Failed!3amdgpu: [powerplay] New power limit is over the max allowed %d 3amdgpu: [powerplay] Setting new power limit is not supported! 3amdgpu: [powerplay] [%s] Set power limit Failed! 6amdgpu: [powerplay] [%s] Invalid Clock Type!3amdgpu: [powerplay] smu unsupported asic type:%d. 6amdgpu: [powerplay] smu driver if version = 0x%08x, smu fw if version = 0x%08x, smu fw version = 0x%08x (%d.%d.%d) 4amdgpu: [powerplay] SMU driver if version not matched smu_v11_0: Failed to load firmware "%s" 4amdgpu: [powerplay] GPU over temperature range detected on PCIe %d:%d.%d! 4amdgpu: [powerplay] GPU under temperature range detected on PCIe %d:%d.%d! 4amdgpu: [powerplay] GPU under temperature range unknown src id (%d), detected on PCIe %d:%d.%d! 3amdgpu: [powerplay] [GetMaxSustainableClock] Failed to get max DC clock from SMC!3amdgpu: [powerplay] [GetMaxSustainableClock] failed to get max AC clock from SMC!3amdgpu: [powerplay] [%s] failed to get max UCLK from SMC!3amdgpu: [powerplay] [%s] failed to get max SOCCLK from SMC!3amdgpu: [powerplay] [%s] failed to get max DCEFCLK from SMC!3amdgpu: [powerplay] [%s] failed to get max DISPCLK from SMC!3amdgpu: [powerplay] [%s] failed to get max PHYCLK from SMC!3amdgpu: [powerplay] [%s] failed to get max PIXCLK from SMC!3amdgpu: [powerplay] [%s]%s smc FAN CONTROL feature failed!3amdgpu: [powerplay] [%s]Set fan control mode failed!3amdgpu: [powerplay] failed send message: %10s (%d) param: 0x%08x response %#x 3amdgpu: [powerplay] failed send message: %10s (%d) response %#x 4amdgpu: [powerplay] Unknown asic for smu11 3amdgpu: [powerplay] Attempt to get max GX frequency from SMC Failed ! 3amdgpu: [powerplay] Attempt to get min GX frequency from SMC Failed ! 6amdgpu: [powerplay] smu driver if version = 0x%08x, smu fw if version = 0x%08x, smu fw version = 0x%08x (%d.%d.%d) 4amdgpu: [powerplay] SMU driver if version not matched enable gfxoff timeout and failed! disable gfxoff timeout and failed! 3amdgpu: [powerplay] Failed to send message 0x%x, response 0x%x, param 0x%x 3amdgpu: [powerplay] Failed to send message 0x%x, response 0x%x param 0x%x 3amdgpu: [powerplay] Failed to send message 0x%x, response 0x%x 4amdgpu: [powerplay] Unknown asic for smu12 3amdgpu: [powerplay] [GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!3amdgpu: [powerplay] Attempt to get current RPM from SMC Failed! 3amdgpu: [powerplay] Invalid power profile mode %d 3amdgpu: [powerplay] [%s] Failed to get activity monitor!3amdgpu: [powerplay] [%s] Failed to set activity monitor!3amdgpu: [powerplay] [GetNumOfDpmLevel] failed to get dpm levels!3amdgpu: [powerplay] [GetNumOfDpmLevel] number of clk levels is invalid!3amdgpu: [powerplay] [GetDpmFreqByIndex] failed to get dpm freq by index!3amdgpu: [powerplay] [GetDpmFreqByIndex] clk value is invalid!3amdgpu: [powerplay] Unsupported PPTable format!3amdgpu: [powerplay] Invalid PowerPlay Table!3amdgpu: [powerplay] Failed to set soft %s gfxclk ! 3amdgpu: [powerplay] Failed to set soft %s memclk ! 3amdgpu: [powerplay] Failed to set soft %s socclk ! 3amdgpu: [powerplay] Failed to set soft %s fclk ! 3amdgpu: [powerplay] Failed to set hard min dcefclk ! 3amdgpu: [powerplay] [%s] Dpm table has no entry!3amdgpu: [powerplay] [%s] Dpm table has too many entries!3amdgpu: [powerplay] [%s] Set hard min uclk failed!3amdgpu: [powerplay] Failed to set uclk to highest dpm level3amdgpu: [powerplay] Attempt to set divider for DCEFCLK Failed!6amdgpu: [powerplay] Attempt to set Hard Min for DCEFCLK Failed!3amdgpu: [powerplay] Failed to update WMTABLE!6amdgpu: [powerplay] force clock level is for dpm manual mode only. 3amdgpu: [powerplay] Clock level specified %d is over max allowed %d 3amdgpu: [powerplay] Failed to upload boot level to lowest! 3amdgpu: [powerplay] Failed to upload dpm max level to highest! 3amdgpu: [powerplay] Failed to set min link dpm level! 3amdgpu: [powerplay] [SetupDefaultDpmTable] failed to get socclk dpm levels!3amdgpu: [powerplay] [SetupDefaultDpmTable] failed to get gfxclk dpm levels!3amdgpu: [powerplay] [SetupDefaultDpmTable] failed to get memclk dpm levels!3amdgpu: [powerplay] [SetupDefaultDpmTable] failed to get eclk dpm levels!3amdgpu: [powerplay] [SetupDefaultDpmTable] failed to get vclk dpm levels!3amdgpu: [powerplay] [SetupDefaultDpmTable] failed to get dclk dpm levels!3amdgpu: [powerplay] [SetupDefaultDpmTable] failed to get dcefclk dpm levels!3amdgpu: [powerplay] [SetupDefaultDpmTable] failed to get pixclk dpm levels!3amdgpu: [powerplay] [SetupDefaultDpmTable] failed to get dispclk dpm levels!3amdgpu: [powerplay] [SetupDefaultDpmTable] failed to get phyclk dpm levels!3amdgpu: [powerplay] [SetupDefaultDpmTable] failed to get fclk dpm levels!6amdgpu: [powerplay] Failed to export SMU metrics table! %16s %s %s %s %s %s %s %s %s %s %s %19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d 3amdgpu: [powerplay] Attempt to get current gfx clk Failed!3amdgpu: [powerplay] Attempt to get current mclk Failed!3amdgpu: [powerplay] Attempt to get current socclk Failed!3amdgpu: [powerplay] Attempt to get current fclk Failed!3amdgpu: [powerplay] Attempt to get current dcefclk Failed!VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz VDDC_CURVE_VOLT[0]: %7dmV %11dmV VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz VDDC_CURVE_VOLT[1]: %7dmV %11dmV VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz VDDC_CURVE_VOLT[2]: %7dmV %11dmV 4amdgpu: [powerplay] NULL user input for clock and voltage 6amdgpu: [powerplay] invalid number of input parameters %d 6amdgpu: [powerplay] Sclk min/max frequency overdrive not supported 6amdgpu: [powerplay] Invalid index %d 6amdgpu: [powerplay] Support min/max sclk frequency settingonly which index by 0/1 6amdgpu: [powerplay] clock freq %d is not within allowed range [%d - %d] 6amdgpu: [powerplay] Mclk max frequency overdrive not supported 6amdgpu: [powerplay] Support max Mclk frequency setting only which index by 1 6amdgpu: [powerplay] Voltage curve calibrate not supported 6amdgpu: [powerplay] Setting for point %d is not supported 6amdgpu: [powerplay] Three supported points index by 0, 1, 2 6amdgpu: [powerplay] clock voltage %d is not within allowed range [%d- %d] 3amdgpu: [powerplay] Failed to export over drive table! 3amdgpu: [powerplay] Failed to import over drive table! 3amdgpu: [powerplay] [Setoverdrive] failed to refresh dpm table! 3amdgpu: [powerplay] [Setoverdrive] failed to set od clk! 3amdgpu: [powerplay] [%s] DPM Table does not exist!3amdgpu: [powerplay] [%s] DPM Table has no entry!3amdgpu: [powerplay] [%s] DPM Table has too many entries!3amdgpu: [powerplay] Failed to upload DPM Bootup Levels!3amdgpu: [powerplay] Failed to upload DPM Max Levels!3amdgpu: [powerplay] Failed to upload boot level to %s! 3amdgpu: [powerplay] Failed to upload dpm max level to %s! !3amdgpu: [powerplay] Retrieve board OD limits failed! 3amdgpu: [powerplay] [%s] get PPT limit failed!3amdgpu: [powerplay] Cannot get PPT limit due to pptable missing!6amdgpu: [powerplay] Dumped PPTable: 6amdgpu: [powerplay] Version = 0x%08x 6amdgpu: [powerplay] FeaturesToRun[0] = 0x%08x 6amdgpu: [powerplay] FeaturesToRun[1] = 0x%08x 6amdgpu: [powerplay] SocketPowerLimitAc[%d] = %d 6amdgpu: [powerplay] SocketPowerLimitAcTau[%d] = %d 6amdgpu: [powerplay] TdcLimitSoc = %d 6amdgpu: [powerplay] TdcLimitSocTau = %d 6amdgpu: [powerplay] TdcLimitGfx = %d 6amdgpu: [powerplay] TdcLimitGfxTau = %d 6amdgpu: [powerplay] TedgeLimit = %d 6amdgpu: [powerplay] ThotspotLimit = %d 6amdgpu: [powerplay] TmemLimit = %d 6amdgpu: [powerplay] Tvr_gfxLimit = %d 6amdgpu: [powerplay] Tvr_memLimit = %d 6amdgpu: [powerplay] Tvr_socLimit = %d 6amdgpu: [powerplay] FitLimit = %d 6amdgpu: [powerplay] PpmPowerLimit = %d 6amdgpu: [powerplay] PpmTemperatureThreshold = %d 6amdgpu: [powerplay] ThrottlerControlMask = %d 6amdgpu: [powerplay] UlvVoltageOffsetGfx = %d 6amdgpu: [powerplay] UlvPadding = 0x%08x 6amdgpu: [powerplay] UlvGfxclkBypass = %d 6amdgpu: [powerplay] Padding234[0] = 0x%02x 6amdgpu: [powerplay] Padding234[1] = 0x%02x 6amdgpu: [powerplay] Padding234[2] = 0x%02x 6amdgpu: [powerplay] MinVoltageGfx = %d 6amdgpu: [powerplay] MinVoltageSoc = %d 6amdgpu: [powerplay] MaxVoltageGfx = %d 6amdgpu: [powerplay] MaxVoltageSoc = %d 6amdgpu: [powerplay] LoadLineResistanceGfx = %d 6amdgpu: [powerplay] LoadLineResistanceSoc = %d 6amdgpu: [powerplay] [PPCLK_GFXCLK] .VoltageMode = 0x%02x .SnapToDiscrete = 0x%02x .NumDiscreteLevels = 0x%02x .padding = 0x%02x .ConversionToAvfsClk{m = 0x%08x b = 0x%08x} .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x} .SsFmin = 0x%04x .Padding_16 = 0x%04x 6amdgpu: [powerplay] [PPCLK_VCLK] .VoltageMode = 0x%02x .SnapToDiscrete = 0x%02x .NumDiscreteLevels = 0x%02x .padding = 0x%02x .ConversionToAvfsClk{m = 0x%08x b = 0x%08x} .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x} .SsFmin = 0x%04x .Padding_16 = 0x%04x 6amdgpu: [powerplay] [PPCLK_DCLK] .VoltageMode = 0x%02x .SnapToDiscrete = 0x%02x .NumDiscreteLevels = 0x%02x .padding = 0x%02x .ConversionToAvfsClk{m = 0x%08x b = 0x%08x} .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x} .SsFmin = 0x%04x .Padding_16 = 0x%04x 6amdgpu: [powerplay] [PPCLK_SOCCLK] .VoltageMode = 0x%02x .SnapToDiscrete = 0x%02x .NumDiscreteLevels = 0x%02x .padding = 0x%02x .ConversionToAvfsClk{m = 0x%08x b = 0x%08x} .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x} .SsFmin = 0x%04x .Padding_16 = 0x%04x 6amdgpu: [powerplay] [PPCLK_UCLK] .VoltageMode = 0x%02x .SnapToDiscrete = 0x%02x .NumDiscreteLevels = 0x%02x .padding = 0x%02x .ConversionToAvfsClk{m = 0x%08x b = 0x%08x} .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x} .SsFmin = 0x%04x .Padding_16 = 0x%04x 6amdgpu: [powerplay] [PPCLK_FCLK] .VoltageMode = 0x%02x .SnapToDiscrete = 0x%02x .NumDiscreteLevels = 0x%02x .padding = 0x%02x .ConversionToAvfsClk{m = 0x%08x b = 0x%08x} .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x} .SsFmin = 0x%04x .Padding_16 = 0x%04x 6amdgpu: [powerplay] FreqTableGfx 6amdgpu: [powerplay] .[%02d] = %d 6amdgpu: [powerplay] FreqTableVclk 6amdgpu: [powerplay] FreqTableDclk 6amdgpu: [powerplay] FreqTableSocclk 6amdgpu: [powerplay] FreqTableUclk 6amdgpu: [powerplay] FreqTableFclk 6amdgpu: [powerplay] Mp0clkFreq 6amdgpu: [powerplay] .[%d] = %d 6amdgpu: [powerplay] Mp0DpmVoltage 6amdgpu: [powerplay] GfxclkFidle = 0x%x 6amdgpu: [powerplay] GfxclkSlewRate = 0x%x 6amdgpu: [powerplay] Padding567[0] = 0x%x 6amdgpu: [powerplay] Padding567[1] = 0x%x 6amdgpu: [powerplay] Padding567[2] = 0x%x 6amdgpu: [powerplay] Padding567[3] = 0x%x 6amdgpu: [powerplay] GfxclkDsMaxFreq = %d 6amdgpu: [powerplay] GfxclkSource = 0x%x 6amdgpu: [powerplay] Padding456 = 0x%x 6amdgpu: [powerplay] EnableTdpm = %d 6amdgpu: [powerplay] TdpmHighHystTemperature = %d 6amdgpu: [powerplay] TdpmLowHystTemperature = %d 6amdgpu: [powerplay] GfxclkFreqHighTempLimit = %d 6amdgpu: [powerplay] FanStopTemp = %d 6amdgpu: [powerplay] FanStartTemp = %d 6amdgpu: [powerplay] FanGainEdge = %d 6amdgpu: [powerplay] FanGainHotspot = %d 6amdgpu: [powerplay] FanGainVrGfx = %d 6amdgpu: [powerplay] FanGainVrSoc = %d 6amdgpu: [powerplay] FanGainVrMem = %d 6amdgpu: [powerplay] FanGainHbm = %d 6amdgpu: [powerplay] FanPwmMin = %d 6amdgpu: [powerplay] FanAcousticLimitRpm = %d 6amdgpu: [powerplay] FanThrottlingRpm = %d 6amdgpu: [powerplay] FanMaximumRpm = %d 6amdgpu: [powerplay] FanTargetTemperature = %d 6amdgpu: [powerplay] FanTargetGfxclk = %d 6amdgpu: [powerplay] FanZeroRpmEnable = %d 6amdgpu: [powerplay] FanTachEdgePerRev = %d 6amdgpu: [powerplay] FanTempInputSelect = %d 6amdgpu: [powerplay] FuzzyFan_ErrorSetDelta = %d 6amdgpu: [powerplay] FuzzyFan_ErrorRateSetDelta = %d 6amdgpu: [powerplay] FuzzyFan_PwmSetDelta = %d 6amdgpu: [powerplay] FuzzyFan_Reserved = %d 6amdgpu: [powerplay] OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x 6amdgpu: [powerplay] OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x 6amdgpu: [powerplay] Padding8_Avfs[0] = %d 6amdgpu: [powerplay] Padding8_Avfs[1] = %d 6amdgpu: [powerplay] dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x} 6amdgpu: [powerplay] dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x} 6amdgpu: [powerplay] dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x} 6amdgpu: [powerplay] qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x} 6amdgpu: [powerplay] qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x} 6amdgpu: [powerplay] qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x} 6amdgpu: [powerplay] qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x} 6amdgpu: [powerplay] DcTol[AVFS_VOLTAGE_GFX] = 0x%x 6amdgpu: [powerplay] DcTol[AVFS_VOLTAGE_SOC] = 0x%x 6amdgpu: [powerplay] DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x 6amdgpu: [powerplay] DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x 6amdgpu: [powerplay] Padding8_GfxBtc[0] = 0x%x 6amdgpu: [powerplay] Padding8_GfxBtc[1] = 0x%x 6amdgpu: [powerplay] DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x 6amdgpu: [powerplay] DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x 6amdgpu: [powerplay] DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x 6amdgpu: [powerplay] DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x 6amdgpu: [powerplay] DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x 6amdgpu: [powerplay] DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x 6amdgpu: [powerplay] XgmiDpmPstates 6amdgpu: [powerplay] XgmiDpmSpare[0] = 0x%02x 6amdgpu: [powerplay] XgmiDpmSpare[1] = 0x%02x 6amdgpu: [powerplay] VDDGFX_TVmin = %d 6amdgpu: [powerplay] VDDSOC_TVmin = %d 6amdgpu: [powerplay] VDDGFX_Vmin_HiTemp = %d 6amdgpu: [powerplay] VDDGFX_Vmin_LoTemp = %d 6amdgpu: [powerplay] VDDSOC_Vmin_HiTemp = %d 6amdgpu: [powerplay] VDDSOC_Vmin_LoTemp = %d 6amdgpu: [powerplay] VDDGFX_TVminHystersis = %d 6amdgpu: [powerplay] VDDSOC_TVminHystersis = %d 6amdgpu: [powerplay] DebugOverrides = 0x%x 6amdgpu: [powerplay] ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x} 6amdgpu: [powerplay] ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x} 6amdgpu: [powerplay] ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x} 6amdgpu: [powerplay] ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x} 6amdgpu: [powerplay] MinVoltageUlvGfx = %d 6amdgpu: [powerplay] PaddingUlv = %d 6amdgpu: [powerplay] TotalPowerConfig = %d 6amdgpu: [powerplay] TotalPowerSpare1 = %d 6amdgpu: [powerplay] TotalPowerSpare2 = %d 6amdgpu: [powerplay] PccThresholdLow = %d 6amdgpu: [powerplay] PccThresholdHigh = %d 6amdgpu: [powerplay] Board Parameters: 6amdgpu: [powerplay] MaxVoltageStepGfx = 0x%x 6amdgpu: [powerplay] MaxVoltageStepSoc = 0x%x 6amdgpu: [powerplay] VddGfxVrMapping = 0x%x 6amdgpu: [powerplay] VddSocVrMapping = 0x%x 6amdgpu: [powerplay] VddMemVrMapping = 0x%x 6amdgpu: [powerplay] BoardVrMapping = 0x%x 6amdgpu: [powerplay] GfxUlvPhaseSheddingMask = 0x%x 6amdgpu: [powerplay] ExternalSensorPresent = 0x%x 6amdgpu: [powerplay] GfxMaxCurrent = 0x%x 6amdgpu: [powerplay] GfxOffset = 0x%x 6amdgpu: [powerplay] Padding_TelemetryGfx = 0x%x 6amdgpu: [powerplay] SocMaxCurrent = 0x%x 6amdgpu: [powerplay] SocOffset = 0x%x 6amdgpu: [powerplay] Padding_TelemetrySoc = 0x%x 6amdgpu: [powerplay] MemMaxCurrent = 0x%x 6amdgpu: [powerplay] MemOffset = 0x%x 6amdgpu: [powerplay] Padding_TelemetryMem = 0x%x 6amdgpu: [powerplay] BoardMaxCurrent = 0x%x 6amdgpu: [powerplay] BoardOffset = 0x%x 6amdgpu: [powerplay] Padding_TelemetryBoardInput = 0x%x 6amdgpu: [powerplay] VR0HotGpio = %d 6amdgpu: [powerplay] VR0HotPolarity = %d 6amdgpu: [powerplay] VR1HotGpio = %d 6amdgpu: [powerplay] VR1HotPolarity = %d 6amdgpu: [powerplay] PllGfxclkSpreadEnabled = %d 6amdgpu: [powerplay] PllGfxclkSpreadPercent = %d 6amdgpu: [powerplay] PllGfxclkSpreadFreq = %d 6amdgpu: [powerplay] UclkSpreadEnabled = %d 6amdgpu: [powerplay] UclkSpreadPercent = %d 6amdgpu: [powerplay] UclkSpreadFreq = %d 6amdgpu: [powerplay] FclkSpreadEnabled = %d 6amdgpu: [powerplay] FclkSpreadPercent = %d 6amdgpu: [powerplay] FclkSpreadFreq = %d 6amdgpu: [powerplay] FllGfxclkSpreadEnabled = %d 6amdgpu: [powerplay] FllGfxclkSpreadPercent = %d 6amdgpu: [powerplay] FllGfxclkSpreadFreq = %d 6amdgpu: [powerplay] I2cControllers[%d]: 6amdgpu: [powerplay] .Enabled = %d 6amdgpu: [powerplay] .SlaveAddress = 0x%x 6amdgpu: [powerplay] .ControllerPort = %d 6amdgpu: [powerplay] .ControllerName = %d 6amdgpu: [powerplay] .ThermalThrottler = %d 6amdgpu: [powerplay] .I2cProtocol = %d 6amdgpu: [powerplay] .Speed = %d 6amdgpu: [powerplay] MemoryChannelEnabled = %d 6amdgpu: [powerplay] DramBitWidth = %d 6amdgpu: [powerplay] TotalBoardPower = %d 6amdgpu: [powerplay] XgmiLinkSpeed 6amdgpu: [powerplay] XgmiLinkWidth 6amdgpu: [powerplay] XgmiFclkFreq 6amdgpu: [powerplay] XgmiSocVoltage 3amdgpu: [powerplay] Failed to set soft %s gfxclk ! 3amdgpu: [powerplay] Failed to set soft %s memclk ! 3amdgpu: [powerplay] Failed to set soft %s socclk ! 3amdgpu: [powerplay] Invalid power profile mode %d 3amdgpu: [powerplay] Unsupported power profile mode %d on arcturus 3amdgpu: [powerplay] Fail to set workload type %d 3amdgpu: [powerplay] [%s] failed to get dpm levels! 3amdgpu: [powerplay] [%s] number of clk levels is invalid! 3amdgpu: [powerplay] [%s] failed to get dpm freq by index! 3amdgpu: [powerplay] [%s] clk value is invalid! 4amdgpu: [powerplay] Unsupported SMU power source: %d 4amdgpu: [powerplay] Unsupported SMU table: %d 4amdgpu: [powerplay] Unsupported SMU clk: %d 3amdgpu: [powerplay] Clock level specified %d is over max allowed %d 3amdgpu: [powerplay] Failed to upload boot level to lowest! 3amdgpu: [powerplay] Failed to upload dpm max level to highest! 3amdgpu: [powerplay] [%s] failed to get socclk dpm levels! 3amdgpu: [powerplay] [SetupDefaultDpmTable] failed to get gfxclk dpm levels!3amdgpu: [powerplay] [SetupDefaultDpmTable] failed to get memclk dpm levels!3amdgpu: [powerplay] [SetupDefaultDpmTable] failed to get fclk dpm levels!6amdgpu: [powerplay] Failed to export SMU metrics table! 3amdgpu: [powerplay] Invalid sensor for retrieving clock activity 3amdgpu: [powerplay] Invalid sensor for retrieving temp 3amdgpu: [powerplay] Attempt to get current gfx clk Failed!3amdgpu: [powerplay] Attempt to get current mclk Failed!3amdgpu: [powerplay] Attempt to get current socclk Failed!3amdgpu: [powerplay] Attempt to get current fclk Failed!6amdgpu: [powerplay] smc_dpm_info table revision(format.content): %d.%d 3amdgpu: [powerplay] [%s] DPM Table has no entry!3amdgpu: [powerplay] [%s] DPM Table has too many entries!3amdgpu: [powerplay] Failed to upload DPM Bootup Levels!3amdgpu: [powerplay] Failed to upload DPM Max Levels!3amdgpu: [powerplay] Failed to upload boot level to %s! 3amdgpu: [powerplay] Failed to upload dpm max level to %s! !3amdgpu: [powerplay] [%s] get PPT limit failed!3amdgpu: [powerplay] Cannot get PPT limit due to pptable missing!3amdgpu: [powerplay] Invalid power profile mode %d 3amdgpu: [powerplay] [%s] Failed to get activity monitor!3amdgpu: [powerplay] [%s] Failed to set activity monitor!6amdgpu: [powerplay] Failed to export SMU metrics table! 3amdgpu: [powerplay] Invalid sensor for retrieving clock activity 3amdgpu: [powerplay] Invalid sensor for retrieving temp 3amdgpu: [powerplay] Attempt to set divider for DCEFCLK Failed!6amdgpu: [powerplay] Attempt to set Hard Min for DCEFCLK Failed!3amdgpu: [powerplay] [%s] Set hard min uclk failed!%16s %s %s %s %s %s %s %s %s %s %s %19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d %s:%d reads=%08ld (%08ld total), writes=%08ld (%08ld total) Destination Rectangle x:%d y:%d width:%d height:%d DM_MST: starting TM on aconnector: %p [id: %d] Invalid connector type! signal:%d drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.cGet ELD : idx=%d ret=%d en=%d VRR packet update: crtc=%u enabled=%d state=%dFailed to pin framebuffer with error %d dc_stream_state is NULL for crtc '%d'! dm: DMCU firmware not supported on direct or SMU loading amdgpu_dm: Can't load firmware "%s" amdgpu_dm: Can't validate firmware "%s" amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d Failed to create stream for sink! No EDID firmware found on connector: %s ,forcing to OFF! Mode %dx%d (clk %d) failed DC validation with error %d %s: crtc_id=%d with size %d to %d %s: bad cursor width or height %d x %d DC failed to set cursor attributes DC failed to set cursor position %s: Failed to create new stream for crtc %d Mode change not required, setting mode_changed to %damdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d Failed to allocate plane updates failed to reserve rbo before unpin crtc %d - vupdate irq %sabling: r=%d Failed to allocate update bundle %s Flipping to hi: 0x%x, low: 0x%x crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED failed to reserve buffer before flip include/drm/drm_atomic_helper.hDisabling DRM plane: %d on DRM crtc %d Enabling DRM plane: %d on DRM crtc %d Overlay plane is enabled with hardware cursor but does not fully cover primary plane Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL[CRTC:%d:%s] hw_done or flip_done timed out Atomic check stopped to avoid deadlock. Atomic check stopped due to signal. Atomic check failed with err: %d KMS: Failed to allocate plane KMS: Failed to initialize plane Atomic commit: SET crtc id %d: [%p] got no status for stream %p on acrtc%p %s: crtc=%u VRR off->on: Get vblank ref %s: crtc=%u VRR on->off: Drop vblank ref Atomic commit: RESET. crtc id %d:[%p] Restoring old state failed with %i dc_sink NULL, could not add free_sync module. DCHPD: connector_id=%d: dc_sink didn't change. DCHPD: connector_id=%d: Old sink=%p New sink=%p KMS: Failed to detect connector DM: Failed to initialize mode config DM: Plane nums out of 6 planes KMS: Failed to initialize primary plane KMS: Failed to initialize overlay plane KMS: Failed to initialize crtc KMS: Cannot support more than %d display indexes KMS: Failed to initialize encoder Failed to create i2c adapter data KMS: Failed to initialize connector DM: Backlight registration failed! DM: Registered Backlight device: %s Failed to add vupdate irq id! Failed to add page flip irq id! amdgpu: failed to initialize DM IRQ support. amdgpu: failed to create cgs device. 6[drm] Display Core initialized with v%s! 6[drm] Display Core failed to initialize with v%s! amdgpu: failed to initialize freesync_module. amdgpu: freesync_module init done %p. amdgpu: failed to initialize sw for display support. amdgpu: failed initialize dtn debugfs support. DM_IRQ: work_func: for dal_src=%d DM_IRQ: schedule_work: for dal_src=%d 6[drm] amdgpu_dm_irq_schedule_work FAILED src %d DM_IRQ: invalid irq_source: %d! DM_IRQ: failed to allocate irq handler! DM_IRQ: added irq handler: %p for: dal_src=%d, irq context=%d DM_IRQ: invalid handler_idx==NULL! DM_IRQ: invalid irq_source:%d! DM_IRQ: removed irq handler: %p for: dal_src=%d, irq context=%d DM_IRQ: failed to find irq handler:%p for irq_source:%d! 6[drm] DM_MST: Disabling connector: %p [id: %d] [master: %p] adev->mode_info.rfbdev is NULL drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_mst_types.c6[drm] DM_MST: added connector: %p [id: %d] [master: %p] Invalid Degamma LUT size. Should be %u but got %u. Invalid Gamma LUT size. Should be %u (or %u for legacy) but got %u. drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_color.c6[drm] SADs count is: %d, don't need to read it Couldn't read Speaker Allocation Data Block: %d drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_helpers.cFailed to found connector for link!6[drm] DM_MST: Differing MST start on aconnector: %p [id: %d] 6[drm] DM_MST: starting TM on aconnector: %p [id: %d] 6[drm] DM_MST: stopping TM on aconnector: %p [id: %d] EDID err: %d, on connector: %sDM_PPLIB: invalid clock type: %d! 6[drm] DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d! 6[drm] DM_PPLIB: values for %s clock 6[drm] DM_PPLIB: Warning: using default validation clocks! 6[drm] DM_PPLIB: Validation clocks: 6[drm] DM_PPLIB: engine_max_clock: %d 6[drm] DM_PPLIB: memory_max_clock: %d 6[drm] DM_PPLIB: level : %d 6[drm] DM_PPLIB: reducing engine clock level from %d to %d 6[drm] DM_PPLIB: reducing memory clock level from %d to %d DM_PPLIB: values for %s clock 6[drm] DM_PPLIB: %d in kHz, %d in mV DM_PPLIB: invalid powerlevel state: %d! smu version is not supported ! Unknown CRC source %s for CRTC%d No DP connector available for CRC source No amd connector matching CRTC-%d MST topology for connector %d string to int convert error code: %d Invalid Test Pattern Parameters Invalid Input value No HW will be programmed Invalid Input No HW will be programmed drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.hdrivers/gpu/drm/amd/amdgpu/../display/dc/basics/fixpt31_32.cdrivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.hdrivers/gpu/drm/amd/amdgpu/../display/dc/basics/vector.c%s: Warning: comparing invalid object 'id1'! %s: Warning: comparing invalid object 'id2'! drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser.cCan't get connector table from atom bios. Can't find connector id %d in connector table of size %d. drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table.cDon't have transmitter_control for v%d Don't have set_pixel_clock for v%d Don't have enable_spread_spectrum_on_ppll for v%d Don't have adjust_display_pll for v%d Don't have set_crtc_timing for dtd v%d Don't have set_crtc_timing for v%d Don't have enable_crtc for v%d Don't have program_clock for v%d Don't enable_disp_power_gating enable_crtc for v%d Don't have set_dce_clock for v%d drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table_helper.cdrivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser_common.c[BIOS]:%s:ps.param.symclk_10khz = %d [BIOS]:%s:program display clock = %d, tg = %d, pll = %d, colorDepth = %d [BIOS]:%s:target_clock_frequency = %dclock_type = %d Don't have dig_encoder_control for v%d drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table2.cDon't have transmitter_control for v%d Don't have set_pixel_clock for v%d Don't have set_crtc_timing for v%d Don't have enable_crtc for v%d Don't enable_disp_power_gating enable_crtc for v%d Don't have set_dce_clock for v%d drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table_helper2.cdrivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser2.cdrivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce80/command_table_helper_dce80.cdrivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce110/command_table_helper_dce110.cdrivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce112/command_table_helper_dce112.cdrivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce112/command_table_helper2_dce112.c[BANDWIDTH_CALCS]:#####################################################################[BANDWIDTH_CALCS]:struct bw_calcs_dceip[BANDWIDTH_CALCS]: [enum] bw_calcs_version version %d[BANDWIDTH_CALCS]: [bool] large_cursor: %d[BANDWIDTH_CALCS]: [bool] dmif_pipe_en_fbc_chunk_tracker: %d[BANDWIDTH_CALCS]: [bool] display_write_back_supported: %d[BANDWIDTH_CALCS]: [bool] argb_compression_support: %d[BANDWIDTH_CALCS]: [bool] pre_downscaler_enabled: %d[BANDWIDTH_CALCS]: [bool] underlay_downscale_prefetch_enabled: %d[BANDWIDTH_CALCS]: [bool] graphics_lb_nodownscaling_multi_line_prefetching: %d[BANDWIDTH_CALCS]: [bool] limit_excessive_outstanding_dmif_requests: %d[BANDWIDTH_CALCS]: [uint32_t] cursor_max_outstanding_group_num: %d[BANDWIDTH_CALCS]: [uint32_t] lines_interleaved_into_lb: %d[BANDWIDTH_CALCS]: [uint32_t] low_power_tiling_mode: %d[BANDWIDTH_CALCS]: [uint32_t] chunk_width: %d[BANDWIDTH_CALCS]: [uint32_t] number_of_graphics_pipes: %d[BANDWIDTH_CALCS]: [uint32_t] number_of_underlay_pipes: %d[BANDWIDTH_CALCS]: [uint32_t] max_dmif_buffer_allocated: %d[BANDWIDTH_CALCS]: [uint32_t] graphics_dmif_size: %d[BANDWIDTH_CALCS]: [uint32_t] underlay_luma_dmif_size: %d[BANDWIDTH_CALCS]: [uint32_t] underlay_chroma_dmif_size: %d[BANDWIDTH_CALCS]: [uint32_t] scatter_gather_lines_of_pte_prefetching_in_linear_mode: %d[BANDWIDTH_CALCS]: [uint32_t] display_write_back420_luma_mcifwr_buffer_size: %d[BANDWIDTH_CALCS]: [uint32_t] display_write_back420_chroma_mcifwr_buffer_size: %d[BANDWIDTH_CALCS]: [uint32_t] scatter_gather_pte_request_rows_in_tiling_mode: %d[BANDWIDTH_CALCS]: [bw_fixed] underlay_vscaler_efficiency10_bit_per_component: %d[BANDWIDTH_CALCS]: [bw_fixed] underlay_vscaler_efficiency12_bit_per_component: %d[BANDWIDTH_CALCS]: [bw_fixed] graphics_vscaler_efficiency6_bit_per_component: %d[BANDWIDTH_CALCS]: [bw_fixed] graphics_vscaler_efficiency8_bit_per_component: %d[BANDWIDTH_CALCS]: [bw_fixed] graphics_vscaler_efficiency10_bit_per_component: %d[BANDWIDTH_CALCS]: [bw_fixed] graphics_vscaler_efficiency12_bit_per_component: %d[BANDWIDTH_CALCS]: [bw_fixed] alpha_vscaler_efficiency: %d[BANDWIDTH_CALCS]: [bw_fixed] lb_write_pixels_per_dispclk: %d[BANDWIDTH_CALCS]: [bw_fixed] lb_size_per_component444: %d[BANDWIDTH_CALCS]: [bw_fixed] stutter_and_dram_clock_state_change_gated_before_cursor: %d[BANDWIDTH_CALCS]: [bw_fixed] underlay420_luma_lb_size_per_component: %d[BANDWIDTH_CALCS]: [bw_fixed] underlay420_chroma_lb_size_per_component: %d[BANDWIDTH_CALCS]: [bw_fixed] underlay422_lb_size_per_component: %d[BANDWIDTH_CALCS]: [bw_fixed] cursor_chunk_width: %d[BANDWIDTH_CALCS]: [bw_fixed] cursor_dcp_buffer_lines: %d[BANDWIDTH_CALCS]: [bw_fixed] underlay_maximum_width_efficient_for_tiling: %d[BANDWIDTH_CALCS]: [bw_fixed] underlay_maximum_height_efficient_for_tiling: %d[BANDWIDTH_CALCS]: [bw_fixed] peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display: %d[BANDWIDTH_CALCS]: [bw_fixed] peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation: %d[BANDWIDTH_CALCS]: [bw_fixed] minimum_outstanding_pte_request_limit: %d[BANDWIDTH_CALCS]: [bw_fixed] maximum_total_outstanding_pte_requests_allowed_by_saw: %d[BANDWIDTH_CALCS]: [bw_fixed] linear_mode_line_request_alternation_slice: %d[BANDWIDTH_CALCS]: [bw_fixed] request_efficiency: %d[BANDWIDTH_CALCS]: [bw_fixed] dispclk_per_request: %d[BANDWIDTH_CALCS]: [bw_fixed] dispclk_ramping_factor: %d[BANDWIDTH_CALCS]: [bw_fixed] display_pipe_throughput_factor: %d[BANDWIDTH_CALCS]: [bw_fixed] mcifwr_all_surfaces_burst_time: %d[BANDWIDTH_CALCS]: [bw_fixed] dmif_request_buffer_size: %d[BANDWIDTH_CALCS]:struct bw_calcs_vbios vbios[BANDWIDTH_CALCS]: [enum] bw_defines memory_type: %d[BANDWIDTH_CALCS]: [uint32_t] dram_channel_width_in_bits: %d[BANDWIDTH_CALCS]: [uint32_t] number_of_dram_channels: %d[BANDWIDTH_CALCS]: [uint32_t] number_of_dram_banks: %d[BANDWIDTH_CALCS]: [bw_fixed] low_yclk: %d[BANDWIDTH_CALCS]: [bw_fixed] mid_yclk: %d[BANDWIDTH_CALCS]: [bw_fixed] high_yclk: %d[BANDWIDTH_CALCS]: [bw_fixed] low_sclk: %d[BANDWIDTH_CALCS]: [bw_fixed] mid1_sclk: %d[BANDWIDTH_CALCS]: [bw_fixed] mid2_sclk: %d[BANDWIDTH_CALCS]: [bw_fixed] mid3_sclk: %d[BANDWIDTH_CALCS]: [bw_fixed] mid4_sclk: %d[BANDWIDTH_CALCS]: [bw_fixed] mid5_sclk: %d[BANDWIDTH_CALCS]: [bw_fixed] mid6_sclk: %d[BANDWIDTH_CALCS]: [bw_fixed] high_sclk: %d[BANDWIDTH_CALCS]: [bw_fixed] low_voltage_max_dispclk: %d[BANDWIDTH_CALCS]: [bw_fixed] mid_voltage_max_dispclk;: %d[BANDWIDTH_CALCS]: [bw_fixed] high_voltage_max_dispclk;: %d[BANDWIDTH_CALCS]: [bw_fixed] low_voltage_max_phyclk: %d[BANDWIDTH_CALCS]: [bw_fixed] mid_voltage_max_phyclk: %d[BANDWIDTH_CALCS]: [bw_fixed] high_voltage_max_phyclk: %d[BANDWIDTH_CALCS]: [bw_fixed] data_return_bus_width: %d[BANDWIDTH_CALCS]: [bw_fixed] trc: %d[BANDWIDTH_CALCS]: [bw_fixed] dmifmc_urgent_latency: %d[BANDWIDTH_CALCS]: [bw_fixed] stutter_self_refresh_exit_latency: %d[BANDWIDTH_CALCS]: [bw_fixed] stutter_self_refresh_entry_latency: %d[BANDWIDTH_CALCS]: [bw_fixed] nbp_state_change_latency: %d[BANDWIDTH_CALCS]: [bw_fixed] mcifwrmc_urgent_latency: %d[BANDWIDTH_CALCS]: [bool] scatter_gather_enable: %d[BANDWIDTH_CALCS]: [bw_fixed] down_spread_percentage: %d[BANDWIDTH_CALCS]: [uint32_t] cursor_width: %d[BANDWIDTH_CALCS]: [uint32_t] average_compression_rate: %d[BANDWIDTH_CALCS]: [uint32_t] number_of_request_slots_gmc_reserves_for_dmif_per_channel: %d[BANDWIDTH_CALCS]: [bw_fixed] blackout_duration: %d[BANDWIDTH_CALCS]: [bw_fixed] maximum_blackout_recovery_time: %d[BANDWIDTH_CALCS]:struct bw_calcs_data data[BANDWIDTH_CALCS]: [uint32_t] number_of_displays: %d[BANDWIDTH_CALCS]: [enum] bw_defines underlay_surface_type: %d[BANDWIDTH_CALCS]: [enum] bw_defines panning_and_bezel_adjustment: %d[BANDWIDTH_CALCS]: [enum] bw_defines graphics_tiling_mode: %d[BANDWIDTH_CALCS]: [uint32_t] graphics_lb_bpc: %d[BANDWIDTH_CALCS]: [uint32_t] underlay_lb_bpc: %d[BANDWIDTH_CALCS]: [enum] bw_defines underlay_tiling_mode: %d[BANDWIDTH_CALCS]: [enum] bw_defines d0_underlay_mode: %d[BANDWIDTH_CALCS]: [bool] d1_display_write_back_dwb_enable: %d[BANDWIDTH_CALCS]: [enum] bw_defines d1_underlay_mode: %d[BANDWIDTH_CALCS]: [bool] cpup_state_change_enable: %d[BANDWIDTH_CALCS]: [bool] cpuc_state_change_enable: %d[BANDWIDTH_CALCS]: [bool] nbp_state_change_enable: %d[BANDWIDTH_CALCS]: [bool] stutter_mode_enable: %d[BANDWIDTH_CALCS]: [uint32_t] y_clk_level: %d[BANDWIDTH_CALCS]: [uint32_t] sclk_level: %d[BANDWIDTH_CALCS]: [uint32_t] number_of_underlay_surfaces: %d[BANDWIDTH_CALCS]: [uint32_t] number_of_dram_wrchannels: %d[BANDWIDTH_CALCS]: [uint32_t] chunk_request_delay: %d[BANDWIDTH_CALCS]: [enum] bw_defines underlay_micro_tile_mode: %d[BANDWIDTH_CALCS]: [enum] bw_defines graphics_micro_tile_mode: %d[BANDWIDTH_CALCS]: [bw_fixed] max_phyclk: %d[BANDWIDTH_CALCS]: [bw_fixed] dram_efficiency: %d[BANDWIDTH_CALCS]: [bw_fixed] src_width_after_surface_type: %d[BANDWIDTH_CALCS]: [bw_fixed] src_height_after_surface_type: %d[BANDWIDTH_CALCS]: [bw_fixed] hsr_after_surface_type: %d[BANDWIDTH_CALCS]: [bw_fixed] vsr_after_surface_type: %d[BANDWIDTH_CALCS]: [bw_fixed] src_width_after_rotation: %d[BANDWIDTH_CALCS]: [bw_fixed] src_height_after_rotation: %d[BANDWIDTH_CALCS]: [bw_fixed] hsr_after_rotation: %d[BANDWIDTH_CALCS]: [bw_fixed] vsr_after_rotation: %d[BANDWIDTH_CALCS]: [bw_fixed] source_height_pixels: %d[BANDWIDTH_CALCS]: [bw_fixed] hsr_after_stereo: %d[BANDWIDTH_CALCS]: [bw_fixed] vsr_after_stereo: %d[BANDWIDTH_CALCS]: [bw_fixed] source_width_in_lb: %d[BANDWIDTH_CALCS]: [bw_fixed] lb_line_pitch: %d[BANDWIDTH_CALCS]: [bw_fixed] underlay_maximum_source_efficient_for_tiling: %d[BANDWIDTH_CALCS]: [bw_fixed] num_lines_at_frame_start: %d[BANDWIDTH_CALCS]: [bw_fixed] min_dmif_size_in_time: %d[BANDWIDTH_CALCS]: [bw_fixed] min_mcifwr_size_in_time: %d[BANDWIDTH_CALCS]: [bw_fixed] total_requests_for_dmif_size: %d[BANDWIDTH_CALCS]: [bw_fixed] peak_pte_request_to_eviction_ratio_limiting: %d[BANDWIDTH_CALCS]: [bw_fixed] useful_pte_per_pte_request: %d[BANDWIDTH_CALCS]: [bw_fixed] scatter_gather_pte_request_rows: %d[BANDWIDTH_CALCS]: [bw_fixed] scatter_gather_row_height: %d[BANDWIDTH_CALCS]: [bw_fixed] scatter_gather_pte_requests_in_vblank: %d[BANDWIDTH_CALCS]: [bw_fixed] inefficient_linear_pitch_in_bytes: %d[BANDWIDTH_CALCS]: [bw_fixed] cursor_total_data: %d[BANDWIDTH_CALCS]: [bw_fixed] cursor_total_request_groups: %d[BANDWIDTH_CALCS]: [bw_fixed] scatter_gather_total_pte_requests: %d[BANDWIDTH_CALCS]: [bw_fixed] scatter_gather_total_pte_request_groups: %d[BANDWIDTH_CALCS]: [bw_fixed] tile_width_in_pixels: %d[BANDWIDTH_CALCS]: [bw_fixed] dmif_total_number_of_data_request_page_close_open: %d[BANDWIDTH_CALCS]: [bw_fixed] mcifwr_total_number_of_data_request_page_close_open: %d[BANDWIDTH_CALCS]: [bw_fixed] bytes_per_page_close_open: %d[BANDWIDTH_CALCS]: [bw_fixed] mcifwr_total_page_close_open_time: %d[BANDWIDTH_CALCS]: [bw_fixed] total_requests_for_adjusted_dmif_size: %d[BANDWIDTH_CALCS]: [bw_fixed] total_dmifmc_urgent_trips: %d[BANDWIDTH_CALCS]: [bw_fixed] total_dmifmc_urgent_latency: %d[BANDWIDTH_CALCS]: [bw_fixed] total_display_reads_required_data: %d[BANDWIDTH_CALCS]: [bw_fixed] total_display_reads_required_dram_access_data: %d[BANDWIDTH_CALCS]: [bw_fixed] total_display_writes_required_data: %d[BANDWIDTH_CALCS]: [bw_fixed] total_display_writes_required_dram_access_data: %d[BANDWIDTH_CALCS]: [bw_fixed] display_reads_required_data: %d[BANDWIDTH_CALCS]: [bw_fixed] display_reads_required_dram_access_data: %d[BANDWIDTH_CALCS]: [bw_fixed] dmif_total_page_close_open_time: %d[BANDWIDTH_CALCS]: [bw_fixed] min_cursor_memory_interface_buffer_size_in_time: %d[BANDWIDTH_CALCS]: [bw_fixed] min_read_buffer_size_in_time: %d[BANDWIDTH_CALCS]: [bw_fixed] display_reads_time_for_data_transfer: %d[BANDWIDTH_CALCS]: [bw_fixed] display_writes_time_for_data_transfer: %d[BANDWIDTH_CALCS]: [bw_fixed] dmif_required_dram_bandwidth: %d[BANDWIDTH_CALCS]: [bw_fixed] mcifwr_required_dram_bandwidth: %d[BANDWIDTH_CALCS]: [bw_fixed] required_dmifmc_urgent_latency_for_page_close_open: %d[BANDWIDTH_CALCS]: [bw_fixed] required_mcifmcwr_urgent_latency: %d[BANDWIDTH_CALCS]: [bw_fixed] required_dram_bandwidth_gbyte_per_second: %d[BANDWIDTH_CALCS]: [bw_fixed] dram_bandwidth: %d[BANDWIDTH_CALCS]: [bw_fixed] dmif_required_sclk: %d[BANDWIDTH_CALCS]: [bw_fixed] mcifwr_required_sclk: %d[BANDWIDTH_CALCS]: [bw_fixed] required_sclk: %d[BANDWIDTH_CALCS]: [bw_fixed] downspread_factor: %d[BANDWIDTH_CALCS]: [bw_fixed] v_scaler_efficiency: %d[BANDWIDTH_CALCS]: [bw_fixed] scaler_limits_factor: %d[BANDWIDTH_CALCS]: [bw_fixed] display_pipe_pixel_throughput: %d[BANDWIDTH_CALCS]: [bw_fixed] total_dispclk_required_with_ramping: %d[BANDWIDTH_CALCS]: [bw_fixed] total_dispclk_required_without_ramping: %d[BANDWIDTH_CALCS]: [bw_fixed] total_read_request_bandwidth: %d[BANDWIDTH_CALCS]: [bw_fixed] total_write_request_bandwidth: %d[BANDWIDTH_CALCS]: [bw_fixed] dispclk_required_for_total_read_request_bandwidth: %d[BANDWIDTH_CALCS]: [bw_fixed] total_dispclk_required_with_ramping_with_request_bandwidth: %d[BANDWIDTH_CALCS]: [bw_fixed] total_dispclk_required_without_ramping_with_request_bandwidth: %d[BANDWIDTH_CALCS]: [bw_fixed] dispclk: %d[BANDWIDTH_CALCS]: [bw_fixed] blackout_recovery_time: %d[BANDWIDTH_CALCS]: [bw_fixed] min_pixels_per_data_fifo_entry: %d[BANDWIDTH_CALCS]: [bw_fixed] sclk_deep_sleep: %d[BANDWIDTH_CALCS]: [bw_fixed] chunk_request_time: %d[BANDWIDTH_CALCS]: [bw_fixed] cursor_request_time: %d[BANDWIDTH_CALCS]: [bw_fixed] line_source_pixels_transfer_time: %d[BANDWIDTH_CALCS]: [bw_fixed] dmifdram_access_efficiency: %d[BANDWIDTH_CALCS]: [bw_fixed] mcifwrdram_access_efficiency: %d[BANDWIDTH_CALCS]: [bw_fixed] total_average_bandwidth_no_compression: %d[BANDWIDTH_CALCS]: [bw_fixed] total_average_bandwidth: %d[BANDWIDTH_CALCS]: [bw_fixed] total_stutter_cycle_duration: %d[BANDWIDTH_CALCS]: [bw_fixed] stutter_burst_time: %d[BANDWIDTH_CALCS]: [bw_fixed] time_in_self_refresh: %d[BANDWIDTH_CALCS]: [bw_fixed] stutter_efficiency: %d[BANDWIDTH_CALCS]: [bw_fixed] worst_number_of_trips_to_memory: %d[BANDWIDTH_CALCS]: [bw_fixed] immediate_flip_time: %d[BANDWIDTH_CALCS]: [bw_fixed] latency_for_non_dmif_clients: %d[BANDWIDTH_CALCS]: [bw_fixed] latency_for_non_mcifwr_clients: %d[BANDWIDTH_CALCS]: [bw_fixed] dmifmc_urgent_latency_supported_in_high_sclk_and_yclk: %d[BANDWIDTH_CALCS]: [bw_fixed] nbp_state_dram_speed_change_margin: %d[BANDWIDTH_CALCS]: [bw_fixed] display_reads_time_for_data_transfer_and_urgent_latency: %d[BANDWIDTH_CALCS]: [bw_fixed] dram_speed_change_margin: %d[BANDWIDTH_CALCS]: [bw_fixed] min_vblank_dram_speed_change_margin: %d[BANDWIDTH_CALCS]: [bw_fixed] min_stutter_refresh_duration: %d[BANDWIDTH_CALCS]: [uint32_t] total_stutter_dmif_buffer_size: %d[BANDWIDTH_CALCS]: [uint32_t] total_bytes_requested: %d[BANDWIDTH_CALCS]: [uint32_t] min_stutter_dmif_buffer_size: %d[BANDWIDTH_CALCS]: [uint32_t] num_stutter_bursts: %d[BANDWIDTH_CALCS]: [bw_fixed] v_blank_nbp_state_dram_speed_change_latency_supported: %d[BANDWIDTH_CALCS]: [bw_fixed] nbp_state_dram_speed_change_latency_supported: %d[BANDWIDTH_CALCS]: [bool] fbc_en[%d]:%d [BANDWIDTH_CALCS]: [bool] lpt_en[%d]:%d[BANDWIDTH_CALCS]: [bool] displays_match_flag[%d]:%d[BANDWIDTH_CALCS]: [bool] use_alpha[%d]:%d[BANDWIDTH_CALCS]: [bool] orthogonal_rotation[%d]:%d[BANDWIDTH_CALCS]: [bool] enable[%d]:%d[BANDWIDTH_CALCS]: [bool] access_one_channel_only[%d]:%d[BANDWIDTH_CALCS]: [bool] scatter_gather_enable_for_pipe[%d]:%d[BANDWIDTH_CALCS]: [bool] interlace_mode[%d]:%d[BANDWIDTH_CALCS]: [bool] display_pstate_change_enable[%d]:%d[BANDWIDTH_CALCS]: [bool] line_buffer_prefetch[%d]:%d[BANDWIDTH_CALCS]: [uint32_t] bytes_per_pixel[%d]:%d[BANDWIDTH_CALCS]: [uint32_t] max_chunks_non_fbc_mode[%d]:%d[BANDWIDTH_CALCS]: [uint32_t] lb_bpc[%d]:%d[BANDWIDTH_CALCS]: [uint32_t] output_bpphdmi[%d]:%d[BANDWIDTH_CALCS]: [uint32_t] output_bppdp4_lane_hbr[%d]:%d[BANDWIDTH_CALCS]: [uint32_t] output_bppdp4_lane_hbr2[%d]:%d[BANDWIDTH_CALCS]: [uint32_t] output_bppdp4_lane_hbr3[%d]:%d[BANDWIDTH_CALCS]: [enum] bw_defines stereo_mode[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] dmif_buffer_transfer_time[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] displays_with_same_mode[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] stutter_dmif_buffer_size[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] stutter_refresh_duration[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] stutter_exit_watermark[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] stutter_entry_watermark[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] h_total[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] v_total[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] pixel_rate[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] src_width[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] pitch_in_pixels[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] pitch_in_pixels_after_surface_type[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] src_height[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] scale_ratio[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] h_taps[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] v_taps[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] h_scale_ratio[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] v_scale_ratio[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] rotation_angle[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] compression_rate[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] hsr[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] vsr[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] source_width_rounded_up_to_chunks[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] source_width_pixels[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] source_height_rounded_up_to_chunks[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] display_bandwidth[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] request_bandwidth[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] bytes_per_request[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] useful_bytes_per_request[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] lines_interleaved_in_mem_access[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] latency_hiding_lines[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] lb_partitions[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] lb_partitions_max[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] dispclk_required_with_ramping[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] dispclk_required_without_ramping[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] data_buffer_size[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] outstanding_chunk_request_limit[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] urgent_watermark[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] nbp_state_change_watermark[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] v_filter_init[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] stutter_cycle_duration[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] average_bandwidth[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] average_bandwidth_no_compression[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] scatter_gather_pte_request_limit[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] lb_size_per_component[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] memory_chunk_size_in_bytes[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] pipe_chunk_size_in_bytes[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] number_of_trips_to_memory_for_getting_apte_row[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] adjusted_data_buffer_size[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] adjusted_data_buffer_size_in_memory[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] pixels_per_data_fifo_entry[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] scatter_gather_pte_requests_in_row[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] pte_request_per_chunk[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] scatter_gather_page_width[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] scatter_gather_page_height[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] lb_lines_in_per_line_out_in_beginning_of_frame[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] lb_lines_in_per_line_out_in_middle_of_frame[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] cursor_width_pixels[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] minimum_latency_hiding[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] maximum_latency_hiding[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] minimum_latency_hiding_with_cursor[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] maximum_latency_hiding_with_cursor[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] src_pixels_for_first_output_pixel[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] src_pixels_for_last_output_pixel[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] src_data_for_first_output_pixel[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] src_data_for_last_output_pixel[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] active_time[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] horizontal_blank_and_chunk_granularity_factor[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] cursor_latency_hiding[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] v_blank_dram_speed_change_margin[%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] line_source_transfer_time[%d][%d][%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] dram_speed_change_line_source_transfer_time[%d][%d][%d]:%d[BANDWIDTH_CALCS]: [uint32_t] num_displays_with_margin[%d][%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] dmif_burst_time[%d][%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] mcifwr_burst_time[%d][%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] min_dram_speed_change_margin[%d][%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] dispclk_required_for_dram_speed_change[%d][%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] blackout_duration_margin[%d][%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] dispclk_required_for_blackout_duration[%d][%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] dispclk_required_for_blackout_recovery[%d][%d]:%d[BANDWIDTH_CALCS]: [bw_fixed] dmif_required_sclk_for_urgent_latency[%d]:%ddrivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.cdrivers/gpu/drm/amd/amdgpu/../display/dc/calcs/calcs_logger.hdrivers/gpu/drm/amd/amdgpu/../display/dc/calcs/bw_fixed.cdrivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.hdrivers/gpu/drm/amd/amdgpu/../display/dc/calcs/custom_float.cdrivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dcn_calcs.c[BANDWIDTH_CALCS]: dcf_clk for voltage = %d [BANDWIDTH_CALCS]:sr_exit_time: %f ns sr_enter_plus_exit_time: %f ns urgent_latency: %f ns write_back_latency: %f ns percent_of_ideal_drambw_received_after_urg_latency: %f %% max_request_size: %d bytes dcfclkv_max0p9: %f kHz dcfclkv_nom0p8: %f kHz dcfclkv_mid0p72: %f kHz dcfclkv_min0p65: %f kHz max_dispclk_vmax0p9: %f kHz max_dispclk_vnom0p8: %f kHz max_dispclk_vmid0p72: %f kHz max_dispclk_vmin0p65: %f kHz max_dppclk_vmax0p9: %f kHz max_dppclk_vnom0p8: %f kHz max_dppclk_vmid0p72: %f kHz max_dppclk_vmin0p65: %f kHz socclk: %f kHz fabric_and_dram_bandwidth_vmax0p9: %f MB/s fabric_and_dram_bandwidth_vnom0p8: %f MB/s fabric_and_dram_bandwidth_vmid0p72: %f MB/s fabric_and_dram_bandwidth_vmin0p65: %f MB/s phyclkv_max0p9: %f kHz phyclkv_nom0p8: %f kHz phyclkv_mid0p72: %f kHz phyclkv_min0p65: %f kHz downspreading: %f %% round_trip_ping_latency_cycles: %d DCFCLK Cycles urgent_out_of_order_return_per_channel: %d Bytes number_of_channels: %d vmm_page_size: %d Bytes dram_clock_change_latency: %f ns return_bus_width: %d Bytes [BANDWIDTH_CALCS]:rob_buffer_size_in_kbyte: %f det_buffer_size_in_kbyte: %f dpp_output_buffer_pixels: %f opp_output_buffer_lines: %f pixel_chunk_size_in_kbyte: %f pte_enable: %d pte_chunk_size: %d kbytes meta_chunk_size: %d kbytes writeback_chunk_size: %d kbytes odm_capability: %d dsc_capability: %d line_buffer_size: %d bits max_line_buffer_lines: %d is_line_buffer_bpp_fixed: %d line_buffer_fixed_bpp: %d writeback_luma_buffer_size: %d kbytes writeback_chroma_buffer_size: %d kbytes max_num_dpp: %d max_num_writeback: %d max_dchub_topscl_throughput: %d pixels/dppclk max_pscl_tolb_throughput: %d pixels/dppclk max_lb_tovscl_throughput: %d pixels/dppclk max_vscl_tohscl_throughput: %d pixels/dppclk max_hscl_ratio: %f max_vscl_ratio: %f max_hscl_taps: %d max_vscl_taps: %d pte_buffer_size_in_requests: %d dispclk_ramping_margin: %f %% under_scan_factor: %f %% max_inter_dcn_tile_repeaters: %d can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one: %d bug_forcing_luma_and_chroma_request_to_same_size_fixed: %d dcfclk_cstate_latency: %d drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/clk_mgr.cdrivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.hdrivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce100/dce_clk_mgr.cdrivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce110/dce110_clk_mgr.cdrivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn10/rv1_clk_mgr.cclk_type,clk_value,deepsleep_cntl,deepsleep_allow,bypass CLK1_CLK3_CURRENT_CNT,%d,dcfclk CLK1_CLK3_DS_CNTL,%d,dcf_deep_sleep_divider CLK1_CLK3_ALLOW_DS,%d,dcf_deep_sleep_allow CLK1_CLK2_CURRENT_CNT,%d,dprefclk CLK1_CLK0_CURRENT_CNT,%d,dispclk CLK1_CLK1_CURRENT_CNT,%d,dppclk CLK1_CLK3_BYPASS_CNTL,%d,dcfclk_bypass CLK1_CLK2_BYPASS_CNTL,%d,dprefclk_bypass CLK1_CLK0_BYPASS_CNTL,%d,dispclk_bypass CLK1_CLK1_BYPASS_CNTL,%d,dppclk_bypass drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr.c[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: %u data: %u [HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: %u data: %u [HW_AUDIO]: ========= AUDIO:dce_aud_az_enable: index: %u data: 0x%x [HW_AUDIO]: ========= AUDIO:dce_aud_az_disable: index: %u data: 0x%x [HW_AUDIO]: %s:Input::requested_pixel_clock_100Hz = %dcalculated_pixel_clock_100Hz =%d audio_dto_module = %d audio_dto_phase =%d drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_audio.c[HW_AUDIO]: AUDIO:az_configure: index: %u data, 0x%x, displayName %s: drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_stream_encoder.c[HW_AUDIO]: %s:Input::requested_pixel_clock_100Hz = %dcalculated_pixel_clock_100Hz = %d drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h4[drm] Invalid HW packet index: %s() drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_link_encoder.c%s: Failed to execute VBIOS command table! 4[drm] %s: Failed to get encoder_cap_info from VBIOS with error code %d! Unknown clock source. clk_src id: %d, TG_inst: %ddrivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.cdrivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.c%s Post divider range is invalid%s Reference divider range is invalidThe dec point num or precision is incorrect!Incorrect fract feedback divider precision num!%s: Failed to adjust pixel clock!!for HDMI in ATOMBIOS info Table!!! drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.hdrivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_clock_source.cdrivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_transform.c4[drm] %s: Invalid LB pixel depthThe pixel depth %d is not valid, set COLOR_DEPTH_101010 instead.4[drm] %s: regamma lut was not powered on in a timely manner, programming still proceeds drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.hdrivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_dmcu.cNew Backlight level: %d (0x%X) drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_abm.cdrivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_ipp.cdrivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.hdrivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.cdrivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_i2c.cdrivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_i2c_sw.cdrivers/gpu/drm/amd/amdgpu/../display/dc/gpio/gpio_base.cdrivers/gpu/drm/amd/amdgpu/../display/dc/gpio/gpio_service.cdrivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_factory.cdrivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_gpio.cdrivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_hpd.cdrivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_ddc.cdrivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_generic.cdrivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_translate.cdrivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce80/hw_translate_dce80.cdrivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce80/hw_factory_dce80.cdrivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce110/hw_translate_dce110.cdrivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce110/hw_factory_dce110.cdrivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce120/hw_translate_dce120.cdrivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce120/hw_factory_dce120.cdrivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn10/hw_translate_dcn10.cdrivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn10/hw_factory_dcn10.cdrivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn20/hw_translate_dcn20.cdrivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn20/hw_factory_dcn20.cdrivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn21/hw_translate_dcn21.cdrivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn21/hw_factory_dcn21.cdrivers/gpu/drm/amd/amdgpu/../display/dc/irq/irq_service.c%s: cannot find irq info table entry for %d %s: called for non-implemented irq source drivers/gpu/drm/amd/amdgpu/../display/dc/virtual/virtual_stream_encoder.cdrivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c%s: not valid soc bounding box/n4[drm] Mode Validation Warning: %s failed validation. DC: failed to create mcif_wb20! DC: failed to create clock sources! DC: failed to initialize soc bounding box! DC: failed to create memory input! DC: failed to create input pixel processor! DC:failed to create aux engine!! DC: failed to create output pixel processor! DC: failed to create display stream compressor %d! DC: failed to create mcif_wb! drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.cReset back end for pipe %d, tg:%d Un-gated front end for pipe %d drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.hdrivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp_cm.cdrivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.cdrivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_mpc.cdrivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_opp.cdrivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubbub.cdrivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_optc.cdrivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_stream_encoder.c%s FEC at link encoder inst %d%s: No supported link rate found %X! drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_link_encoder.c4[drm] %s: Failed to get encoder_cap_info from VBIOS with error code %d! drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dccg.c4[drm] Timeout while waiting for GPUVM context update drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_vmid.c%s inst = %d, FAILED!LUMA SCALING NOT SUPPORTEDdrivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dwb_scl.cdrivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.hdrivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dsc.c%s: pix height %d not divisible by num_slices_v %d rc_range_parameters[%d].range_min_qp %d rc_range_parameters[%d].range_max_qp %d rc_range_parameters[%d].range_bpg_offset %dGetting packed DSC PPS for DSC Config:DSC Picture Parameter Set (PPS):Setting DSC Config at DSC inst %dprogramming DSC Picture Parameter Set (PPS):%s: DPCD DSC throughput mode not recognized. %s: DPCD DSC buffer size not recognized. %s: DPCD DSC buffer depth not recognized. %s: DPCD DSC bits-per-pixel increment not recognized. drivers/gpu/drm/amd/amdgpu/../display/dc/dsc/dc_dsc.cERROR: Requested rc_calc to find a bpp entry that exceeds the table size drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_resource.cDC: failed to create clock sources! DC: failed to create memory input! DC: failed to create input pixel processor! DC: failed to create output pixel processor! DC:failed to create aux engine!! drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.cGSL: reset occurred at wait count: %d GSL: Timeout on reset trigger! Multi-display sync is complete [GAMMA]:Logging all tf points...[GAMMA]:Logging all channels...Reset back end for pipe %d, tg:%d HUBP: format addr_hi width height rot mir sw_mode dcc_en blank_en ttu_dis underflow min_ttu_vblank qos_low_wm qos_high_wm [%2d]: %5xh %6xh %5d %6d %2xh %2xh %6xh %6d %8d %7d %8xhHUBP: drq_exp_m prq_exp_m mrq_exp_m crq_exp_m plane1_ba L:chunk_s min_chu_s meta_ch_s min_m_c_s dpte_gr_s mpte_gr_s swath_hei pte_row_h C:chunk_s min_chu_s meta_ch_s min_m_c_s dpte_gr_s mpte_gr_s swath_hei pte_row_h [%2d]: %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh HUBP: rc_hbe dlg_vbe min_d_y_n rc_per_ht rc_x_a_s dst_y_a_s dst_y_pf dst_y_vvb dst_y_rvb dst_y_vfl dst_y_rfl rf_pix_fq vratio_pf vrat_pf_c rc_pg_vbl rc_pg_vbc rc_mc_vbl rc_mc_vbc rc_pg_fll rc_pg_flc rc_mc_fll rc_mc_flc pr_nom_l pr_nom_c rc_pg_nl rc_pg_nc mr_nom_l mr_nom_c rc_mc_nl rc_mc_nc rc_ld_pl rc_ld_pc rc_ld_l rc_ld_c cha_cur0 ofst_cur1 cha_cur1 vr_af_vc0 ddrq_limt x_rt_dlay x_rp_dlay x_rr_sfl [%2d]: %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh% 8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh HUBP: qos_ll_wm qos_lh_wm mn_ttu_vb qos_l_flp rc_rd_p_l rc_rd_l rc_rd_p_c rc_rd_c rc_rd_c0 rc_rd_pc0 rc_rd_c1 rc_rd_pc1 qos_lf_l qos_rds_l qos_lf_c qos_rds_c qos_lf_c0 qos_rds_c0 qos_lf_c1 qos_rds_c1 [%2d]: %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh HUBBUB WM: data_urgent pte_meta_urgent sr_enter sr_exit dram_clk_change DPP: IGAM format IGAM mode DGAM mode RGAM mode GAMUT mode C11 C12 C13 C14 C21 C22 C23 C24 C31 C32 C33 C34 MPCC: OPP DPP MPCCBOT MODE ALPHA_MODE PREMULT OVERLAP_ONLY IDLE [%2d]: %11xh %-11s %-11s %-11s%8x %08xh %08xh %08xh %08xh %08xh %08xhOTG: v_bs v_be v_ss v_se vpol vmax vmin vmax_sel vmin_sel h_bs h_be h_ss h_se hpol htot vtot underflow [%2d]: %2xh %2xh %6xh %4d %10d %7d %12d %4d DSC: CLOCK_EN SLICE_WIDTH Bytes_pp [%d]: %5d %5d %5d %5d %5d %5d %5d %9d %9d %5d %5d %5d %5d %5d %5d %5d %9d S_ENC: DSC_MODE SEC_GSP7_LINE_NUM VBID6_LINE_REFERENCE VBID6_LINE_NUM SEC_GSP7_ENABLE SEC_STREAM_ENABLE L_ENC: DPHY_FEC_EN DPHY_FEC_READY_SHADOW DPHY_FEC_ACTIVE_STATUS [%-3d]: %-9d %-18d %-21d %-15d %-16d %-17d CALCULATED Clocks: dcfclk_khz:%d dcfclk_deep_sleep_khz:%d dispclk_khz:%d dppclk_khz:%d max_supported_dppclk_khz:%d fclk_khz:%d socclk_khz:%d MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.hUn-gated front end for pipe %d wm_set_index,data_urgent,pte_meta_urgent,sr_enter,sr_exit,dram_clk_chanage %x,%d.%03d,%d.%03d,%d.%03d,%d.%03d,%d.%03d instance,format,addr_hi,width,height,rotation,mirror,sw_mode,dcc_en,blank_en,ttu_dis,underflow,min_ttu_vblank,qos_low_wm,qos_high_wm instance,format,addr_hi,addr_lo,width,height,rotation,mirror,sw_mode,dcc_en,blank_en,ttu_dis,underflow,min_ttu_vblank,qos_low_wm,qos_high_wm %x,%x,%x,%d,%d,%x,%x,%x,%x,%x,%x,%x,%d.%03d,%d.%03d,%d.%03d %x,%x,%x,%x,%d,%d,%x,%x,%x,%x,%x,%x,%x,%d.%03d,%d.%03d,%d.%03d instance,drq_exp_m,prq_exp_m,mrq_exp_m,crq_exp_m,plane1_ba,luma_chunk_s,luma_min_chu_s,luma_meta_ch_s,luma_min_m_c_s,luma_dpte_gr_s,luma_mpte_gr_s,luma_swath_hei,luma_pte_row_h,chroma_chunk_s,chroma_min_chu_s,chroma_meta_ch_s,chroma_min_m_c_s,chroma_dpte_gr_s,chroma_mpte_gr_s,chroma_swath_hei,chroma_pte_row_h %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x instance,rc_hbe,dlg_vbe,min_d_y_n,rc_per_ht,rc_x_a_s,dst_y_a_s,dst_y_pf,dst_y_vvb,dst_y_rvb,dst_y_vfl,dst_y_rfl,rf_pix_fq,vratio_pf,vrat_pf_c,rc_pg_vbl,rc_pg_vbc,rc_mc_vbl,rc_mc_vbc,rc_pg_fll,rc_pg_flc,rc_mc_fll,rc_mc_flc,pr_nom_l,pr_nom_c,rc_pg_nl,rc_pg_nc,mr_nom_l,mr_nom_c,rc_mc_nl,rc_mc_nc,rc_ld_pl,rc_ld_pc,rc_ld_l,rc_ld_c,cha_cur0,ofst_cur1,cha_cur1,vr_af_vc0,ddrq_limt,x_rt_dlay,x_rp_dlay,x_rr_sfl %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x instance,qos_ll_wm,qos_lh_wm,mn_ttu_vb,qos_l_flp,rc_rd_p_l,rc_rd_l,rc_rd_p_c,rc_rd_c,rc_rd_c0,rc_rd_pc0,rc_rd_c1,rc_rd_pc1,qos_lf_l,qos_rds_l,qos_lf_c,qos_rds_c,qos_lf_c0,qos_rds_c0,qos_lf_c1,qos_rds_c1 %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x instance,igam_format,igam_mode,dgam_mode,rgam_mode,gamut_mode,c11_c12,c13_c14,c21_c22,c23_c24,c31_c32,c33_c34 %x,%x,%s,%s,%s,%x,%08x,%08x,%08x,%08x,%08x,%08x instance,opp,dpp,mpccbot,mode,alpha_mode,premult,overlap_only,idle instance,v_bs,v_be,v_ss,v_se,vpol,vmax,vmin,vmax_sel,vmin_sel,h_bs,h_be,h_ss,h_se,hpol,htot,vtot,underflow,pixelclk[khz] %x,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d dcfclk,dcfclk_deep_sleep,dispclk,dppclk,fclk,socclk %d,%d,%d,%d,%d,%d drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_optc.cdrivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hubp.cInvalid cursor pitch of %d. Only 64/128/256 is supported on DCN. drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_mpc.cdrivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_dpp_dscl.cdrivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.hdrivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_dpp_cm.cdrivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.hdrivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_cm_common.cIndex out of bounds: i=%d, TRANSFER_FUNC_POINTS=%d drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.hdrivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hubbub.c4[drm] pstate took longer than expected ~%dus 4[drm] pstate TEST_DEBUG_DATA: 0x%X [BANDWIDTH_CALCS]:URGENCY_WATERMARK_A calculated =%d HW register value = 0x%x [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_A calculated =%d HW register value = 0x%x [BANDWIDTH_CALCS]:URGENCY_WATERMARK_B calculated =%d HW register value = 0x%x [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_B calculated =%d HW register value = 0x%x [BANDWIDTH_CALCS]:URGENCY_WATERMARK_C calculated =%d HW register value = 0x%x [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_C calculated =%d HW register value = 0x%x [BANDWIDTH_CALCS]:URGENCY_WATERMARK_D calculated =%d HW register value = 0x%x [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_D calculated =%d HW register value = 0x%x [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_A calculated =%d HW register value = 0x%x [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_A calculated =%d HW register value = 0x%x [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_B calculated =%d HW register value = 0x%x [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_B calculated =%d HW register value = 0x%x [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_C calculated =%d HW register value = 0x%x [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_C calculated =%d HW register value = 0x%x [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_D calculated =%d HW register value = 0x%x [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_D calculated =%d HW register value = 0x%x [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_A calculated =%d HW register value = 0x%x [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_B calculated =%d HW register value = 0x%x [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_C calculated =%d HW register value = 0x%x [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_D calculated =%d HW register value = 0x%x drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.hdrivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_stream_encoder.c[HW_AUDIO]: %s:Input::requested_pixel_clock_100Hz = %dcalculated_pixel_clock_100Hz = %d drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_link_encoder.c%s: Failed to execute VBIOS command table! 4[drm] %s: Failed to get encoder_cap_info from VBIOS with error code %d! Total vertical active bandwidth[DML]:DML_RQ_DLG_CALC: ===================================== [DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST [DML]:DML_RQ_DLG_CALC: chunk_bytes = %0d [DML]:DML_RQ_DLG_CALC: min_chunk_bytes = %0d [DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = %0d [DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = %0d [DML]:DML_RQ_DLG_CALC: mpte_group_bytes = %0d [DML]:DML_RQ_DLG_CALC: dpte_group_bytes = %0d [DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST [DML]:DML_RQ_DLG_CALC: swath_width_ub = %0d [DML]:DML_RQ_DLG_CALC: swath_height = %0d [DML]:DML_RQ_DLG_CALC: req_per_swath_ub = %0d [DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = %0d [DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = %0d [DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = %0d [DML]:DML_RQ_DLG_CALC: dpte_row_height = %0d [DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = %0d [DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = %0d [DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = %0d [DML]:DML_RQ_DLG_CALC: meta_row_height = %0d [DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = %0d [DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST [DML]:DML_RQ_DLG_CALC: full_swath_bytes = %0d [DML]:DML_RQ_DLG_CALC: stored_swath_bytes = %0d [DML]:DML_RQ_DLG_CALC: blk256_width = %0d [DML]:DML_RQ_DLG_CALC: blk256_height = %0d [DML]:DML_RQ_DLG_CALC: req_width = %0d [DML]:DML_RQ_DLG_CALC: req_height = %0d [DML]:DML_RQ_DLG_CALC: *************************** [DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_PARAM_ST [DML]:DML_RQ_DLG_CALC: [DML]:DML_RQ_DLG_CALC: === [DML]:DML_RQ_DLG_CALC: [DML]:DML_RQ_DLG_CALC: [DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_DLG_PARAM_ST [DML]:DML_RQ_DLG_CALC: [DML]:DML_RQ_DLG_CALC: t_mclk_wm_us = %3.2f [DML]:DML_RQ_DLG_CALC: t_urg_wm_us = %3.2f [DML]:DML_RQ_DLG_CALC: t_sr_wm_us = %3.2f [DML]:DML_RQ_DLG_CALC: t_extra_us = %3.2f [DML]:DML_RQ_DLG_CALC: t_srx_delay_us = %3.2f [DML]:DML_RQ_DLG_CALC: deepsleep_dcfclk_mhz = %3.2f [DML]:DML_RQ_DLG_CALC: total_flip_bw = %3.2f [DML]:DML_RQ_DLG_CALC: total_flip_bytes = %i [DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_REGS_ST [DML]:DML_RQ_DLG_CALC: chunk_size = 0x%0x [DML]:DML_RQ_DLG_CALC: min_chunk_size = 0x%0x [DML]:DML_RQ_DLG_CALC: meta_chunk_size = 0x%0x [DML]:DML_RQ_DLG_CALC: min_meta_chunk_size = 0x%0x [DML]:DML_RQ_DLG_CALC: dpte_group_size = 0x%0x [DML]:DML_RQ_DLG_CALC: mpte_group_size = 0x%0x [DML]:DML_RQ_DLG_CALC: swath_height = 0x%0x [DML]:DML_RQ_DLG_CALC: pte_row_height_linear = 0x%0x [DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_REGS_ST [DML]:DML_RQ_DLG_CALC: drq_expansion_mode = 0x%0x [DML]:DML_RQ_DLG_CALC: prq_expansion_mode = 0x%0x [DML]:DML_RQ_DLG_CALC: mrq_expansion_mode = 0x%0x [DML]:DML_RQ_DLG_CALC: crq_expansion_mode = 0x%0x [DML]:DML_RQ_DLG_CALC: plane1_base_address = 0x%0x [DML]:DML_RQ_DLG_CALC: DISPLAY_DLG_REGS_ST [DML]:DML_RQ_DLG_CALC: refcyc_h_blank_end = 0x%0x [DML]:DML_RQ_DLG_CALC: dlg_vblank_end = 0x%0x [DML]:DML_RQ_DLG_CALC: min_dst_y_next_start = 0x%0x [DML]:DML_RQ_DLG_CALC: refcyc_per_htotal = 0x%0x [DML]:DML_RQ_DLG_CALC: refcyc_x_after_scaler = 0x%0x [DML]:DML_RQ_DLG_CALC: dst_y_after_scaler = 0x%0x [DML]:DML_RQ_DLG_CALC: dst_y_prefetch = 0x%0x [DML]:DML_RQ_DLG_CALC: dst_y_per_vm_vblank = 0x%0x [DML]:DML_RQ_DLG_CALC: dst_y_per_row_vblank = 0x%0x [DML]:DML_RQ_DLG_CALC: dst_y_per_vm_flip = 0x%0x [DML]:DML_RQ_DLG_CALC: dst_y_per_row_flip = 0x%0x [DML]:DML_RQ_DLG_CALC: ref_freq_to_pix_freq = 0x%0x [DML]:DML_RQ_DLG_CALC: vratio_prefetch = 0x%0x [DML]:DML_RQ_DLG_CALC: vratio_prefetch_c = 0x%0x [DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_l = 0x%0x [DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_c = 0x%0x [DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_l = 0x%0x [DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_c = 0x%0x [DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_l = 0x%0x [DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_c = 0x%0x [DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_flip_l = 0x%0x [DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_flip_c = 0x%0x [DML]:DML_RQ_DLG_CALC: dst_y_per_pte_row_nom_l = 0x%0x [DML]:DML_RQ_DLG_CALC: dst_y_per_pte_row_nom_c = 0x%0x [DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_l = 0x%0x [DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_c = 0x%0x [DML]:DML_RQ_DLG_CALC: dst_y_per_meta_row_nom_l = 0x%0x [DML]:DML_RQ_DLG_CALC: dst_y_per_meta_row_nom_c = 0x%0x [DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_l = 0x%0x [DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_c = 0x%0x [DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_pre_l = 0x%0x [DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_pre_c = 0x%0x [DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_l = 0x%0x [DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_c = 0x%0x [DML]:DML_RQ_DLG_CALC: chunk_hdl_adjust_cur0 = 0x%0x [DML]:DML_RQ_DLG_CALC: dst_y_offset_cur1 = 0x%0x [DML]:DML_RQ_DLG_CALC: chunk_hdl_adjust_cur1 = 0x%0x [DML]:DML_RQ_DLG_CALC: vready_after_vcount0 = 0x%0x [DML]:DML_RQ_DLG_CALC: dst_y_delta_drq_limit = 0x%0x [DML]:DML_RQ_DLG_CALC: xfc_reg_transfer_delay = 0x%0x [DML]:DML_RQ_DLG_CALC: xfc_reg_precharge_delay = 0x%0x [DML]:DML_RQ_DLG_CALC: xfc_reg_remote_surface_flip_latency = 0x%0x [DML]:DML_RQ_DLG_CALC: refcyc_per_vm_dmdata = 0x%0x [DML]:DML_RQ_DLG_CALC: DISPLAY_TTU_REGS_ST [DML]:DML_RQ_DLG_CALC: qos_level_low_wm = 0x%0x [DML]:DML_RQ_DLG_CALC: qos_level_high_wm = 0x%0x [DML]:DML_RQ_DLG_CALC: min_ttu_vblank = 0x%0x [DML]:DML_RQ_DLG_CALC: qos_level_flip = 0x%0x [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_l = 0x%0x [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_l = 0x%0x [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_c = 0x%0x [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_c = 0x%0x [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur0 = 0x%0x [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur0 = 0x%0x [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur1 = 0x%0x [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur1 = 0x%0x [DML]:DML_RQ_DLG_CALC: qos_level_fixed_l = 0x%0x [DML]:DML_RQ_DLG_CALC: qos_ramp_disable_l = 0x%0x [DML]:DML_RQ_DLG_CALC: qos_level_fixed_c = 0x%0x [DML]:DML_RQ_DLG_CALC: qos_ramp_disable_c = 0x%0x [DML]:DML_RQ_DLG_CALC: qos_level_fixed_cur0 = 0x%0x [DML]:DML_RQ_DLG_CALC: qos_ramp_disable_cur0 = 0x%0x [DML]:DML_RQ_DLG_CALC: qos_level_fixed_cur1 = 0x%0x [DML]:DML_RQ_DLG_CALC: qos_ramp_disable_cur1 = 0x%0x drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_rq_dlg_helpers.c[DML]:DLG: %s: refclk_freq_in_mhz = %3.2f[DML]:DLG: %s: pclk_freq_in_mhz = %3.2f[DML]:DLG: %s: recout_width = %d[DML]:DLG: %s: vratio = %3.2f[DML]:DLG: %s: req_per_swath_ub = %d[DML]:DLG: %s: refcyc_per_delivery= %3.2f[DML]:DLG: %s: max_num_sw = %0d[DML]:DLG: %s: max_partial_sw = %0d[DML]:DLG: %s: swath_height = %0d[DML]:DLG: %s: vinit = %3.2f[DML]:DLG: %s: vratio_pre = %3.2f[DML]:WARNING_DLG: %s: vratio_pre=%3.2f < 1.0, set to 1.0[DML]:WARNING_DLG: %s: vratio_pre=%3.2f > 4.0 (max scaling ratio). set to 4.0drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dml1_display_rq_dlg_calc.c[DML]:DLG: %s: rq_sizing param[DML]:DLG: %s: surf_linear = %d[DML]:DLG: %s: surf_vert = %d[DML]:DLG: %s: blk256_width = %d[DML]:DLG: %s: blk256_height = %d[DML]:DLG: %s: meta_blk_height = %d[DML]:DLG: %s: meta_blk_width = %d[DML]:DLG: %s: meta_surface_bytes = %d[DML]:DLG: %s: meta_pte_req_per_frame_ub = %d[DML]:DLG: %s: meta_pte_bytes_per_frame_ub = %d[DML]:MISMATCH: rq_dlg_param->meta_row_height = %d[DML]:MISMATCH: func_meta_row_height = %d[DML]:MISMATCH: rq_dlg_param->dpte_row_height = %d[DML]:MISMATCH: func_dpte_row_height = %d[DML]:DLG: %s: bug workaround DEGVIDCN10-137[DML]:DLG: %s: full_swath_bytes_packed_l = %0d[DML]:DLG: %s: full_swath_bytes_packed_c = %0d[DML]:DLG: %s: dppclk_freq_in_mhz = %3.2f[DML]:DLG: %s: dispclk_freq_in_mhz = %3.2f[DML]:DLG: %s: refclk_freq_in_mhz = %3.2f[DML]:DLG: %s: pclk_freq_in_mhz = %3.2f[DML]:DLG: %s: interlaced = %d[DML]:DLG: %s: min_dcfclk_mhz = %3.2f[DML]:DLG: %s: min_ttu_vblank = %3.2f[DML]:DLG: %s: min_dst_y_ttu_vblank = %3.2f[DML]:DLG: %s: t_calc_us = %3.2f[DML]:DLG: %s: disp_dlg_regs->min_dst_y_next_start = 0x%0x[DML]:DLG: %s: ref_freq_to_pix_freq = %3.2f[DML]:WARNING_DLG: %s: vblank_start=%d vblank_end=%d[DML]:WARNING_DLG: %s: vstartup_start=%d should be less than min_vblank=%d[DML]:DLG: %s: htotal = %d[DML]:DLG: %s: pixel_rate_delay_subtotal = %d[DML]:DLG: %s: dst_x_after_scaler = %d[DML]:DLG: %s: dst_y_after_scaler = %d[DML]:DLG: %s: soc.sr_enter_plus_exit_time_us = %3.2f[DML]:DLG: %s: soc.dram_clock_change_latency_us = %3.2f[DML]:DLG: %s: soc.urgent_latency_us = %3.2f[DML]:DLG: %s: swath_height_l = %d[DML]:DLG: %s: swath_height_c = %d[DML]:DLG: %s: t_srx_delay_us = %3.2f[DML]:DLG: %s: line_time_in_us = %3.2f[DML]:DLG: %s: vupdate_offset = %d[DML]:DLG: %s: vupdate_width = %d[DML]:DLG: %s: vready_offset = %d[DML]:DLG: %s: line_wait = %3.2f[DML]:DLG: %s: line_o = %3.2f[DML]:DLG: %s: line_setup = %3.2f[DML]:DLG: %s: line_calc = %3.2f[DML]:DLG: %s: dst_y_prefetch (before rnd) = %3.2f[DML]:DLG: %s: dst_y_prefetch (after rnd) = %3.2f[DML]:DLG: %s: sw_bytes_ub_l = %d[DML]:DLG: %s: sw_bytes_ub_c = %d[DML]:DLG: %s: sw_bytes = %d[DML]:DLG: %s: vm_bytes = %d[DML]:DLG: %s: meta_row_bytes = %d[DML]:DLG: %s: dpte_row_bytes = %d[DML]:DLG: %s: disp_dlg_regs->dst_y_after_scaler = 0x%0x[DML]:DLG: %s: disp_dlg_regs->refcyc_x_after_scaler = 0x%0x[DML]:DLG: %s: disp_dlg_regs->dst_y_prefetch = %d[DML]:DLG: %s: lsw_l = %d[DML]:DLG: %s: lsw_c = %d[DML]:DLG: %s: dpte_bytes_per_row_ub_l = %d[DML]:DLG: %s: dpte_bytes_per_row_ub_c = %d[DML]:DLG: %s: prefetch_bw = %3.2f[DML]:DLG: %s: flip_bw = %3.2f[DML]:DLG: %s: t_pre_us = %3.2f[DML]:DLG: %s: t_vm_us = %3.2f[DML]:DLG: %s: t_r0_us = %3.2f[DML]:DLG: %s: dst_y_per_vm_vblank = %3.2f[DML]:DLG: %s: dst_y_per_row_vblank = %3.2f[DML]:DLG: %s: dst_y_prefetch = %3.2f[DML]:DLG: %s: vratio_pre_l=%3.2f[DML]:DLG: %s: vratio_pre_c=%3.2f[DML]:DLG: %s: Warningfull_recout_width not set in hsplit mode[DML]:DLG: %s: full_recout_width = %d[DML]:DLG: %s: hscale_pixel_rate_l = %3.2f[DML]:DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f[DML]:DLG: %s: refcyc_per_line_delivery_l = %3.2f[DML]:DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f[DML]:DLG: %s: refcyc_per_line_delivery_c = %3.2f[DML]:DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f[DML]:DLG: %s: refcyc_per_req_delivery_l = %3.2f[DML]:DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f[DML]:DLG: %s: refcyc_per_req_delivery_c = %3.2f[DML]:DLG: %s: cur0_req_width = %d[DML]:DLG: %s: cur0_width_ub = %3.2f[DML]:DLG: %s: cur0_req_per_width = %3.2f[DML]:DLG: %s: hactive_cur0 = %3.2f[DML]:DLG: %s: refcyc_per_req_delivery_pre_cur0 = %3.2f[DML]:DLG: %s: refcyc_per_req_delivery_cur0 = %3.2f[DML]:ERROR: ODM Combine is specified but is_hsplit has not be specified for pipe %i drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_vba.cdrivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c[DML]:DML_DLG: %s: cur_req_width = %d [DML]:DML_DLG: %s: cur_width_ub = %3.2f [DML]:DML_DLG: %s: cur_req_per_width = %3.2f [DML]:DML_DLG: %s: hactive_cur = %3.2f [DML]:DML_DLG: %s: refcyc_per_req_delivery_pre_cur = %3.2f [DML]:DML_DLG: %s: refcyc_per_req_delivery_cur = %3.2f [DML]:DML_DLG: %s: refclk_freq_in_mhz = %3.2f [DML]:DML_DLG: %s: pclk_freq_in_mhz = %3.2f [DML]:DML_DLG: %s: recout_width = %d [DML]:DML_DLG: %s: vratio = %3.2f [DML]:DML_DLG: %s: req_per_swath_ub = %d [DML]:DML_DLG: %s: refcyc_per_delivery= %3.2f [DML]:DML_DLG: %s: cstate_en = %d [DML]:DML_DLG: %s: pstate_en = %d [DML]:DML_DLG: %s: dppclk_freq_in_mhz = %3.2f [DML]:DML_DLG: %s: dispclk_freq_in_mhz = %3.2f [DML]:DML_DLG: %s: refclk_freq_in_mhz = %3.2f [DML]:DML_DLG: %s: pclk_freq_in_mhz = %3.2f [DML]:DML_DLG: %s: interlaced = %d [DML]:DML_DLG: %s: min_dcfclk_mhz = %3.2f [DML]:DML_DLG: %s: min_ttu_vblank = %3.2f [DML]:DML_DLG: %s: min_dst_y_ttu_vblank = %3.2f [DML]:DML_DLG: %s: t_calc_us = %3.2f [DML]:DML_DLG: %s: disp_dlg_regs->min_dst_y_next_start = 0x%0x [DML]:DML_DLG: %s: ref_freq_to_pix_freq = %3.2f [DML]:WARNING: DML_DLG: %s: vblank_start=%d vblank_end=%d [DML]:WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d [DML]:DML_DLG: %s: htotal = %d [DML]:DML_DLG: %s: pixel_rate_delay_subtotal = %d [DML]:DML_DLG: %s: dst_x_after_scaler = %d [DML]:DML_DLG: %s: dst_y_after_scaler = %d [DML]:DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f [DML]:DML_DLG: %s: dst_y_per_vm_vblank = %3.2f [DML]:DML_DLG: %s: dst_y_per_row_vblank = %3.2f [DML]:DML_DLG: %s: lsw = %3.2f [DML]:DML_DLG: %s: vratio_pre_l=%3.2f [DML]:DML_DLG: %s: vratio_pre_c=%3.2f [DML]:DML_DLG: %s: Warning: full_recout_width not set in hsplit mode [DML]:DML_DLG: %s: full_recout_width = %d [DML]:DML_DLG: %s: hscale_pixel_rate_l = %3.2f [DML]:DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f [DML]:DML_DLG: %s: refcyc_per_line_delivery_l = %3.2f [DML]:DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f [DML]:DML_DLG: %s: refcyc_per_line_delivery_c = %3.2f [DML]:DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f [DML]:DML_DLG: %s: refcyc_per_req_delivery_l = %3.2f [DML]:DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f [DML]:DML_DLG: %s: refcyc_per_req_delivery_c = %3.2f [DML]:DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u larger than supported by register format U15.2 %u [DML]:DML_DLG: %s: rq_sizing param [DML]:DML_DLG: %s: surf_linear = %d [DML]:DML_DLG: %s: surf_vert = %d [DML]:DML_DLG: %s: blk256_width = %d [DML]:DML_DLG: %s: blk256_height = %d [DML]:DML_DLG: %s: meta_blk_height = %d [DML]:DML_DLG: %s: meta_blk_width = %d [DML]:DML_DLG: %s: meta_surface_bytes = %d [DML]:DML_DLG: %s: meta_pte_req_per_frame_ub = %d [DML]:DML_DLG: %s: meta_pte_bytes_per_frame_ub = %d [DML]:DML_DLG: %s: req128_l = %0d [DML]:DML_DLG: %s: req128_c = %0d [DML]:DML_DLG: %s: full_swath_bytes_packed_l = %0d [DML]:DML_DLG: %s: full_swath_bytes_packed_c = %0d [DML]:DML_DLG: Calculation for pipe[%d] start [DML]:DML_DLG: Calculation for pipe[%d] end [DML]:WARNING DML: using viewport y position of 0 even though actual viewport y position is non-zero in prefetch source lines calculation [DML]:DML::CalculateRemoteSurfaceFlipDelay: SrcActiveDrainRate: %f [DML]:DML::CalculateRemoteSurfaceFlipDelay: TSlvSetup: %f [DML]:DML::CalculateRemoteSurfaceFlipDelay: TInitXFill: %f [DML]:DML::CalculateRemoteSurfaceFlipDelay: AvgfillRate: %f [DML]:DML::CalculateRemoteSurfaceFlipDelay: TslvChk: %f [DML]:DML::CalculateRemoteSurfaceFlipDelay: RemoteSurfaceFlipDelay: %f [DML]:DML: XFCRemoteSurfaceFlipDelay: %f [DML]:DML: DSTYAfterScaler: %f [DML]:DML: DSTXAfterScaler: %f drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_mode_vba_20.c[DML]: dispclk_mhz (calculated) = %f[DML]: dppclk_mhz[%i] (calculated) = %f[DML]: dcfclk_mhz = %f[DML]: return_bw_to_dcn = %f[DML]: return_bus_bw = %f[DML]: urgent_extra_latency = %fus[DML]: wm_pstate_change = %fus[DML]: calculating wb pstate watermark[DML]: total wb outputs %d[DML]: socclk frequency %f Mhz[DML]: dcfclk_deepsleep_per_plane[%i] = %fMHz[DML]: dcfclk_deepsleep_mhz = %fMHz[DML]: wm_cstate_exit = %fus[DML]: wm_cstate_enter_exit = %fus[DML]:DML: CalculatePrefetchSchedule ***failed***. Bandwidth violation. Results are NOT valid [DML]:DML: CalculatePrefetchSchedule ***failed***. Prefetch schedule violation. Results are NOT valid drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c[DML]:DML_DLG: %s: cur_req_width = %d [DML]:DML_DLG: %s: cur_width_ub = %3.2f [DML]:DML_DLG: %s: cur_req_per_width = %3.2f [DML]:DML_DLG: %s: hactive_cur = %3.2f [DML]:DML_DLG: %s: refcyc_per_req_delivery_pre_cur = %3.2f [DML]:DML_DLG: %s: refcyc_per_req_delivery_cur = %3.2f [DML]:DML_DLG: %s: refclk_freq_in_mhz = %3.2f [DML]:DML_DLG: %s: pclk_freq_in_mhz = %3.2f [DML]:DML_DLG: %s: recout_width = %d [DML]:DML_DLG: %s: vratio = %3.2f [DML]:DML_DLG: %s: req_per_swath_ub = %d [DML]:DML_DLG: %s: refcyc_per_delivery= %3.2f [DML]:DML_DLG: %s: cstate_en = %d [DML]:DML_DLG: %s: pstate_en = %d [DML]:DML_DLG: %s: dppclk_freq_in_mhz = %3.2f [DML]:DML_DLG: %s: dispclk_freq_in_mhz = %3.2f [DML]:DML_DLG: %s: refclk_freq_in_mhz = %3.2f [DML]:DML_DLG: %s: pclk_freq_in_mhz = %3.2f [DML]:DML_DLG: %s: interlaced = %d [DML]:DML_DLG: %s: min_dcfclk_mhz = %3.2f [DML]:DML_DLG: %s: min_ttu_vblank = %3.2f [DML]:DML_DLG: %s: min_dst_y_ttu_vblank = %3.2f [DML]:DML_DLG: %s: t_calc_us = %3.2f [DML]:DML_DLG: %s: disp_dlg_regs->min_dst_y_next_start = 0x%0x [DML]:DML_DLG: %s: ref_freq_to_pix_freq = %3.2f [DML]:WARNING: DML_DLG: %s: vblank_start=%d vblank_end=%d [DML]:WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d [DML]:DML_DLG: %s: htotal = %d [DML]:DML_DLG: %s: pixel_rate_delay_subtotal = %d [DML]:DML_DLG: %s: dst_x_after_scaler = %d [DML]:DML_DLG: %s: dst_y_after_scaler = %d [DML]:DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f [DML]:DML_DLG: %s: dst_y_per_vm_vblank = %3.2f [DML]:DML_DLG: %s: dst_y_per_row_vblank = %3.2f [DML]:DML_DLG: %s: lsw = %3.2f [DML]:DML_DLG: %s: vratio_pre_l=%3.2f [DML]:DML_DLG: %s: vratio_pre_c=%3.2f [DML]:DML_DLG: %s: Warning: full_recout_width not set in hsplit mode [DML]:DML_DLG: %s: full_recout_width = %d [DML]:DML_DLG: %s: hscale_pixel_rate_l = %3.2f [DML]:DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f [DML]:DML_DLG: %s: refcyc_per_line_delivery_l = %3.2f [DML]:DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f [DML]:DML_DLG: %s: refcyc_per_line_delivery_c = %3.2f [DML]:DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f [DML]:DML_DLG: %s: refcyc_per_req_delivery_l = %3.2f [DML]:DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f [DML]:DML_DLG: %s: refcyc_per_req_delivery_c = %3.2f [DML]:DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u larger than supported by register format U15.2 %u [DML]:DML_DLG: %s: rq_sizing param [DML]:DML_DLG: %s: surf_linear = %d [DML]:DML_DLG: %s: surf_vert = %d [DML]:DML_DLG: %s: blk256_width = %d [DML]:DML_DLG: %s: blk256_height = %d [DML]:DML_DLG: %s: meta_blk_height = %d [DML]:DML_DLG: %s: meta_blk_width = %d [DML]:DML_DLG: %s: meta_surface_bytes = %d [DML]:DML_DLG: %s: meta_pte_req_per_frame_ub = %d [DML]:DML_DLG: %s: meta_pte_bytes_per_frame_ub = %d [DML]:DML_DLG: %s: req128_l = %0d [DML]:DML_DLG: %s: req128_c = %0d [DML]:DML_DLG: %s: full_swath_bytes_packed_l = %0d [DML]:DML_DLG: %s: full_swath_bytes_packed_c = %0d [DML]:DML_DLG: Calculation for pipe[%d] start [DML]:DML_DLG: Calculation for pipe[%d] end [DML]:WARNING DML: using viewport y position of 0 even though actual viewport y position is non-zero in prefetch source lines calculation [DML]:DML::CalculateRemoteSurfaceFlipDelay: SrcActiveDrainRate: %f [DML]:DML::CalculateRemoteSurfaceFlipDelay: TSlvSetup: %f [DML]:DML::CalculateRemoteSurfaceFlipDelay: TInitXFill: %f [DML]:DML::CalculateRemoteSurfaceFlipDelay: AvgfillRate: %f [DML]:DML::CalculateRemoteSurfaceFlipDelay: TslvChk: %f [DML]:DML::CalculateRemoteSurfaceFlipDelay: RemoteSurfaceFlipDelay: %f [DML]:DML: XFCRemoteSurfaceFlipDelay: %f [DML]:DML: DSTYAfterScaler: %f [DML]:DML: DSTXAfterScaler: %f drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_mode_vba_20v2.c[DML]: dispclk_mhz (calculated) = %f[DML]: dppclk_mhz[%i] (calculated) = %f[DML]: dcfclk_mhz = %f[DML]: return_bw_to_dcn = %f[DML]: return_bus_bw = %f[DML]: urgent_extra_latency = %fus[DML]: wm_pstate_change = %fus[DML]: calculating wb pstate watermark[DML]: total wb outputs %d[DML]: socclk frequency %f Mhz[DML]: dcfclk_deepsleep_per_plane[%i] = %fMHz[DML]: dcfclk_deepsleep_mhz = %fMHz[DML]: wm_cstate_exit = %fus[DML]: wm_cstate_enter_exit = %fus[DML]:DML: CalculatePrefetchSchedule ***failed***. Bandwidth violation. Results are NOT valid [DML]:DML: CalculatePrefetchSchedule ***failed***. Prefetch schedule violation. Results are NOT valid drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn21/display_rq_dlg_calc_21.c[DML]:DML_DLG: %s: cur_req_width = %d [DML]:DML_DLG: %s: cur_width_ub = %3.2f [DML]:DML_DLG: %s: cur_req_per_width = %3.2f [DML]:DML_DLG: %s: hactive_cur = %3.2f [DML]:DML_DLG: %s: refcyc_per_req_delivery_pre_cur = %3.2f [DML]:DML_DLG: %s: refcyc_per_req_delivery_cur = %3.2f [DML]:DML_DLG: %s: refclk_freq_in_mhz = %3.2f [DML]:DML_DLG: %s: pclk_freq_in_mhz = %3.2f [DML]:DML_DLG: %s: recout_width = %d [DML]:DML_DLG: %s: vratio = %3.2f [DML]:DML_DLG: %s: req_per_swath_ub = %d [DML]:DML_DLG: %s: refcyc_per_delivery= %3.2f [DML]:DML_DLG: %s: cstate_en = %d [DML]:DML_DLG: %s: pstate_en = %d [DML]:DML_DLG: %s: dppclk_freq_in_mhz = %3.2f [DML]:DML_DLG: %s: dispclk_freq_in_mhz = %3.2f [DML]:DML_DLG: %s: refclk_freq_in_mhz = %3.2f [DML]:DML_DLG: %s: pclk_freq_in_mhz = %3.2f [DML]:DML_DLG: %s: interlaced = %d [DML]:DML_DLG: %s: min_dcfclk_mhz = %3.2f [DML]:DML_DLG: %s: min_ttu_vblank = %3.2f [DML]:DML_DLG: %s: min_dst_y_ttu_vblank = %3.2f [DML]:DML_DLG: %s: t_calc_us = %3.2f [DML]:DML_DLG: %s: disp_dlg_regs->min_dst_y_next_start = 0x%0x [DML]:DML_DLG: %s: ref_freq_to_pix_freq = %3.2f [DML]:WARNING: DML_DLG: %s: vblank_start=%d vblank_end=%d [DML]:WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d [DML]:DML_DLG: %s: htotal = %d [DML]:DML_DLG: %s: pixel_rate_delay_subtotal = %d [DML]:DML_DLG: %s: dst_x_after_scaler = %d [DML]:DML_DLG: %s: dst_y_after_scaler = %d [DML]:DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f [DML]:DML_DLG: %s: dst_y_per_vm_flip = %3.2f [DML]:DML_DLG: %s: dst_y_per_row_flip = %3.2f [DML]:DML_DLG: %s: dst_y_per_vm_vblank = %3.2f [DML]:DML_DLG: %s: dst_y_per_row_vblank = %3.2f [DML]:DML_DLG: %s: lsw = %3.2f [DML]:DML_DLG: %s: vratio_pre_l=%3.2f [DML]:DML_DLG: %s: vratio_pre_c=%3.2f [DML]:DML_DLG: %s: Warning: full_recout_width not set in hsplit mode [DML]:DML_DLG: %s: full_recout_width = %d [DML]:DML_DLG: %s: hscale_pixel_rate_l = %3.2f [DML]:DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f [DML]:DML_DLG: %s: refcyc_per_line_delivery_l = %3.2f [DML]:DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f [DML]:DML_DLG: %s: refcyc_per_line_delivery_c = %3.2f [DML]:DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f [DML]:DML_DLG: %s: refcyc_per_req_delivery_l = %3.2f [DML]:DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f [DML]:DML_DLG: %s: refcyc_per_req_delivery_c = %3.2f [DML]:DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_vblank = 0x%x [DML]:DML_DLG: %s: disp_dlg_regs->dst_y_per_row_vblank = 0x%x [DML]:DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_flip = 0x%x [DML]:DML_DLG: %s: disp_dlg_regs->dst_y_per_row_flip = 0x%x [DML]:DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u larger than supported by register format U15.2 %u [DML]:DML_DLG: %s: rq_sizing param [DML]:DML_DLG: %s: surf_linear = %d [DML]:DML_DLG: %s: surf_vert = %d [DML]:DML_DLG: %s: blk256_width = %d [DML]:DML_DLG: %s: blk256_height = %d [DML]:DML_DLG: %s: meta_blk_height = %d [DML]:DML_DLG: %s: meta_blk_width = %d [DML]:DML_DLG: %s: meta_surface_bytes = %d [DML]:DML_DLG: %s: meta_pte_req_per_frame_ub = %d [DML]:DML_DLG: %s: meta_pte_bytes_per_frame_ub = %d [DML]:DML_DLG: %s: vp_width = %d [DML]:DML_DLG: %s: vp_height = %d [DML]:DML_DLG: %s: full_src_vp_width = %d [DML]:DML_DLG: %s: hactive_half = %d [DML]:DML_DLG: %s: src_hactive_half = %d [DML]:DML_DLG: %s: req128_l = %0d [DML]:DML_DLG: %s: req128_c = %0d [DML]:DML_DLG: %s: full_swath_bytes_packed_l = %0d [DML]:DML_DLG: %s: full_swath_bytes_packed_c = %0d [DML]:DML_DLG: Calculation for pipe[%d] start [DML]:DML_DLG: Calculation for pipe[%d] end [DML]:WARNING DML: using viewport y position of 0 even though actual viewport y position is non-zero in prefetch source lines calculation [DML]:DML::CalculateRemoteSurfaceFlipDelay: SrcActiveDrainRate: %f [DML]:DML::CalculateRemoteSurfaceFlipDelay: TSlvSetup: %f [DML]:DML::CalculateRemoteSurfaceFlipDelay: TInitXFill: %f [DML]:DML::CalculateRemoteSurfaceFlipDelay: AvgfillRate: %f [DML]:DML::CalculateRemoteSurfaceFlipDelay: TslvChk: %f [DML]:DML::CalculateRemoteSurfaceFlipDelay: RemoteSurfaceFlipDelay: %f [DML]:DML: vm_bytes = meta_pte_bytes_per_frame (per_pipe) = MetaPTEBytesFrame = : %d [DML]:DML: XFCRemoteSurfaceFlipDelay: %f [DML]:DML: DSTYAfterScaler: %f [DML]:DML: DSTXAfterScaler: %f [DML]:DML: row_bytes = dpte_row_bytes (per_pipe) = PixelPTEBytesPerRow = : %d drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn21/display_mode_vba_21.c[DML]: dispclk_mhz (calculated) = %f[DML]: dppclk_mhz[%i] (calculated) = %f[DML]: dcfclk_mhz = %f[DML]: return_bw_to_dcn = %f[DML]: return_bus_bw = %f[DML]:DML: CalculatePrefetchSchedule ***failed***. Bandwidth violation. Results are NOT valid [DML]:DML: CalculatePrefetchSchedule ***failed***. Prefetch schedule violation. Results are NOT valid [BANDWIDTH_CALCS]:URGENCY_WATERMARK_A calculated =%d HW register value = 0x%x [BANDWIDTH_CALCS]:URGENCY_WATERMARK_B calculated =%d HW register value = 0x%x [BANDWIDTH_CALCS]:URGENCY_WATERMARK_C calculated =%d HW register value = 0x%x [BANDWIDTH_CALCS]:URGENCY_WATERMARK_D calculated =%d HW register value = 0x%x [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_A calculated =%d HW register value = 0x%x [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_A calculated =%d HW register value = 0x%x [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_B calculated =%d HW register value = 0x%x [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_B calculated =%d HW register value = 0x%x [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_C calculated =%d HW register value = 0x%x [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_C calculated =%d HW register value = 0x%x [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_D calculated =%d HW register value = 0x%x [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_D calculated =%d HW register value = 0x%x [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_A calculated =%d HW register value = 0x%x [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_B calculated =%d HW register value = 0x%x [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_C calculated =%d HW register value = 0x%x [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_D calculated =%d HW register value = 0x%x drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_hubbub.cdrivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c4[drm] Mode Validation Warning: %s failed validation. DC: failed to create clock sources! DC: failed to create memory input! DC: failed to create input pixel processor! DC:failed to create aux engine!! DC: failed to create output pixel processor! DC: failed to create display stream compressor %d! DC: failed to create mcif_wb! drivers/gpu/drm/amd/amdgpu/../display/dc/dce120/dce120_resource.cDC: failed to create clock sources! DC: failed to create memory input! DC: failed to create input pixel processor! DC: failed to create transform! DC: failed to create output pixel processor! DC:failed to create aux engine!! DC:failed to create i2c engine!! 4[drm] %s: wait counter exceeded, changes to HW not applied4[drm] %s: Unexpected DCE11 compression ratio4[drm] %s: Invalid selected DRAM channels for LPT!!!4[drm] %s: Invalid LPT NUM_PIPES!!!4[drm] %s: Invalid LPT NUM_BANKS!!!4[drm] %s: Invalid LPT INTERLEAVE_SIZE!!!4[drm] %s: Invalid LPT ROW_SIZE!!!4[drm] %s: LPT MC Configuration is not provided%s: Bandwidth validation failed![BANDWIDTH_CALCS]:%s: finish, nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d stutMark_b: %d stutMark_a: %d nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d stutMark_b: %d stutMark_a: %d nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d drivers/gpu/drm/amd/amdgpu/../display/dc/dce112/dce112_resource.cDC: failed to create clock sources! DC: failed to create memory input! DC:failed to create input pixel processor! DC: failed to create transform! DC:failed to create output pixel processor! DC:failed to create aux engine!! DC:failed to create i2c engine!! drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_timing_generator.c4[drm] %s: wait counter exceeded, changes to HW not applied4[drm] %s: Unexpected DCE11 compression ratioFrame count did not increase for 100ms. drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c%s: wait %lld ms to power on eDP. %s: Panel Power bp_result: %d %s: Skipping Panel Power action: %s %s: panel already powered up. Do nothing. [SURFACE]:Pipe:%d %p: addr hi:0x%x, addr low:0x%x, src: %d, %d, %d, %d; dst: %d, %d, %d, %d;clip: %d, %d, %d, %d [SURFACE]:Pipe %d: width, height, x, y viewport:%d, %d, %d, %d recout: %d, %d, %d, %d Failed to power down pll! (dp clk src) Failed to power down pll! (clk src index=%d) GSL: reset occurred at wait count: %d GSL: Timeout on reset trigger! GSL: waiting for reset to occur. GSL: Restoring register states. drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h%s: %dx%d@%d Bandwidth validation failed! [BANDWIDTH_CALCS]:%s: finish, nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d stutMark_b: %d stutMark_a: %d nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d stutMark_b: %d stutMark_a: %d nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.cDC: failed to create dp clock source! DC: failed to create clock sources! DC: failed to create memory input! DC: failed to create input pixel processor! DC: failed to create transform! DC: failed to create output pixel processor! DC:failed to create aux engine!! DC:failed to create i2c engine!! drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_opp_csc_v.cTiming Sync not supported on underlay pipe drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_mem_input_v.cdrivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_transform_v.c4[drm] %s: Capability not supporteddrivers/gpu/drm/amd/amdgpu/../display/dc/dce100/dce100_resource.cDC: failed to create dp clock source! DC: failed to create clock sources! DC: failed to create memory input! DC: failed to create input pixel processor! DC: failed to create transform! DC: failed to create output pixel processor! DC:failed to create aux engine!! DC:failed to create i2c engine!! drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.cDC: failed to create dp clock source! DC: failed to create clock sources! DC: failed to create memory input! DC: failed to create input pixel processor! DC: failed to create transform! DC: failed to create output pixel processor! DC:failed to create aux engine!! DC:failed to create i2c engine!! 4[drm] CRC capture not supported.drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c%s: failed to create dc->vm_helper %s: failed to create validate ctx DC: Number of connectors %d exceeds maximum of %d! DC: %s: connectors_num: physical:%d, virtual:%d Failed to allocate new validate context! Mode validation failed for stream update! Max EDID buffer size breached! drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.cretimer write to slave_address = 0x%x, offset = 0x%x, reg_val= 0x%x, i2c_success = %d retimer write to slave_address = 0x%x, offset = 0x%x, reg_val = 0x%x, i2c_success = %d above 340Mhz: retimer write to slave_address = 0x%x, offset = 0x%x, reg_val = 0x%x, i2c_success = %d retimer write to slave_address = 0x%x, offset = 0x%x, reg_val = 0x%x, i2c_success = %d retimer write to slave_address = 0x%x, offset = 0x%x, reg_val = 0x%x, i2c_success = %d retimer write to slave_address = 0x%x, offset = 0x%x, reg_val = 0x%x, i2c_success = %d retimer writes default setting to slave_address = 0x%x, offset = 0x%x, reg_val = 0x%x, i2c_success = %d retimer write to slave_addr = 0x%x, offset = 0x%x, reg_val = 0x%x, i2c_success = %d retimer write to slave_addr = 0x%x, offset = 0x%x, reg_val= 0x%x, i2c_success = %d retimer write to slave_addr = 0x%x, offset = 0x%x, reg_val = 0x%x, i2c_success = %d retimer write to slave_addr = 0x%x, offset = 0x%x, reg_val= 0x%x, i2c_success = %d retimer write default setting to slave_addr = 0x%x, offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here redriver write 0 to all 16 reg offset expect following: slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x, offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x, i2c_success = %d %s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d 4[drm] Unsupported Connector type:%d! Connector[%d] description:signal %d Failed to create ddc_service! Failed to get I2C info for connector! Failed to create link encoder! 4[drm] DP Alt mode state on HPD: %d 4[drm] Alt mode entered finished after %llu ms 4[drm] Alt mode has timed out after %llu ms link=%d, mst branch is now Connected Invalid connector type! signal:%d %s: manufacturer_id = %X, product_id = %X, serial_number = %X, manufacture_week = %d, manufacture_year = %d, display_name = %s, speaker_flag = %d, audio_mode_count = %d %s: mode number = %d, format_code = %d, channel_count = %d, sample_rate = %d, sample_size = %d link=%d, mst branch is now Disconnected link=%d, dc_sink_in=%p is now %s prev_sink=%p dpcd same=%d edid same=%d New Backlight level: %d (0x%X) 4[drm] Failed to updateMST allocation table forpipe idx:%d stream_enc[%d]: %p stream[%d].vcp_id: %d stream[%d].slot_count: %d drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h4[drm] enabling link %u failed: %d drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_resource.cdrivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.hDC: failed to create stream_encoder! [SCALER]:%s: Viewport: height:%d width:%d x:%d y:%d dst_rect: height:%d width:%d x:%d y:%d Existing stream not found; failed to attach surface! Surface: can not attach plane_state %p! Maximum is: %d Head pipe not found for stream_state %p ! Existing stream not found; failed to remove plane. Existing plane_state not found; failed to detach it! Existing stream %p not found! 4[drm] Max streams reached, can't add stream %p ! 4[drm] Adding stream %p to context failed with err %d! Pipe not found for stream %p ! Context doesn't have stream %p ! Stream %p not found in new ctx! drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_surface.c bytes_per_pixel 0x%08x (%d.%07d)drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_hwss.cSetting stream encoder DSC config for engine %d:Setting optc DSC config for tg instance %d:Setting stream encoder DSC PPS SDP for engine %d [HW_LINK_TRAINING]:%s %x VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x [HW_LINK_TRAINING]:%s %x rate = %x %x lane = %x framing = %x %x spread = %x [HW_LINK_TRAINING]:%s %x rate set = %x %x lane = %x framing = %x %x spread = %x %s: DPCD read failed to obtain power state. drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c[HW_LINK_TRAINING]:%s: Invalid HW Training pattern: %d [HW_LINK_TRAINING]:%s %x pattern = %x [HW_LINK_TRAINING]:%s: %x VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x [HW_LINK_TRAINING]:%s: %x Lane01Status = %x %x Lane23Status = %x [HW_LINK_TRAINING]:%s: %x Lane01AdjustRequest = %x %x Lane23AdjustRequest = %x 4[drm] %s: Post Link Training Adjust Request Timed out 4[drm] %s: Post Link Training Adjust Request limit reached [HW_LINK_TRAINING]:%s: wait = %d %s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue%s: Read extend caps data failed, use cap from dpcd 0. %s: Read DPRX caps data failed. Link: %d eDP panel mode supported: %d eDP panel mode enabled: %d dpcd write failed to set fec_ready%s: Got short pulse HPD on link %d %s: DPCD read failed to obtain irq data %s: skipping HPD handling on %d drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_ddc.cType 2 DP-HDMI passive dongle %dMhz: Type 2 DP-HDMI passive dongle (no signature) %dMhz: Type 1 DP-HDMI passive dongle %dMhz: Type 1 DP-HDMI passive dongle (no signature) %dMhz: [IF_TRACE]:plane_state->visible = %d; plane_state->flip_immediate = %d; plane_state->address.type = %d; plane_state->address.grph.addr.quad_part = 0x%llX; plane_state->address.grph.meta_addr.quad_part = 0x%llX; plane_state->scaling_quality.h_taps = %d; plane_state->scaling_quality.v_taps = %d; plane_state->scaling_quality.h_taps_c = %d; plane_state->scaling_quality.v_taps_c = %d; [IF_TRACE]:plane_state->src_rect.x = %d; plane_state->src_rect.y = %d; plane_state->src_rect.width = %d; plane_state->src_rect.height = %d; plane_state->dst_rect.x = %d; plane_state->dst_rect.y = %d; plane_state->dst_rect.width = %d; plane_state->dst_rect.height = %d; plane_state->clip_rect.x = %d; plane_state->clip_rect.y = %d; plane_state->clip_rect.width = %d; plane_state->clip_rect.height = %d; [IF_TRACE]:plane_state->plane_size.surface_size.x = %d; plane_state->plane_size.surface_size.y = %d; plane_state->plane_size.surface_size.width = %d; plane_state->plane_size.surface_size.height = %d; plane_state->plane_size.surface_pitch = %d; [IF_TRACE]:plane_state->tiling_info.gfx8.num_banks = %d; plane_state->tiling_info.gfx8.bank_width = %d; plane_state->tiling_info.gfx8.bank_width_c = %d; plane_state->tiling_info.gfx8.bank_height = %d; plane_state->tiling_info.gfx8.bank_height_c = %d; plane_state->tiling_info.gfx8.tile_aspect = %d; plane_state->tiling_info.gfx8.tile_aspect_c = %d; plane_state->tiling_info.gfx8.tile_split = %d; plane_state->tiling_info.gfx8.tile_split_c = %d; plane_state->tiling_info.gfx8.tile_mode = %d; plane_state->tiling_info.gfx8.tile_mode_c = %d; [IF_TRACE]:plane_state->tiling_info.gfx8.pipe_config = %d; plane_state->tiling_info.gfx8.array_mode = %d; plane_state->color_space = %d; plane_state->dcc.enable = %d; plane_state->format = %d; plane_state->rotation = %d; plane_state->stereo_format = %d; [IF_TRACE]:plane_state->tiling_info.gfx9.swizzle = %d; [IF_TRACE]:flip_addr->address.type = %d; flip_addr->address.grph.addr.quad_part = 0x%llX; flip_addr->address.grph.meta_addr.quad_part = 0x%llX; flip_addr->flip_immediate = %d; [IF_TRACE]:plane_info->color_space = %d; plane_info->format = %d; plane_info->plane_size.surface_pitch = %d; plane_info->plane_size.surface_size.height = %d; plane_info->plane_size.surface_size.width = %d; plane_info->plane_size.surface_size.x = %d; plane_info->plane_size.surface_size.y = %d; plane_info->rotation = %d; plane_info->stereo_format = %d; [IF_TRACE]:plane_info->tiling_info.gfx8.num_banks = %d; plane_info->tiling_info.gfx8.bank_width = %d; plane_info->tiling_info.gfx8.bank_width_c = %d; plane_info->tiling_info.gfx8.bank_height = %d; plane_info->tiling_info.gfx8.bank_height_c = %d; plane_info->tiling_info.gfx8.tile_aspect = %d; plane_info->tiling_info.gfx8.tile_aspect_c = %d; plane_info->tiling_info.gfx8.tile_split = %d; plane_info->tiling_info.gfx8.tile_split_c = %d; plane_info->tiling_info.gfx8.tile_mode = %d; plane_info->tiling_info.gfx8.tile_mode_c = %d; [IF_TRACE]:plane_info->tiling_info.gfx8.pipe_config = %d; plane_info->tiling_info.gfx8.array_mode = %d; plane_info->visible = %d; plane_info->per_pixel_alpha = %d; [IF_TRACE]:surface->tiling_info.gfx9.swizzle = %d; [IF_TRACE]:scaling_info->src_rect.x = %d; scaling_info->src_rect.y = %d; scaling_info->src_rect.width = %d; scaling_info->src_rect.height = %d; scaling_info->dst_rect.x = %d; scaling_info->dst_rect.y = %d; scaling_info->dst_rect.width = %d; scaling_info->dst_rect.height = %d; scaling_info->clip_rect.x = %d; scaling_info->clip_rect.y = %d; scaling_info->clip_rect.width = %d; scaling_info->clip_rect.height = %d; scaling_info->scaling_quality.h_taps = %d; scaling_info->scaling_quality.v_taps = %d; scaling_info->scaling_quality.h_taps_c = %d; scaling_info->scaling_quality.v_taps_c = %d; [IF_TRACE]:post surface process. OTG_%d H_tot:%d V_tot:%d H_pos:%d V_pos:%d [BANDWIDTH_CALCS]:Current: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d [BANDWIDTH_CALCS]:Calculated: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_debug.cDC: dc_writeback_info is NULL! DC: writeback pipe is invalid! 4[drm] %s:send_immediate_sdp_message not implemented on this ASIC core_stream 0x%p: src: %d, %d, %d, %d; dst: %d, %d, %d, %d, colorSpace:%d pix_clk_khz: %d, h_total: %d, v_total: %d, pixelencoder:%d, displaycolorDepth:%d drivers/gpu/drm/amd/amdgpu/../display/dc/dc_helper.cREG_WAIT taking a while: %dms in %s line:%d 4[drm] REG_WAIT timeout %dus * %d tries - %s line:%d drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services.hdrivers/gpu/drm/amd/amdgpu/../display/modules/color/color_gamma.cdrivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.hdrivers/gpu/drm/amd/amdgpu/../display/modules/power/power_helpers.camdgpudrmfb6[drm] retry init %d ,amdgpuAMD GPU20150101%llu ib ring test failed (%d). navi14navi10raven2vega10arcturusrenoirpicassonavi12vega12raven,all;amdgpu/%s_gpu_info.bindisabled ip block: %d <%s> amdgpu_atombios_init failed hw_init %d failed %d (%d) create WB bo failed allocate CSA failed %d 6[drm] IP block:%s is hung! gart size (%d) too small gtt size (%d) too small Problem resizing BAR0 (%d).amdgpu/fiji_smc.bin&adev->firmware.mutex&adev->pm.mutex&adev->gfx.gpu_clock_mutex&adev->srbm_mutex&adev->gfx.pipe_reserve_mutex&adev->gfx.gfx_off_mutex&adev->grbm_idx_mutex&adev->mn_lock&adev->virt.vf_errors.lock&adev->lock_reset&adev->virt.dpm_mutex&adev->psp.mutex&adev->shadow_list_lock6[drm] MCBP is enabled amdgpu_discovery_init failed asic reset on init failed no vBIOS found 6[drm] GPU posting now... gpu post error! VF exclusive mode timeout amdgpu_device_ip_init failed amdgpu_pmu_init failed %p reserve failed amdgpu asic reset failed amdgpu asic init failed Failed to pin cursor BO (%d) 6amdgpu: switched on 6amdgpu: switched off failedsucceededGPU reset begin! 6[drm] RE-INIT-early: %s %s 6[drm] RE-INIT-late: %s %s GPU reset(%d) failed GPU reset(%d) succeeded! GPU reset end with ret = %d pcie_replay_countTAHITIPITCAIRNVERDEOLANDHAINANBONAIREKAVERIKABINIHAWAIIMULLINSTOPAZTONGAFIJICARRIZOSTONEYPOLARIS10POLARIS11POLARIS12VEGAMVEGA10VEGA12VEGA20RAVENARCTURUSRENOIRNAVI10NAVI14NAVI12LASTinclude/linux/thread_info.hunknown crtc id %d unallowed offset %#x Invalid request %d XGMIRASVBIOS version: %s Fatal error during GPU init No more PASIDs available!&fpriv->bo_list_lock%p reserve failed Invalid crtc %u Query failed! stat %d amdgpu_firmware_infoAMDGPU_GEM_CREATEAMDGPU_GEM_MMAPAMDGPU_CTXAMDGPU_BO_LISTAMDGPU_CSAMDGPU_INFOAMDGPU_GEM_METADATAAMDGPU_GEM_WAIT_IDLEAMDGPU_GEM_VAAMDGPU_WAIT_CSAMDGPU_GEM_OPAMDGPU_GEM_USERPTRAMDGPU_WAIT_FENCESAMDGPU_VMAMDGPU_FENCE_TO_HANDLEAMDGPU_SCHEDamdgpu%s 0x%xUnsupported IGP table: %d %d Unknown table version %d, %d unknown voltage object table old table version %d, %d vbios_versionUnknown table version %d %d Adding native panel mode %s load_detect %x returned: %x 6Unknown IIO opcode 6unimplemented! ATOM BIOS beeped! 7 PROCESSDS output: 0x%02X DEBUG output: 0x%02X block: %d base: 0x%04X POST card output: 0x%02X 7REG[0x%04X]6Bad IO mode 7PS[0x%02X,0x%04X]7WS[0x%02X]7ID[0x%04X+%04X]7ID[0x%04X]7FB[0x%02X]7IMM 0x%08X 7IMM 0x%04X 7IMM 0x%02X 7PLL[0x%02X]7MC[0x%02X]7.[31:0] -> 0x%08X 7.[15:0] -> 0x%04X 7.[23:8] -> 0x%04X 7.[31:16] -> 0x%04X 7.[7:0] -> 0x%02X 7.[15:8] -> 0x%02X 7.[23:16] -> 0x%02X 7.[31:24] -> 0x%02X src1: src2: EQNE result: %s switch: case: target: %04X 6Bad case GTLE result: %s %s fb_base: 7PS[0x%02X]7.[31:0] <- 0x%08X 7.[15:0] <- 0x%04X 7.[23:8] <- 0x%04X 7.[31:16] <- 0x%04X 7.[7:0] <- 0x%02X 7.[15:8] <- 0x%02X 7.[23:16] <- 0x%02X 7.[31:24] <- 0x%02X dst: shift: %d src: count: %d target: 0x%04X no taken: %s yes mask: 0x%08x port: %d (%s) port: %d %s @ 0x%04X [%d] @ 0x%04X << table: %d (%s) table: %d 6Invalid BIOS magic 7612955206Invalid ATI magic ATOM6Invalid ATOM magic 6ATOM BIOS: %s MMPLLMCPCIEPCIE PORTASIC_InitGetDisplaySurfaceSizeASIC_RegistersInitVRAM_BlockVenderDetectionSetClocksRatioMemoryControllerInitGPIO_PinInitMemoryParamAdjustDVOEncoderControlGPIOPinControlSetEngineClockSetMemoryClockSetPixelClockDynamicClockGatingResetMemoryDLLResetMemoryDeviceMemoryPLLInitEnableMemorySelfRefreshAdjustMemoryControllerEnableASIC_StaticPwrMgtASIC_StaticPwrMgtStatusChangeDAC_LoadDetectionTMDS2EncoderControlLCD1OutputControlDAC1EncoderControlDAC2EncoderControlDVOOutputControlCV1OutputControlSetCRTC_DPM_StateTVEncoderControlTMDS1EncoderControlLVDSEncoderControlTV1OutputControlEnableScalerBlankCRTCEnableCRTCGetPixelClockEnableVGA_RenderEnableVGA_AccessSetCRTC_TimingSetCRTC_OverScanSetCRTC_ReplicationSelectCRTC_SourceEnableGraphSurfacesLUT_AutoFillEnableHW_IconCursorGetMemoryClockGetEngineClockSetCRTC_UsingDTDTimingTVBootUpStdPinDetectionDFP2OutputControlVRAM_BlockDetectionByStrapMemoryCleanUpReadEDIDFromHWAssistedI2CWriteOneByteToHWAssistedI2CReadHWAssistedI2CStatusSpeedFanControlPowerConnectorDetectionMC_SynchronizationComputeMemoryEnginePLLMemoryRefreshConversionVRAM_GetCurrentInfoBlockDynamicMemorySettingsMemoryTrainingEnableLVDS_SSDFP1OutputControlSetVoltageCRT1OutputControlCRT2OutputControlSetupHWAssistedI2CStatusClockSourceMemoryDeviceInitEnableYUVRESERVEDMOVE_REGMOVE_PSMOVE_WSMOVE_FBMOVE_PLLMOVE_MCAND_REGAND_PSAND_WSAND_FBAND_PLLAND_MCOR_REGOR_PSOR_WSOR_FBOR_PLLOR_MCSHIFT_LEFT_REGSHIFT_LEFT_PSSHIFT_LEFT_WSSHIFT_LEFT_FBSHIFT_LEFT_PLLSHIFT_LEFT_MCSHIFT_RIGHT_REGSHIFT_RIGHT_PSSHIFT_RIGHT_WSSHIFT_RIGHT_FBSHIFT_RIGHT_PLLSHIFT_RIGHT_MCMUL_REGMUL_PSMUL_WSMUL_FBMUL_PLLMUL_MCDIV_REGDIV_PSDIV_WSDIV_FBDIV_PLLDIV_MCADD_REGADD_PSADD_WSADD_FBADD_PLLADD_MCSUB_REGSUB_PSSUB_WSSUB_FBSUB_PLLSUB_MCSET_ATI_PORTSET_PCI_PORTSET_SYS_IO_PORTSET_REG_BLOCKSET_FB_BASECOMPARE_REGCOMPARE_PSCOMPARE_WSCOMPARE_FBCOMPARE_PLLCOMPARE_MCSWITCHJUMPJUMP_EQUALJUMP_BELOWJUMP_ABOVEJUMP_BELOW_OR_EQUALJUMP_ABOVE_OR_EQUALJUMP_NOT_EQUALTEST_REGTEST_PSTEST_WSTEST_FBTEST_PLLTEST_MCDELAY_MILLISECDELAY_MICROSECCALL_TABLEREPEATCLEAR_REGCLEAR_PSCLEAR_WSCLEAR_FBCLEAR_PLLCLEAR_MCNOPEOTMASK_REGMASK_PSMASK_WSMASK_FBMASK_PLLMASK_MCPOST_CARDBEEPSAVE_REGRESTORE_REGSET_DATA_BLOCKXOR_REGXOR_PSXOR_WSXOR_FBXOR_PLLXOR_MCSHL_REGSHL_PSSHL_WSSHL_FBSHL_PLLSHL_MCSHR_REGSHR_PSSHR_WSSHR_FBSHR_PLLSHR_MCDEBUGCTB_DSamdgpugpu recover amdgpu_fence--- ring %d (%s) --- amdgpu_fence_infoamdgpu_gpu_recoverUnsupported memory type %u Missing get_user_page_done Failed to get hmm_mirror No user pages to check include/linux/dma-mapping.hfailed to pin userptr &adev->mman.gtt_window_lockFailed initializing oa heap. amdgpu_vramamdgpu_iomemFailed to init debugfs sync failed (%d). Error scheduling IBs (%d) amdgpu_vram_mmamdgpu_gtt_mmamdgpu_gds_mmamdgpu_gws_mmamdgpu_oa_mmttm_page_poolttm_dma_page_pool%p unpin not necessary %p validate failed for unpin %p reserve failed 6[drm] RAM width %dbits %s %p pin failed (%d) kernel bo pin failed %p bind failed (%d) kernel bo map failed UNKNOWNGDDR1DDR2GDDR3GDDR4GDDR5HBMDDR3DDR4GDDR6%p reserve failed %p reserve failed 6[drm] Connector %d: 6[drm] %s 6[drm] Encoders: 6[drm] CRT1: %s 6[drm] CRT2: %s 6[drm] LCD1: %s 6[drm] DFP1: %s 6[drm] DFP2: %s 6[drm] DFP3: %s 6[drm] DFP4: %s 6[drm] DFP5: %s 6[drm] DFP6: %s 6[drm] TV1: %s 6[drm] CV: %s coherentload detectionunderscanunderscan hborderunderscan vborderaudioditherabm level%p bind failed offonautoHPD1HPD2HPD3HPD4HPD5HPD6NONEINTERNAL_LVDSINTERNAL_TMDS1INTERNAL_TMDS2INTERNAL_DAC1INTERNAL_DAC2INTERNAL_SDVOAINTERNAL_SDVOBSI170BCH7303CH7301INTERNAL_DVO1EXTERNAL_SDVOAEXTERNAL_SDVOBTITFP513INTERNAL_LVTM1VT1623HDMI_SI1930HDMI_INTERNALINTERNAL_KLDSCP_TMDS1INTERNAL_KLDSCP_DVO1INTERNAL_KLDSCP_DAC1INTERNAL_KLDSCP_DAC2SI178MVPU_FPGAINTERNAL_DDIVT1625HDMI_SI1932DP_AN9801DP_DP501INTERNAL_UNIPHYINTERNAL_KLDSCP_LVTMAINTERNAL_UNIPHY1INTERNAL_UNIPHY2NUTMEGTRAVISINTERNAL_VCEINTERNAL_UNIPHY3HDMI_ANX9805INTERNAL_AMCLKVIRTUALval = 0x%02x &i2c->mutexAMDGPU i2c hw bus %sAMDGPU i2c bit bus %s%p reserve failed %p bind failed 6[drm] fb mappable at 0x%lX 6[drm] vram apper at 0x%lX 6[drm] size %lu 6[drm] fb depth is %d 6[drm] pitch is %d CPU GTTVRAM 0x%08x: %12ld byte %s pin count %d imported from %p exported as %p CPU_ACCESS_REQUIRED NO_CPU_ACCESS CPU_GTT_USWC VRAM_CLEARED SHADOW VRAM_CONTIGUOUS VM_ALWAYS_VALID EXPLICIT_SYNC pid %8d command %s: And also active allocations! %p reserve failed GDS bo cannot be per-vm-bo %d unsupported operation %d Couldn't update BO_VA (%d) amdgpu_gem_infoamdgpu(%d) ring create failed &ring->priority_mutexamdgpu_ring_%s3ring test on %s succeeded include/linux/thread_info.hcalloc failure IB va_start is invalid Failed to get ib ! ATOMBIOS detected ATRMUnable to allocate bios VFCTACPI VFCT image truncated 761295520Unable to locate a BIOS ROM %p reserve failed dmaUnknown benchmark Failed to create VRAM object %p reserve failed Failed to pin VRAM object Failed to pin GTT object %d %p bind failed Failed to map GTT object %d Failed GTT->VRAM copy %d Failed VRAM->GTT copy %d switching from power state: switching to power state: highautomanualprofile_exitprofile_standardprofile_min_sclkprofile_min_mclkprofile_peaklowunknown%s %016llx %d batterybalancedperformance%u featuremask = 0x%llx %llu %llu %i bootdefaultstates: %d %d %s %i GFX Clocks and Power: %u MHz (MCLK) %u MHz (SCLK) %u MHz (PSTATE_SCLK) %u MHz (PSTATE_MCLK) %u mV (VDDGFX) %u mV (VDDNB) %u.%u W (average GPU) GPU Temperature: %u C GPU Load: %u %% MEM Load: %u %% SMC Feature Mask: 0x%016llx VCN: Disabled VCN: Enabled %u MHz (DCLK) %u MHz (VCLK) UVD: Disabled UVD: Enabled VCE: Disabled VCE: Enabled %u MHz (ECCLK) OnOff %s: %s dpm not enabled PX asic powered off truefalseamdgpuamdgpu_pm_infofreq2_labelfreq2_inputfreq1_labelfreq1_inputpower1_cappower1_cap_minpower1_cap_maxpower1_averagein1_labelin1_inputin0_labelin0_inputfan1_enablefan1_targetfan1_maxfan1_minfan1_inputpwm1_maxpwm1_minpwm1_enablepwm1temp3_labeltemp2_labeltemp1_labeltemp3_emergencytemp3_crit_hysttemp3_crittemp3_inputtemp2_emergencytemp2_crit_hysttemp2_crittemp2_inputtemp1_emergencytemp1_crit_hysttemp1_crittemp1_inputunique_idpp_featurespcie_bwmem_busy_percentgpu_busy_percentpp_od_clk_voltagepp_power_profile_modepp_mclk_odpp_sclk_odpp_dpm_pciepp_dpm_dcefclkpp_dpm_fclkpp_dpm_socclkpp_dpm_mclkpp_dpm_sclkpp_tablepp_force_statepp_cur_statepp_num_statespower_dpm_stateedgejunctionmemMemory Controller Light SleepBus Interface Light SleepHost Data Path Light SleepRom Medium Grain Clock Gatingdp_aux_ch flags not zero dp_aux_ch error DPCD: %*ph Sink OUI: %02hx%02hx%02hx Branch OUI: %02hx%02hx%02hx clock recovery tried 5 times clock recovery failed channel eq failed: 5 tries channel eq failed 0dB3.5dB6dB9.5dB0.4V0.6V0.8V1.2Vdidunsignedreguint32_tvalueihclient_idsrc_idring_idvmidvmid_srctimestampuint64_ttimestamp_srcpasidsrc_dataunsigned[4]bostruct amdgpu_bo *pagesu32typepreferallowvisiblebo_liststruct amdgpu_bo_list *ringdwfencessched_job_idtimeline__data_loc char[]contextunsigned intseqnofencestruct dma_fence *num_ibsvm_hubpd_addru64needs_flushstartlonglastoffsetflagssoffseteoffsetpeaddrcountincrsrclistbo_sizetotal_bototal_sizenew_placementold_placementidctx0x%04lx, 0x%08lx, 0x%08lx pasid=%u list=%p, bo=%p, bo_size=%Ld (null)Unknown table version %d, %d Memory allocation failed amdgpu_bl%dUnsupported action 0x%x Bios 0 scratch %x %08x detect returned false LCD1 connected LCD1 disconnected CRT1 connected CRT1 disconnected CRT2 connected CRT2 disconnected DFP1 connected DFP1 disconnected DFP2 connected DFP2 disconnected DFP3 connected DFP3 disconnected DFP4 connected DFP4 disconnected DFP5 connected DFP5 disconnected DFP6 connected DFP6 disconnected Bad LCD record %d &sa_manager->wqno bo for sa manager > hw_i2c error %p reserve failed the level%d isn't supported. CPUSDMAVM update mode is %s %p reserve failed still active bo inside vm &adev->vm_manager.lock_pstatefailed to get a new IB (%d) VM IB without ID scheduling IB failed (%d). failed to emit fence (%d) ib test on %s succeeded 3amdgpu_sa_infosize_bytes: %u header_size_bytes: %u header_version_major: %u header_version_minor: %u ip_version_major: %u ip_version_minor: %u ucode_version: 0x%08x ucode_size_bytes: %u ucode_array_offset_bytes: %u crc32: 0x%08x 0x%08x MC io_debug_size_bytes: %u SMC ucode_start_addr: %u ppt_offset_bytes: %u ppt_size_bytes: %u GFX ucode_feature_version: %u jt_offset: %u jt_size: %u RLC save_and_restore_offset: %u reg_restore_list_size: %u reg_list_format_start: %u starting_offsets_start: %u reg_list_size_bytes: %u SDMA ucode_change_version: %u digest_size: %u PSP sos_offset_bytes: %u sos_size_bytes: %u toc_header_version: %u toc_offset_bytes: %u toc_size_bytes: %u kdb_header_version: %u kdb_offset_bytes: %u kdb_size_bytes: %u GPU_INFO version_major: %u version_minor: %u Unknown firmware load type fw_versiondmcu_fw_versionvcn_fw_versionsdma2_fw_versionsdma_fw_versionsmc_fw_versionta_xgmi_fw_versionta_ras_fw_versionasd_fw_versionsos_fw_versionmec2_fw_versionmec_fw_versionrlc_srls_fw_versionrlc_srlg_fw_versionrlc_srlc_fw_versionrlc_fw_versionce_fw_versionpfp_fw_versionme_fw_versionmc_fw_versionuvd_fw_versionvce_fw_versioninclude/linux/thread_info.h&ctx->lockunknown HW IP type: %d invalid ip instance: %d invalid ring: %d %d &mgr->lockctx %p is still alive include/linux/dma-fence.hamdgpu_sync%llu mem_info_gtt_usedmem_info_gtt_total%llu mem_info_vis_vram_usedmem_info_vram_usedmem_info_vis_vram_totalmem_info_vram_total3failed to read reg:%x 3failed to write reg:%x Invalid context priority %d (%d) run ib test: ib ring tests failed (%d). ib ring tests passed. %llu amdgpu_preempt_ibamdgpu_vbiosamdgpu_test_ibamdgpu_evict_vramamdgpu_evict_gttamdgpu_regsamdgpu_regs_didtamdgpu_regs_pcieamdgpu_regs_smcamdgpu_gca_configamdgpu_sensorsamdgpu_waveamdgpu_gprinclude/linux/dma-fence.h&id_mgr->locklimiting GART %llu %d xgmi_hive_infoxgmi_hive_id&tmp->hive_lock&tmp->reset_lockSet xgmi pstate %d. XGMI: Failed to get hive id XGMI: Failed to get node id node%damdgpuxgmi_errorxgmi_device_idfeature mask: 0x%x disable %32senable %32s %8sinject %32s %8s%*s %*s %*s %u %llu %lluFRP0x%08x : 0x%08x : %1s enabledisableceue%s: %lu %s: %lu include/linux/thread_info.hras&con->recovery_lockfeaturesgpu_vram_bad_pagesras_ctrlFeature mask is not clearedumcsdmagfxmmhubathubpcie_bifhdpxgmi_wafldfsmnsemmp0mp1fusenoneparitysingle_correctablemulti_uncorrectablepoisonip discovery uninitialized number of dies: %d %s(%d) #%d v%d.%d.%d: 0x%08x MP1MP2THMSMUIOFUSECLKAPWRGCUVDAUDIO_AZACPDCIDCOXDMADCEAZSDPMUXNTBIOHCL2IMUVCEMMHUBATHUBDBGU_NBIODFXDBGU0DBGU1OSSSYSHDPSDMA0SDMA1ISPDBGU_IODFCLKBFCHDFX_DAPL1IMU_PCIEL1IMU_NBIFL1IMU_IOAGRL1IMU3L1IMU4L1IMU5L1IMU6L1IMU7L1IMU8L1IMU9L1IMU10L1IMU11L1IMU12L1IMU13L1IMU14L1IMU15WAFLCFCH_USB_PDPCIEPCSDDCLSSTIOAGRNBIFIOAPICSYSTEMHUBNTBCCPUMCSATAUSBCCXSECXGMIXGBEMP0DMUDIODAZ&control->tbl_mutexI2C_Abort() Done.data: 6TIMEOUT ERROR !!!4[drm] I2C busy !amdgpu_df%s_%dDFGPU pci config reset cik_commonSRBM_SOFT_RESET=0x%08X cik_ihdiseninvalid dpm profile %d uvd %sabled vce %sabled uvd vclk: %d dclk: %d kv_update_vce_dpm failed IH: thermal low to high IH: thermal high to low Unsupported IGP table: %d %d kv_populate_uvd_table failed kv_populate_vce_table failed kv_populate_acp_table failed kv_set_dpm_interval failed kv_set_dpm_boot_state failed kv_enable_ulv failed kv_enable_didt failed kv_enable_smc_cac failed kv_dpminvalid pageflip crtc %d x %d y %d c->x %d c->y %d %d EnDisinvalid crtc %d force priority to high Mode too big for LB! invalid encoder_id: 0x%x Unhandled interrupt: %d %d IH: HPD%d IH: D%d vblank IH: D%d vline SRBM_SOFT_RESET=0x%08X Couldn't read SADs: %d invalid hdp %d unable to allocate a PPLL %p reserve failed No FB bound Unsupported screen format %s dce_v8_0IH: CP EOP unknown asic: 0x%x invalid me %d GRBM_SOFT_RESET=0x%08X SRBM_SOFT_RESET=0x%08X amdgpu/%s_pfp.binamdgpu/%s_me.binamdgpu/%s_ce.binamdgpu/%s_mec.binamdgpu/%s_rlc.binamdgpu/%s_mec2.binFailed to load gfx firmware! Failed to init rlc BOs! Failed to init MEC BOs! comp_%d.%d.%d(%d) create MQD bo failed bonairekaverikabinihawaiimullinsgfx_v7_0SRBM_SOFT_RESET=0x%08X IH: SDMA trap amdgpu/%s_sdma.binamdgpu/%s_sdma1.binsdma%dbonairekaverikabinihawaiimullinscik_sdmaIH: UVD TRAP uvd_v4_26[drm] vce is not idle vce%dIH: VCE Unhandled interrupt: %d %d vce_v2_0si_commonSRBM_SOFT_RESET=0x%08X Wait for MC idle timedout ! Failed to load MC firmware! writeread amdgpu/%s_mc.binFailed to load mc firmware! tahitipitcairnverdeolandhainangmc_v6_06[drm] Not implemented amdgpu/%s_pfp.binamdgpu/%s_me.binamdgpu/%s_ce.binamdgpu/%s_rlc.binFailed to load gfx firmware! Failed to init rlc BOs! Too many (%d) compute rings! comp_%d.%d.%dunknown asic: 0x%x (%d) create RLC c bo failed tahitipitcairnverdeolandhainangfx_v6_0SRBM_SOFT_RESET=0x%08X si_ihsdma%dsi_dmainvalid pageflip crtc %d x %d y %d c->x %d c->y %d %d EnDisinvalid crtc %d force priority to high invalid encoder_id: 0x%x Unhandled interrupt: %d %d IH: HPD%d IH: D%d vblank IH: D%d vline invalid hdp %d unable to allocate a PPLL Couldn't read SADs: %d %p reserve failed No FB bound Unsupported screen format %s dce_v6_0si_cps is NULL invalid dpm profile %d uvd vclk: %d dclk: %d DTE is not enabled! IH: thermal low to high IH: thermal high to low si_disable_ulv failed si_enable_smc_cac failed si_halt_smc failed si_upload_sw_state failed si_upload_ulv_state failed si_resume_smc failed si_set_sw_state failed si_upload_firmware failed si_init_smc_table failed olandoland_khainan_khainanpitcairnverdeverde_ktahitipitcairn_kbanks_k_2 amdgpu/%s_smc.binsi_dpmGPU pci config reset vi_common3Doesn't get ack from pf. get ack intr and do nothing. 3failed to receive FLR_CMPL GPU BACO reset GPU mode1 reset GPU mode1 reset failed soc15_commonget ack intr and do nothing. 6DPM request failed6Mailbox is brokenSCLKMCLK6%s DPM request failedGPU mode1 reset GPU mode1 reset failed nv_common%i df_cntr_availeventscake1_ftiinstat_rspalloccake0_ftiinstat_rspalloccake1_ftiinstat_reqalloccake0_ftiinstat_reqalloccake1_pcsout_txmetacake0_pcsout_txmetacake1_pcsout_txdatacake0_pcsout_txdataformatumaskinstanceeventWait for MC idle timedout ! SRBM_SOFT_RESET=0x%08X Failed to load MC firmware! writereadbonairehawaiitopaz amdgpu/%s_mc.binFailed to load mc firmware! gmc_v7_0SRBM_SOFT_RESET=0x%08X Wait for MC idle timedout ! Failed to load MC firmware! writereadpolaris10polaris12polaris11polaris10_kpolaris11_ktongapolaris12_k amdgpu/%s_mc.binFailed to load mc firmware! gmc_v8_0retryno-retry MORE_FAULTS: 0x%lx WALKER_ERROR: 0x%lx PERMISSION_FAULTS: 0x%lx MAPPING_ERROR: 0x%lx RW: 0x%lx no VM inv eng for ring %s 6[drm] ECC is not present. 6[drm] ECC is active. 6[drm] SRAM ECC is active. gmc_v9_0mmhubgfxhub MORE_FAULTS: 0x%lx WALKER_ERROR: 0x%lx PERMISSION_FAULTS: 0x%lx MAPPING_ERROR: 0x%lx RW: 0x%lx gmc_v10_0amdgpu: using MSI. amdgpu: irq initialized. Invalid client_id in IV: %d Invalid src_id in IV: %d GPU irq add domain failed amdgpu-ihamdgpu%s: rptr %d, wptr %d SRBM_SOFT_RESET=0x%08X iceland_ihSRBM_SOFT_RESET=0x%08X tonga_ihSRBM_SOFT_RESET=0x%08X cz_ihvega10_ihnavi10_ihFailed to load psp firmware! Unknown firmware type Failed to start rlc autoload Failed to terminate xgmi ta Failed to terminate ras ta PSP ring stop failed PSP load kdb failed! PSP load sysdrv failed! PSP load sos failed! PSP create ring failed! Failed to load toc PSP tmr init failed! PSP load tmr failed! PSP asd init failed! PSP load asd failed! 6[drm] PSP is resuming... PSP resume failed PSP ring init failed! PSP firmware loading failed pspFail to stop psp ring sos fw version = 0x%x. vega10vega12 amdgpu/%s_sos.binamdgpu/%s_asd.binFail to stop psp ring picassoraven2raven amdgpu/%s_asd.binFail to stop psp ring sos fw version = 0x%x. vega20navi10arcturusnavi14navi12 amdgpu/%s_sos.binUnsupported psp sos firmware amdgpu/%s_asd.binamdgpu/%s_ta.binFail to stop psp ring sos fw version = 0x%x. renoiramdgpu/%s_asd.binnone ui class: %s internal class:c nonec bootc thermalc limited_pwrc restc forcedc 3d_perfc ovrdrvc uvdc 3d_lowc acpic uvd_hd2c uvd_hdc uvd_sdc limited_pwr2c ulvc uvd_mvcc caps:c single_dispc videoc no_dc status:c cc rc bwithoutwithbatterybalancedperformanceNONElm63adm1032adm1030max6649lm64f75375RV6xxRV770adt7473External GPIOEvergreenemc2103SumoNorthern IslandsSouthern Islandslm96163Sea IslandsKaveri/Kabiniinvalid pageflip crtc %d x %d y %d c->x %d c->y %d %d EnDisforce priority to high Mode too big for LB! invalid encoder_id: 0x%x Unhandled interrupt: %d %d invalid hdp %d IH: HPD%d invalid crtc %d IH: D%d vblank IH: D%d vline SRBM_SOFT_RESET=0x%08X Couldn't read SADs: %d unable to allocate a PPLL %p reserve failed No FB bound Unsupported screen format %s dce_v10_0invalid pageflip crtc %d x %d y %d c->x %d c->y %d %d EnDisforce priority to high Mode too big for LB! invalid encoder_id: 0x%x Unhandled interrupt: %d %d invalid hdp %d IH: HPD%d invalid crtc %d IH: D%d vblank IH: D%d vline SRBM_SOFT_RESET=0x%08X Couldn't read SADs: %d unable to allocate a PPLL %p reserve failed No FB bound Unsupported screen format %s dce_v11_0invalid crtc %d Enable software vsync timer Disable software vsync timer invalid pageflip crtc %d dce_virtual%u.%u.%ukiq_%d.%d.%d(%d) failed to init kiq ring %p reserve failed Invalid KCQ enabled: %d Failed to lock KIQ (%d). KCQ enable failed (%d) create RLC sr bo failed CP EDC/ECC error detected.unavailabletruefalseinstruction intrEDC/ECC errorSQ invalid encoding type . amdgpu/%s_pfp_2.binamdgpu/%s_pfp.binamdgpu/%s_me_2.binamdgpu/%s_me.binamdgpu/%s_ce_2.binamdgpu/%s_ce.binamdgpu/%s_rlc.binamdgpu/%s_mec_2.binamdgpu/%s_mec.binamdgpu/%s_mec2_2.binamdgpu/%s_mec2.binIH: CP EOP unknown asic: 0x%x SRBM_SOFT_RESET=0x%08X GRBM_SOFT_RESET=0x%08X invalid me %d Failed to load gfx firmware! Failed to init rlc BOs! Failed to init MEC BOs! comp_%d.%d.%dFailed to init KIQ BOs! Failed to lock KIQ (%d). KCQ disable failed 3cp is busy, skip halt cp 3rlc is busy, skip halt rlc %p reserve failed Invalid KCQ enabled: %d topaztongafijicarrizostoneypolaris10polaris11polaris12vegamgfx_v8_0amdgpuGRBM_SOFT_RESET=0x%08X amdgpu/%s_mec.binamdgpu/%s_mec2.binpicassoamdgpu/%s_rlc_am4.binravenamdgpu/%s_kicker_rlc.binamdgpu/%s_rlc.binCP ECC ERROR IRQ IH: CP EOP KIQ dequeue request failed. invalid pipe %d invalid me %d Buffer size is invalid: %d Failed to lock KIQ (%d). KCQ disable failed arcturusvega20vega10vega12renoirraven2 amdgpu/%s_me.binamdgpu/%s_ce.binFailed to load gfx firmware! Failed to init rlc BOs! gfx_%dcomp_%d.%d.%dFailed to init KIQ BOs! Failed to init MEC BOs! amdgpu/%s_pfp.bin%p reserve failed Invalid KCQ enabled: %d KCQ enable failed gfx_v9_0CPC_SCRATCHCPC_UCODECPF_ROQ_ME1CPF_ROQ_ME2CPF_TAGCPG_DMA_ROQCPG_DMA_TAGCPG_TAGDC_CSINVOCDC_RESTOREDC_STATEGDS_MEMGDS_INPUT_QUEUEGDS_ME0_CS_PIPE_MEMGDS_OA_PHY_PHY_CMD_RAM_MEMGDS_OA_PHY_PHY_DATA_RAM_MEMSPI_SR_MEMTA_FS_DFIFOTA_FS_AFIFOTA_FL_LFIFOTA_FX_LFIFOTA_FS_CFIFOTCA_HOLE_FIFOTCA_REQ_FIFOTCC_CACHE_DATATCC_CACHE_DIRTYTCC_HIGH_RATE_TAGTCC_LOW_RATE_TAGTCC_SRC_FIFOTCC_IN_USE_DECTCC_IN_USE_TRANSFERTCC_LATENCY_FIFOTCC_RETURN_DATATCC_RETURN_CONTROLTCC_UC_ATOMIC_FIFOTCC_WRITE_RETURNTCC_WRITE_CACHE_READTCC_SRC_FIFO_NEXT_RAMTCC_LATENCY_FIFO_NEXT_RAMTCC_CACHE_TAG_PROBE_FIFOTCC_WRRET_TAG_WRITE_RETURNTCC_ATOMIC_RETURN_BUFFERTCI_WRITE_RAMTCP_CACHE_RAMTCP_LFIFO_RAMTCP_CMD_FIFOTCP_VM_FIFOTCP_DB_RAMTCP_UTCL1_LFIFO0TCP_UTCL1_LFIFO1TD_SS_FIFO_LOTD_SS_FIFO_HITD_CS_FIFOSQ_LDS_DSQ_LDS_ISQ_SGPRSQ_VGPR0SQ_VGPR1SQ_VGPR2SQ_VGPR3SQC_DATA_CU0_WRITE_DATA_BUFSQC_DATA_CU0_UTCL1_LFIFOSQC_DATA_CU1_WRITE_DATA_BUFSQC_DATA_CU1_UTCL1_LFIFOSQC_DATA_CU2_WRITE_DATA_BUFSQC_DATA_CU2_UTCL1_LFIFOSQC_INST_BANKA_TAG_RAMSQC_INST_BANKA_BANK_RAMSQC_DATA_BANKA_TAG_RAMSQC_DATA_BANKA_BANK_RAMSQC_INST_BANKA_MISS_FIFOSQC_DATA_BANKA_HIT_FIFOSQC_DATA_BANKA_MISS_FIFOSQC_DATA_BANKA_DIRTY_BIT_RAMSQC_INST_UTCL1_LFIFOSQC_INST_BANKB_TAG_RAMSQC_INST_BANKB_BANK_RAMSQC_DATA_BANKB_TAG_RAMSQC_DATA_BANKB_BANK_RAMSQC_INST_BANKB_MISS_FIFOSQC_DATA_BANKB_HIT_FIFOSQC_DATA_BANKB_MISS_FIFOSQC_DATA_BANKB_DIRTY_BIT_RAMEA_DRAMRD_CMDMEMEA_DRAMWR_CMDMEMEA_DRAMWR_DATAMEMEA_RRET_TAGMEMEA_WRET_TAGMEMEA_DRAMRD_PAGEMEMEA_DRAMWR_PAGEMEMEA_IORD_CMDMEMEA_IOWR_CMDMEMEA_IOWR_DATAMEMGMIRD_CMDMEMGMIWR_CMDMEMGMIWR_DATAMEMGMIRD_PAGEMEMGMIWR_PAGEMEMMAM_D0MEMMAM_D1MEMMAM_D2MEMMAM_D3MEMGFX_CPC_SCRATCHGFX_CPC_UCODEGFX_DC_STATE_ME1GFX_DC_CSINVOC_ME1GFX_DC_RESTORE_ME1GFX_DC_STATE_ME2GFX_DC_CSINVOC_ME2GFX_DC_RESTORE_ME2GFX_CPF_ROQ_ME2GFX_CPF_ROQ_ME1GFX_CPF_TAGGFX_CPG_DMA_ROQGFX_CPG_DMA_TAGGFX_CPG_TAGGFX_GDS_MEMGFX_GDS_INPUT_QUEUEGFX_GDS_OA_PHY_CMD_RAM_MEMGFX_GDS_OA_PHY_DATA_RAM_MEMGFX_GDS_OA_PIPE_MEMGFX_SPI_SR_MEMGFX_SQ_SGPRGFX_SQ_LDS_DGFX_SQ_LDS_IGFX_SQ_VGPRGFX_SQC_INST_UTCL1_LFIFOGFX_SQC_DATA_CU0_UTCL1_LFIFOGFX_SQC_DATA_CU1_UTCL1_LFIFOGFX_SQC_DATA_CU2_UTCL1_LFIFOGFX_SQC_INST_BANKA_TAG_RAMGFX_SQC_INST_BANKA_MISS_FIFOGFX_SQC_INST_BANKA_BANK_RAMGFX_SQC_DATA_BANKA_TAG_RAMGFX_SQC_DATA_BANKA_HIT_FIFOGFX_SQC_DATA_BANKA_MISS_FIFOGFX_SQC_DATA_BANKA_BANK_RAMGFX_SQC_INST_BANKB_TAG_RAMGFX_SQC_INST_BANKB_MISS_FIFOGFX_SQC_INST_BANKB_BANK_RAMGFX_SQC_DATA_BANKB_TAG_RAMGFX_SQC_DATA_BANKB_HIT_FIFOGFX_SQC_DATA_BANKB_MISS_FIFOGFX_SQC_DATA_BANKB_BANK_RAMGFX_TA_FS_DFIFOGFX_TA_FS_AFIFOGFX_TA_FL_LFIFOGFX_TA_FX_LFIFOGFX_TA_FS_CFIFOGFX_TCA_HOLE_FIFOGFX_TCA_REQ_FIFOGFX_TCC_CACHE_DATAGFX_TCC_CACHE_DATA_BANK_0_1GFX_TCC_CACHE_DATA_BANK_1_0GFX_TCC_CACHE_DATA_BANK_1_1GFX_TCC_CACHE_DIRTY_BANK_0GFX_TCC_CACHE_DIRTY_BANK_1GFX_TCC_HIGH_RATE_TAGGFX_TCC_LOW_RATE_TAGGFX_TCC_IN_USE_DECGFX_TCC_IN_USE_TRANSFERGFX_TCC_RETURN_DATAGFX_TCC_RETURN_CONTROLGFX_TCC_UC_ATOMIC_FIFOGFX_TCC_WRITE_RETURNGFX_TCC_WRITE_CACHE_READGFX_TCC_SRC_FIFOGFX_TCC_SRC_FIFO_NEXT_RAMGFX_TCC_CACHE_TAG_PROBE_FIFOGFX_TCC_LATENCY_FIFOGFX_TCC_LATENCY_FIFO_NEXT_RAMGFX_TCC_ATOMIC_RETURN_BUFFERGFX_TCI_WRITE_RAMGFX_TCP_CACHE_RAMGFX_TCP_LFIFO_RAMGFX_TCP_CMD_FIFOGFX_TCP_VM_FIFOGFX_TCP_DB_RAMGFX_TCP_UTCL1_LFIFO0GFX_TCP_UTCL1_LFIFO1GFX_TD_SS_FIFO_LOGFX_TD_SS_FIFO_HIGFX_TD_CS_FIFOGFX_EA_DRAMRD_CMDMEMGFX_EA_DRAMWR_CMDMEMGFX_EA_DRAMWR_DATAMEMGFX_EA_RRET_TAGMEMGFX_EA_WRET_TAGMEMGFX_EA_GMIRD_CMDMEMGFX_EA_GMIWR_CMDMEMGFX_EA_GMIWR_DATAMEMGFX_EA_DRAMRD_PAGEMEMGFX_EA_DRAMWR_PAGEMEMGFX_EA_IORD_CMDMEMGFX_EA_IOWR_CMDMEMGFX_EA_IOWR_DATAMEMGFX_EA_GMIRD_PAGEMEMGFX_EA_GMIWR_PAGEMEMGFX_EA_MAM_D0MEMGFX_EA_MAM_D1MEMGFX_EA_MAM_D2MEMGFX_EA_MAM_D3MEMUTC_VML2_BANK_CACHEUTC_VML2_WALKERUTC_ATCL2_CACHE_2M_BANKUTC_ATCL2_CACHE_4K_BANKunhalthaltfailed to %s cp gfx GRBM_SOFT_RESET=0x%08X KGQ disable failed KCQ disable failed ring %d failed to preempt ib navi12navi14navi10 amdgpu/%s_pfp%s.binamdgpu/%s_me%s.binamdgpu/%s_ce%s.binamdgpu/%s_rlc.binamdgpu/%s_mec%s.binamdgpu/%s_mec2%s.binIH: CP EOP RLC ROM should halt itself invalid pipe %d invalid me %d amdgpu: IB test timed out. Failed to load gfx firmware! Failed to init rlc BOs! gfx_%d.%d.%dcomp_%d.%d.%dFailed to init KIQ BOs! failed to parse rlc toc Failed to init MEC BOs! %p reserve failed Failed to lock KIQ (%d). kfq enable failed (%d) failed to load pfp fw (%d) failed to load ce fw (%d) failed to load me fw gfx_v10_0amdgpuSRBM_SOFT_RESET=0x%08X topazamdgpu/%s_sdma.binamdgpu/%s_sdma1.binsdma%dIH: SDMA trap sdma_v2_4SRBM_SOFT_RESET=0x%08X amdgpu/%s_sdma.binamdgpu/%s_sdma1.binsdma%dIH: SDMA trap tongafijicarrizostoneypolaris10polaris11polaris12vegamsdma_v3_0Setting write pointer truesdma%dpage%dIH: SDMA trap arcturusrenoirraven2vega20picassovega12vega10ravenfalse amdgpu/%s_sdma.binamdgpu/%s_sdma%d.binpsp_load == '%s' sdma_v4_0Setting write pointer truefalse amdgpu/%s_sdma.binamdgpu/%s_sdma1.binpsp_load == '%s' sdma%dIH: SDMA trap amdgpu: IB test timed out navi10navi14navi12sdma_v5_0navi10amdgpu/%s_mes.binfailed to MES fw, r=%d mes_v10_1Invalid reg 0x%X! Unknown packet type %d ! invalid UVD command %X! Invalid UVD handle! )Handle 0x%x already in use! No more free UVD handles! UVD codec not handled %d! Invalid UVD handle 0x%x! amdgpu/vega12_uvd.binamdgpu/mullins_uvd.binamdgpu/bonaire_uvd.binamdgpu/kaveri_uvd.binamdgpu/stoney_uvd.binamdgpu/carrizo_uvd.binamdgpu/hawaii_uvd.binamdgpu/fiji_uvd.binamdgpu/kabini_uvd.binamdgpu/polaris12_uvd.binamdgpu/vegam_uvd.binamdgpu/polaris11_uvd.binamdgpu/vega20_uvd.binamdgpu/polaris10_uvd.binamdgpu/tonga_uvd.binamdgpu/vega10_uvd.binUVD-IBs need a msg command! Error destroying UVD %d! IH: UVD TRAP uvd_v5_0SRBM_SOFT_RESET=0x%08X 6[drm] UVD ENC is disabled uvd_enc%dIH: UVD TRAP Unhandled interrupt: %d %d uvd_v6_0Unhandled client id: %d IH: UVD TRAP Unhandled interrupt: %d %d uvd_%duvd_enc_%d.%duvd_v7_0No more free VCE handles! amdgpu/vega12_vce.binamdgpu/bonaire_vce.binamdgpu/mullins_vce.binamdgpu/kaveri_vce.binamdgpu/stoney_vce.binamdgpu/carrizo_vce.binamdgpu/fiji_vce.binamdgpu/hawaii_vce.binamdgpu/kabini_vce.binamdgpu/polaris12_vce.binamdgpu/vegam_vce.binamdgpu/polaris11_vce.binamdgpu/tonga_vce.binamdgpu/vega20_vce.binamdgpu/polaris10_vce.binamdgpu/vega10_vce.bin&adev->vce.idle_mutex%p reserve failed (%d) VCE map failed Handle already in use! invalid VCE command (0x%x)! SRBM_SOFT_RESET=0x%08X vce%dIH: VCE Unhandled interrupt: %d %d vce_v3_0vce%dIH: VCE Unhandled interrupt: %d %d vce_v4_0amdgpu/navi14_vcn.binamdgpu/navi12_vcn.binamdgpu/raven2_vcn.binamdgpu/renoir_vcn.binamdgpu/navi10_vcn.binamdgpu/arcturus_vcn.binamdgpu/raven_vcn.binamdgpu/picasso_vcn.binmmUVD_STATUSmmUVD_POWER_STATUSmmUVD_RB_RPTRmmUVD_RB_RPTR2mmUVD_JRBC_RB_RPTRmmUVD_RBC_RB_RPTRvcn_enc%dmmUVD_DPG_PAUSEIH: VCN TRAP Unhandled interrupt: %d %d mmUVD_PGFSM_STATUSmmUVD_LMI_STATUSDPG ModeSPG Modevcn_v1_0mmUVD_STATUSDPG ModeSPG ModemmUVD_POWER_STATUSmmUVD_RB_RPTRmmUVD_RB_RPTR2mmUVD_JRBC_RB_RPTRmmUVD_RBC_RB_RPTRmmUVD_PGFSM_STATUSvcn_enc%dmmUVD_DPG_PAUSEIH: VCN TRAP Unhandled interrupt: %d %d mmUVD_LMI_STATUSvcn_v2_0mmUVD_STATUSmmUVD_LMI_STATUSmmUVD_CGC_GATEvcn_dec_%dvcn_jpeg_%dvcn_enc_%d.%dUnhandled client id: %d IH: VCN TRAP Unhandled interrupt: %d %d vcn_v2_5%p reserve failed %p bind failed amdgpu&kfd->gtt_sa_lockkgd2kfd_probe failed &kfd->doorbell_mutexCould not allocate %d gws Could not allocate %d bytes Allocated %d bytes on gart Error initializing iommuv2 added device %x:%x Ring entry too small Found = %d gpu_addr = %p, cpu_addr = %p Single bit 3HWS is not enabledamdgpunavi10arcturusvega20vega12vega10vegampolaris12polaris11polaris10fijitongahawaiiravencarrizokaveri3Can't access read pointer 3Can't access write pointer Can't access eop bufferQueue Percentage: %d, %d Queue Priority: %d, %d Queue Size: 0x%llX, %u Queue r/w Pointers: %px, %px Queue Format: %d Queue EOP: 0x%llX Queue CTX save area: 0x%llX get apertures for PASID %dnode id %u gpu id %u lds_base %llX lds_limit %llX gpuvm_base %llX gpuvm_limit %llX scratch_base %llX scratch_limit %llX debugger already registered 3Event page is already set 3Failed to set event page include/linux/thread_info.hCreating queue ioctl Looking for gpu id 0x%x Could not find gpu id 0x%x no process no function ret = %d CU mask cannot be 0Device IDs array empty n_success exceeds n_devices 3Failed to map to gpu %d/%d amdgpuAMDKFD_IOC_GET_VERSIONAMDKFD_IOC_CREATE_QUEUEAMDKFD_IOC_DESTROY_QUEUEAMDKFD_IOC_SET_MEMORY_POLICYAMDKFD_IOC_GET_CLOCK_COUNTERSAMDKFD_IOC_UPDATE_QUEUEAMDKFD_IOC_CREATE_EVENTAMDKFD_IOC_DESTROY_EVENTAMDKFD_IOC_SET_EVENTAMDKFD_IOC_RESET_EVENTAMDKFD_IOC_WAIT_EVENTSAMDKFD_IOC_DBG_REGISTERAMDKFD_IOC_DBG_UNREGISTERAMDKFD_IOC_DBG_ADDRESS_WATCHAMDKFD_IOC_DBG_WAVE_CONTROLAMDKFD_IOC_GET_TILE_CONFIGAMDKFD_IOC_SET_TRAP_HANDLERAMDKFD_IOC_ACQUIRE_VMAMDKFD_IOC_FREE_MEMORY_OF_GPUAMDKFD_IOC_MAP_MEMORY_TO_GPUAMDKFD_IOC_SET_CU_MASKAMDKFD_IOC_GET_DMABUF_INFOAMDKFD_IOC_IMPORT_DMABUF6Topology: Add CPU node %s%u type%s%s %u version_majorversion_minornode_fromnode_toweightmin_latencymax_latencymin_bandwidthmax_bandwidthrecommended_transfer_sizeflagsheap_typesize_in_bytes%s%s %llu widthmem_clk_maxprocessor_id_lowlevelsizecache_line_sizecache_lines_per_tagassociationlatency%ssibling_map ,%s%d%splatform_oemplatform_idplatform_revcpu_cores_countsimd_countmem_banks_countcaches_countio_links_countcpu_core_id_basesimd_id_basemax_waves_per_simdlds_size_in_kbgds_size_in_kbnum_gwswave_front_sizearray_countsimd_arrays_per_enginecu_per_simd_arraysimd_per_cumax_slots_scratch_cuvendor_iddevice_idlocation_iddrm_render_minorhive_idnum_sdma_enginesnum_sdma_xgmi_enginesmax_engine_clk_fcomputelocal_mem_sizefw_versioncapabilitysdma_fw_versionmax_engine_clk_ccomputegpu_idname%s%s %dmem_bankscachesio_linksperfpropertiesiommutopologynodesgeneration_idsystem_properties&topology_lockUnexpected ASIC family %uNode %u, gpu_id %x: amdgpumax_concurrentnum_counterscounter_idsDoorbell initialization: Unaligned 64-bit doorbellamdgpuUnexpected ASIC family %unode id %u gpu id %u lds_base %llX lds_limit %llX gpuvm_base %llX gpuvm_limit %llX scratch_base %llX scratch_limit %llX amdgpupasid%d 3Invalid attributeMap GTT BO to kernel failed include/linux/srcu.hprockfd_process_wqkfd_restore_wqProcess already found &process->mutex%d3Failed to restore queues Eviction fence mismatch Started evicting pasid %d Finished evicting pasid %d Started restoring pasid %d Finished restoring pasid %d Process %d PASID %d: amdgpuPrinting queue properties: Queue Type: %u Queue Size: %llu Queue percent: %u Queue Address: 0x%llX Queue Id: %u Queue Process Vmid: %u Queue Read Pointer: 0x%px Queue Write Pointer: 0x%px Queue Doorbell Pointer: 0x%p Queue Doorbell Offset: %u Printing queue: Queue MQD Address: 0x%p Queue MQD Gart: 0x%llX Queue Process Address: 0x%p Queue Device Address: 0x%p amdgpu amdgpu cp_hqd_pq_control 0x%x amdgpu include/linux/thread_info.hcp_hqd_pq_control 0x%x amdgpu include/linux/thread_info.hcp_hqd_pq_control 0x%x %s@%i amdgpurptr: %d wptr: %d queue_address 0x%p Assigning hiq to hqd Unexpected ASIC family %uamdgpuqueue type %dfilter %dqueue type %dfilter %dqueue type %d filter %d Unexpected ASIC family %u&pm->lockOver subscribed runlist runlist ib size %d Runlist IB overflow0x%2X runlist IB address: 0x%llX No active runlist amdgpuPQM After init queueThe new slot id %lu Invalid queue type %dPQM After DQM create queue PQM done creating queue SDMA queue on device %x Compute queue on device %x DIQ on device %x amdgpuSDMA engine id: %d SDMA queue id: %d num of pipes: %d &dqm->lock_hidden %s %08x: %08x %08x3Failed to flush TC No doorbells available%s sent runlist 3failed to execute runlist emptynot emptyqpd->queues_list is %s Updated PD address to 0x%llx 6Evicting PASID %u queues 6Restoring PASID %u queues vmid allocation %d hqd slot - pipe %d, queue %d Allocating fence memory 3unmap queue failed 3destroy mqd failed Loading device queue manager Unexpected ASIC family %uNo hiq sdma mqd trunk to free CP Pipe %d, Queue %d SDMA Engine %d, RLC %d amdgpuamdgpuamdgpush_mem_bases 0x%X amdgpush_mem_bases 0x%X amdgpuRing entry too small Failed to allocate IH fifo KFD IHEvent found: id %X type %d&p->event_mutex&ev->wqMapping signal page include/linux/srcu.hamdgpuamdgpuset reg mask : %20s %08x set reg add high :set reg add low : %30s register index :vmid is :Address Low is :Address high is :Control Mask is :Control Mode is :Control Vmid is :Control atc is :3Failed to create DIQ 3Error getting DIQ %30s mode is: %u operand is: %u trap id is: %u msg value is: %u vmid is: %u chk_vmid is : %u command is : %u queue id is : %u simd id is : %u mode is : %u vm_id is : %u wave_id is : %u ibw is : %u ii is : %u sebw is : %u se_ind is : %u sh_ind is : %u sbw is : %u Add ptr is : %20s %p Add is : %20s %08llx 3Failed to submit IB to DIQ vmid is: N/A amdgpuamdgpuCU CPU: cores=%d id_base=%d CU GPU: id_base=%d 4Unknown subtype %d in CRAT DSDTAdded [%d] GPU cache entries CRAT6CRAT table not found 3CRAT table error: %s amdgpuerror setting pasid limit include/linux/srcu.hamdgpu3Invalid input for gpu id. 3Cannot find device %d. echo gpu_id > hang_hws kfdmqdshqdsrlshang_hwsamdgpu_amdkfd_fenceCalled with userptr BO&info->lock%p reserve failed Duplicates should be empty&(*mem)->lockkfd2kgd: Validate failed amdgpu DEC mapping count %d INC mapping count %d Validate failed Release VA 0x%llx - 0x%llx Insufficient system memory Releasing process vm %p Destroying process vm %p CPUGTTVRAMGDSGWSOA3non kfd vmid %d sdma base address: 0x%x HW is processing IQ IQ timer is active Dequeue request is pending amdgpu3kfd2kgd: non kfd vmid %d amdgpusdma base address: 0x%x amdgpusdma base address: 0x%x 3kfd2kgd: non kfd vmid %d kfd2kgd: ATHUB, reg %x kfd2kgd: sdma base addr %x amdgpusdma base addr %x Load hqd of pipe %d queue %d sdma base address: 0x%x ATHUB, reg %x 3non kfd vmid sdma base address: 0x%x HW is processing IQ IQ timer is active Dequeue request is pending amdgpuFirmware type not supported amdgpu/polaris11_k2_smc.binamdgpu/polaris10_k2_smc.binSMC firmware not supported Failed to request firmware Failed to load firmware "%s"Error adding fence (%d) Error getting VM ID (%d) include/linux/dma-fence.h6[drm] Skip scheduling IBs! Error scheduling IBs (%d) Failed to reset ACP ACP_AUDIOacp2x_dmaacp2x_dw_i2s_playacp2x_dw_i2s_capacp2x_dw_bt_i2s_play_capacp2x_dma_irqacp_audio_dmadesignware-i2sacp_ipATPXATPX Hybrid Graphics ATCSATIFNo ATIF handle found Found ATIF handle %s ac_adapterpm: AC pm: DC videoSBIOS pending requests: %#x Changing brightness to %d disabledenabledATCS version %u ATIF version %u &amn->lock3Invalid Firmware Type 6smu version %02d.%02d.%02d 3SMU firmware load failed 3Mec Firmware load failed smu8_smu4amdgpu: [powerplay] %s Invalid VramInfo table.tonga_smu4amdgpu: [powerplay] %s SMU Firmware start failed!fiji_smu4amdgpu: [powerplay] %s SMU Firmware start failed!Failed to load SMU ucode.polaris10_smu4amdgpu: [powerplay] %s Invalid VramInfo table.can not get ULV voltage valueiceland_smu4amdgpu: [powerplay] %s Failed to Get Firmware Entry.amdgpumessage %x was not supported Invalid SMU Table ID!4amdgpu: [powerplay] %s Invalid SMU Table version!Invalid SMU Table Length!vega10_smuFailed to send Message %x. Invalid SMU Table ID!4amdgpu: [powerplay] %s Invalid SMU Table version!Invalid SMU Table Length!smu10_smu4amdgpu: [powerplay] %s Invalid VramInfo table.can not get ULV voltage valueci_smuamdgpucan't get the mac of %x Invalid SMU Table ID!4amdgpu: [powerplay] %s Invalid SMU Table version!Invalid SMU Table Length!SMC is not running!vega12_smu4amdgpu: [powerplay] %s SMU Firmware start failed!Failed to load SMU ucode.vegam_smuInvalid SMU Table ID!4amdgpu: [powerplay] %s Invalid SMU Table version!Invalid SMU Table Length!vega20_smuset_platform_caps failed4amdgpu: [powerplay] %s init_dpm2_parameters failedMissing PowerPlay Table!Invalid Input!4amdgpu: [powerplay] %s *%d: %uMhz %s 4amdgpu: [powerplay] %s amdgpu cpu_pstate_disable: %d cpu_cc6_disable: %d New Display Configuration: enabling ALL SMU features. disable Low Memory PState. enable Low Memory PState. Setting Deep Sleep Clock: %d min_core_set_clock not set 4amdgpu: [powerplay] %s Invalid PowerPlay Table!Missing PowerPlay Table!Unsupported PPTable format!State table is not set!check_powerplay_tables failedUnsupported fan table format!init_dpm_2_parameters failedInvalid VramInfo table.4amdgpu: [powerplay] %s Too many voltage entries!amdgpu4amdgpu: [powerplay] %s Too many voltage entries!*%3d %16s: %8d %16d %16d -%3d %16s: %8s %16s %16s %16d %16d %16d %16s %16s %16s 2.5GT/s, x85.0GT/s, x168.0GT/s, x16%d: %uMhz %s %d: %s %s OD_SCLK%s: %d: %10uMHz %10umV OD_MCLKOD_RANGESCLK: %7uMHz %10uMHz MCLK: %7uMHz %10uMHz VDDC: %7umV %11umV Lookup Table empty.4amdgpu: [powerplay] %s Lookup Table is full.Invalid Powerstate Type!Lookup table is emptyFailed to enable AVFS!Failed to disable AVFS!Failed to disable SMC CAC!Failed to disable DIDT!Failed to stop DPM!Failed to disable ULV!Failed to reset to default!Failed to stop smc!Invalid VDDGFX value!No pcie performance levels!Failed to enable ULV!Failed to start DPM!Failed to enable SMC CAC!BOOTUP_DEFAULT3D_FULL_SCREENPOWER_SAVINGVIDEOVRCOMPUTECUSTOMNUMMODE_NAMESCLK_UP_HYSTSCLK_DOWN_HYSTSCLK_ACTIVE_LEVELMCLK_UP_HYSTMCLK_DOWN_HYSTMCLK_ACTIVE_LEVELamdgpu4amdgpu: [powerplay] %s DIDT Config failed.EnableDiDt failed.Failed to enable DPM DIDT.Failed to disable DPM DIDT.Failed to enable CAC in SMC.Failed to disable CAC in SMC.Failed to disable DTE in SMC.Unsupported PPTable format!4amdgpu: [powerplay] %s State table is not set!Invalid PowerPlay Table!Missing PowerPlay Table!check_powerplay_tables failedinit_dpm_2_parameters failed4amdgpu: [powerplay] %s YN%-19s %-22s %s %-19s 0x%016llx %6s *%s %16s %s %s %s %s 8.0GT/s, x162.5GT/s, x15.0GT/s, x16%d: %uMhz %s %d: %s %s OD_SCLK%s: %d: %10uMhz %10umV OD_MCLKOD_RANGESCLK: %7uMHz %10uMHz MCLK: %7uMHz %10uMHz VDDC: %7umV %11umV enableddisabled[PrepareMp1] Failed!Failed to update WMTABLE!Invalid Divider ID!Invalid Powerstate Type!Failed to disable AVFS!Failed to stop DPM!Failed to disable deep sleep!disable ULV Feature Failed!Failed to disable ulv!Voltage Table empty.VDDCR_SOC is not SVID2!Lookup table is emptyFailed to upload PPtable!Failed to trim MVDD Table!Failed to trim VDDCI table.Failed to start DPM!Failed to enable didt config!Enable ULV Feature Failed!Failed to enable ULV!BOOTUP_DEFAULT3D_FULL_SCREENPOWER_SAVINGVIDEOVRCOMPUTECUSTOMNUMMODE_NAMEBUSY_SET_POINTFPSUSE_RLC_BUSYMIN_ACTIVE_LEVELDPM_PREFETCHERGFXCLK_DPMUCLK_DPMSOCCLK_DPMUVD_DPMVCE_DPMULVMP0CLK_DPMLINK_DPMDCEFCLK_DPMAVFSGFXCLK_DSSOCCLK_DSLCLK_DSPPTTDCTHERMALGFX_PER_CU_CGRMDCEFCLK_DSACDCVR0HOTVR1HOTFW_CTFLED_DISPLAYFAN_CONTROLFAST_PPTDIDTACGPCC_LIMITFEATURESBITMASKENABLEMENTamdgpufeatures_to_enable 0x%llx features_to_disable 0x%llx 4amdgpu: [powerplay] %s amdgpu4amdgpu: [powerplay] %s *%s %16s %s %s %s %s 2: %uMhz %s %d: %uMhz %s 0: %uMhz %s 1: %uMhz %s 4amdgpu: [powerplay] %s BOOTUP_DEFAULT3D_FULL_SCREENPOWER_SAVINGVIDEOVRCOMPUTENUMMODE_NAMEBUSY_SET_POINTFPSUSE_RLC_BUSYMIN_ACTIVE_LEVEL4amdgpu: [powerplay] %s Missing PowerPlay Table!Unsupported PPTable format!Invalid PowerPlay Table!check_powerplay_tables failed4amdgpu: [powerplay] %s Failed to set soft max vclk!Failed to set soft max dclk!Failed to set soft max eclk!Failed to set soft min vclk!Failed to set soft min dclk!Failed to set soft min eclk!YN%-19s %-22s %s %-19s 0x%016llx %6s Failed to run ACG BTC!Failed to upload PPtable![PrepareMp1] Failed!*%d: %uMhz %s Failed to update WMTABLE!DPM_PREFETCHERGFXCLK_DPMUCLK_DPMSOCCLK_DPMUVD_DPMVCE_DPMULVMP0CLK_DPMLINK_DPMDCEFCLK_DPMGFXCLK_DSSOCCLK_DSLCLK_DSPPTTDCTHERMALGFX_PER_CU_CGRMDCEFCLK_DSACDCVR0HOTVR1HOTFW_CTFLED_DISPLAYFAN_CONTROLDIDTGFXOFFCGACGFEATURESBITMASKENABLEMENTamdgpufeatures_to_enable 0x%llx features_to_disable 0x%llx 4amdgpu: [powerplay] %s Voltage Table empty.4amdgpu: [powerplay] %s vol_table empty.Failed to trim MVDD table.Failed to trim VDDCI table.Voltage Lookup Table empty.Lookup Table empty.Lookup table is emptyVoltage Lookup Table emptyamdgpu4amdgpu: [powerplay] %s Missing PowerPlay Table!Unsupported PPTable format!Invalid PowerPlay Table!check_powerplay_tables failed4amdgpu: [powerplay] %s Failed to set soft max vclk!Failed to set soft max dclk!Failed to set soft max eclk!Failed to set soft max fclk!Failed to set soft min vclk!Failed to set soft min dclk!Failed to set soft min eclk!Failed to set soft min fclk![PrepareMp1] Failed!YN%-19s %-22s %s %-19s 0x%016llx %6s *x16x8x1x2x4x1216.0GT/s,5.0GT/s,2.5GT/s,8.0GT/s,0: %uMhz * (DPM disabled) %d: %uMhz %s %d: %s %s %dMhz %s OD_SCLK%s: 0: %10uMhz 1: %10uMhz OD_MCLKOD_VDDC_CURVE0: %10uMhz %10dmV 1: %10uMhz %10dmV 2: %10uMhz %10dmV OD_RANGESCLK: %7uMhz %10uMhz MCLK: %7uMhz %10uMhz %2d %14s%s: GFXCLKSOCCLKUCLKFCLKFailed to update WMTABLE!BOOTUP_DEFAULT3D_FULL_SCREENPOWER_SAVINGVIDEOVRCOMPUTECUSTOMPROFILE_INDEX(NAME)CLOCK_TYPE(NAME)FPSUseRlcBusyMinActiveFreqTypeMinActiveFreqBoosterFreqTypeBoosterFreqPD_Data_limit_cPD_Data_error_coeffPD_Data_error_rate_coeffDPM_PREFETCHERGFXCLK_DPMUCLK_DPMSOCCLK_DPMUVD_DPMVCE_DPMULVMP0CLK_DPMLINK_DPMDCEFCLK_DPMGFXCLK_DSSOCCLK_DSLCLK_DSPPTTDCTHERMALGFX_PER_CU_CGRMDCEFCLK_DSACDCVR0HOTVR1HOTFW_CTFLED_DISPLAYFAN_CONTROLGFX_EDCGFXOFFCGFCLK_DPMFCLK_DSMP1CLK_DSMP0CLK_DSXGMIECCFEATURESBITMASKENABLEMENTamdgpufeatures_to_enable 0x%llx features_to_disable 0x%llx 4amdgpu: [powerplay] %s Invalid BACO command. failedsuccessfully&hwmgr->smu_lockamdgpu%s was not implemented. Error in phm_get_clock_info powerplaypowerplay sw init %s &smu->mutex&smu->smu_feature.mutex&smu->smu_baco.mutex&smu->sensor_lock&smu->metrics_lockunknown smu messageunknown smu featureenableddisabled%02d. %-20s (%2d) : %s smuDPM_PREFETCHERDPM_GFXCLKDPM_UCLKDPM_SOCCLKDPM_UVDDPM_VCEULVDPM_MP0CLKDPM_LINKDPM_DCEFCLKDS_GFXCLKDS_SOCCLKDS_LCLKPPTTDCTHERMALGFX_PER_CU_CGRMDS_DCEFCLKACDCVR0HOTVR1HOTFW_CTFLED_DISPLAYFAN_CONTROLGFX_EDCGFXOFFCGDPM_FCLKDS_FCLKDS_MP1CLKDS_MP0CLKXGMIDPM_GFX_PACEMEM_VDDCI_SCALINGMEM_MVDD_SCALINGDS_UCLKGFX_ULVFW_DSTATEBACOVCN_PGJPEG_PGUSB_PGRSMU_SMN_CGAPCC_PLUSGTHRGFX_DCSGFX_SSOUT_OF_BAND_MONITORTEMP_DEPENDENT_VMINMMHUB_PGATHUB_PGWAFL_CGTestMessageGetSmuVersionGetDriverIfVersionSetAllowedFeaturesMaskLowSetAllowedFeaturesMaskHighEnableAllSmuFeaturesDisableAllSmuFeaturesEnableSmuFeaturesLowEnableSmuFeaturesHighDisableSmuFeaturesLowDisableSmuFeaturesHighGetEnabledSmuFeaturesLowGetEnabledSmuFeaturesHighSetWorkloadMaskSetPptLimitSetDriverDramAddrHighSetDriverDramAddrLowSetToolsDramAddrHighSetToolsDramAddrLowTransferTableSmu2DramTransferTableDram2SmuUseDefaultPPTableUseBackupPPTableRunBtcRequestI2CBusReleaseI2CBusSetFloorSocVoltageSoftResetStartBacoMonitorCancelBacoMonitorEnterBacoSetSoftMinByFreqSetSoftMaxByFreqSetHardMinByFreqSetHardMaxByFreqGetMinDpmFreqGetMaxDpmFreqGetDpmFreqByIndexGetDpmClockFreqGetSsVoltageByDpmSetMemoryChannelConfigSetGeminiModeSetGeminiApertureHighSetGeminiApertureLowSetMinLinkDpmByIndexOverridePcieParametersOverDriveSetPercentageSetMinDeepSleepDcefclkReenableAcDcInterruptNotifyPowerSourceSetUclkFastSwitchSetUclkDownHystGfxDeviceDriverResetGetCurrentRpmSetVideoFpsSetTjMaxSetFanTemperatureTargetPrepareMp1ForUnloadDramLogSetDramAddrHighDramLogSetDramAddrLowDramLogSetDramSizeSetFanMaxRpmSetFanMinPwmConfigureGfxDidtNumOfDisplaysRemoveMarginsReadSerialNumTop32ReadSerialNumBottom32SetSystemVirtualDramAddrHighSetSystemVirtualDramAddrLowWaflTestSetFclkGfxClkRatioAllowGfxOffDisallowGfxOffGetPptLimitGetDcModeMaxDpmFreqGetDebugDataSetXgmiModeRunAfllBtcExitBacoPrepareMp1ForResetPrepareMp1ForShutdownSetMGpuFanBoostLimitRpmGetAVFSVoltageByDpmPowerUpVcnPowerDownVcnPowerUpJpegPowerDownJpegBacoAudioD3PMEArmD3RunGfxDcBtcRunSocDcBtcSetMemoryChannelEnableSetDfSwitchTypeGetVoltageByDpmGetVoltageByDpmOverdrivePowerUpVcn0PowerDownVcn0PowerUpVcn1PowerDownVcn1PowerUpGfxPowerDownIspByTilePowerUpIspByTilePowerDownSdmaPowerUpSdmaSetHardMinIspclkByFreqSetHardMinVcnSpare1Spare2SetAllowFclkSwitchSetMinVideoGfxclkFreqActiveProcessNotifySetCustomPolicyQueryPowerLimitSetGfxclkOverdriveByFreqVidSetHardMinDcfclkByFreqSetHardMinSocclkByFreqControlIgpuATSSetMinVideoFclkFreqSetMinDeepSleepDcfclkForcePowerDownGfxSetPhyclkVoltageByFreqSetDppclkVoltageByFreqSetSoftMinVcnEnablePostCodeGetGfxclkFrequencyGetFclkFrequencyGetMinGfxclkFrequencyGetMaxGfxclkFrequencySetGfxCGPGSetSoftMaxGfxClkSetHardMinGfxClkSetSoftMaxSocclkByFreqSetSoftMaxFclkByFreqSetSoftMaxVcnPowerGateMmHubUpdatePmeRestoreGpuChangeStateSetPowerLimitPercentageForceGfxContentSaveEnableTmdp48MHzRefclkPwrDownPowerGateAtHubSetSoftMinJpegSetHardMinFclkByFreqnavi14vega20navi10arcturusnavi12Unsupported ASIC type %d amdgpu/%s_smc.binStartStopminmax *%2d %14s%s: GFXCLKSOCCLKUCLKFCLKx8x2x12x16x1x45.0GT/s,16.0GT/s,8.0GT/s,2.5GT/s,%d: %uMhz %s %d: %s %s %dMhz %s OD_SCLK%s: 0: %10uMhz 1: %10uMhz OD_MCLKOD_VDDC_CURVE0: %10uMhz %10dmV 1: %10uMhz %10dmV 2: %10uMhz %10dmV OD_RANGESCLK: %7uMhz %10uMhz MCLK: %7uMhz %10uMhz highestlowestBOOTUP_DEFAULT3D_FULL_SCREENPOWER_SAVINGVIDEOVRCOMPUTECUSTOMPROFILE_INDEX(NAME)CLOCK_TYPE(NAME)FPSUseRlcBusyMinActiveFreqTypeMinActiveFreqBoosterFreqTypeBoosterFreqPD_Data_limit_cPD_Data_error_coeffPD_Data_error_rate_coeffminmax *%16s %2d %14s%s %d: %uMhz %s highestlowestBOOTUP_DEFAULT3D_FULL_SCREENPOWER_SAVINGVIDEOVRCOMPUTECUSTOMPROFILE_INDEX(NAME) *%2d %14s%s: GFXCLKSOCCLKMEMLK%d: %uMhz %s BOOTUP_DEFAULT3D_FULL_SCREENPOWER_SAVINGVIDEOVRCOMPUTECUSTOMPROFILE_INDEX(NAME)CLOCK_TYPE(NAME)FPSMinFreqTypeMinActiveFreqTypeMinActiveFreqBoosterFreqTypeBoosterFreqPD_Data_limit_cPD_Data_error_coeffPD_Data_error_rate_coeff*2: %uMhz %s %uMhz * 0: %uMhz %s 1: %uMhz %s %d: %uMhz %s reguint32_tvaluereadswritesread_deltawrite_deltafunc__data_loc char[]linereg=0x%08lx, value=0x%08lx DM_MST: Failed to start MST Failed to create sink! Failed to read EDIDUnsupported screen format %s No FB bound fail to reserve bo (%d) %p bind failed DM: Failed to initialize FBC 6[drm] DM: FBC alloc %lu Unsupported ASIC type: 0x%X amdgpu/raven_dmcu.bindm: DMCU firmware not found PSP loading DMCU firmware (null)CRTC is null, returning. crtc:%d, vupdate-vrr:%d aconnector is NULL! No preferred mode found dc_sink is NULL! HDR SB:7Disabling DRM crtc: %d Enabling DRM crtc: %d %p reserve failed Unable to reserve buffer: %d disenWaiting for fences timed out!plane: id=%d dcc_en=%d Bad cursor size %d x %d Notify ELD: %d &aconnector->hpd_lock%s - Connector has no state%s() AMDGPU DM i2c hw bus %dFailed to register hw i2c %d connector_init failed amdgpu_bl%dFailed to add crtc irq id! Failed to add hpd irq id! DM: Failed to initialize IRQ &adev->dm.dc_lock&adev->dm.audio_lock3.2.48KMS initialized. ESI %02x %02x %02x Loop exceeded max iterations dm%s: crtc is NULL at id :%d DM_IRQ: invalid input! DM_IRQ: invalid context: %d! DM_IRQ DM_IRQ: releasing resources. DM_IRQ: suspend DM_IRQ: early resume DM_IRQ: resume :%d dmdc6%pV6%s%sPixelDisplay PHYDPPFDisplayEngineMemoryDCFDCEFSoCInvalid6[drm] DM_PPLIB: %d DM_PPLIB: %d in kHz noneautocrtcdprxcrtc ditherdprx ditherNo dp aux for amd connector dp start crc failed dp stop crc failed include/linux/thread_info.hMin: %u Max: %u Current: %u Maximum: %u %llu 0x%x user data not be read %d %d %d Current: %d 0x%x %d Verified: %d 0x%x %d Reported: %d 0x%x %d Preferred: %d 0x%x %d user data not read link_settingsamdgpu_dm_dtn_logamdgpu_dm_visual_confirmamdgpu_current_backlight_pwmamdgpu_target_backlight_pwmamdgpu_mst_topologyphy_settingstest_patternoutput_bpcvrr_rangesdp_messageaux_dpcd_addressaux_dpcd_sizeaux_dpcd_data%2.2X Invalid slot_layout_info Invalid board_layout_info amdgpuInvalid board_layout_info Invalid slot_layout_info amdgpu%s duration: %lld ticks amdgpu0x0 DFS0x1 REFCLK0x2 ERROR0x3 400 FCH0x4 600 FCHdcfclk,%d,%d,%d,%s dprefclk,%d,N/A,N/A,%s dispclk,%d,N/A,N/A,%s SPLIT reg_name,value,clk_type amdgpuamdgpuunsupported grph pixel format%s Bad requested pixel clock%s: Invalid parameters!! Invalid entry !!! Invalid array pointer!!! Invalid ATOMBIOS SS Table!!! Invalid SS percentage %s: Capability not supportedFailed to get VBLANK! No DSCs available DC: failed to create dwbc20! DC: failed to create dccg! DC: failed to create dmcu! DC: failed to create abm! DC: failed to create dpps! DC:failed to create hw i2c!! DC: failed to create tg! DC: failed to create mpc! DC: failed to create hubbub! DC: failed to create dwbc! DC: failed to blank crtc! Power down front end %d Reset mpcc for pipe %d EnablingDisabling%s inst = %d, Disabled%s inst = %d%s SUPPORTED! inst = %d%s NOT SUPPORTED! inst = %d%s inst = %d, enabled =%d%s inst = %d, scaling%s inst = %d, ENABLEDdisable DSCenable DSC at opp pipe %d%s: Invalid parameters %s: DSC config failed num_slices_h %d num_slices_v %d bits_per_pixel %d (%d.%04d) color_depth %d dsc_version_major %d dsc_version_minor %d bits_per_component %d line_buf_depth %d block_pred_enable %d convert_rgb %d simple_422 %d vbr_enable %d pic_height %d pic_width %d slice_height %d slice_width %d slice_chunk_size %d initial_xmit_delay %d initial_dec_delay %d initial_scale_value %d scale_increment_interval %d scale_decrement_interval %d first_line_bpg_offset %d nfl_bpg_offset %d slice_bpg_offset %d initial_offset %d final_offset %d flatness_min_qp %d flatness_max_qp %d native_420 %d native_422 %d second_line_bpg_offset %d nsl_bpg_offset %d second_line_offset_adj %d rc_model_size %d rc_edge_factor %d rc_quant_incr_limit0 %d rc_quant_incr_limit1 %d rc_tgt_offset_high %d rc_tgt_offset_low %d rc_buf_thresh[%d] %d DC: failed to create dmcu! DC: failed to create abm! DC: failed to create dpp! DC: failed to create tg! DC:failed to create hw i2c!! DC: failed to create mpc! DC: failed to create hubbub! Power gated front end %d Power down front end %d TG counter is not moving! Setting up Waiting for trigger Setting up OTG reset trigger Sync complete [GAMMA]:Gamma Correction TF[GAMMA]:R %d %llu [GAMMA]:G %d %llu [GAMMA]:B %d %llu %11d.%03d =========RQ======== ========DLG======== ========TTU======== WM_Set[%d]:sRGBBypassYccRAMUnknownBypassFixedBypassFloat[%d]: %-9d %-12d %-10d [%-3d]: %-12d %-22d %-22d Reset mpcc for pipe %d amdgpuRAMsRGBYccBypassUnknownBypassFloatBypassFixed%x,%x,%x,%x,%x,%x,%x,%x,%x amdgpuamdgpuUnknown StatusValidation OKScale ratio/tapSource pixel formatViewport sizeDIO supportNot enough DSC UnitsDSC clock requiredUrgent latencyRe-ordering bufferDispclk and DppclkTotal available pipesNumber of OTGWriteback modeWriteback latencyWriteback scale ratio/tapCursor supportPitch supportPTE buffer sizeDSC input bpcPrefetch supportVertical ratio prefetchamdgpu[DML]:DLG: %s: req128_l = %0d[DML]:DLG: %s: req128_c = %0d[DML]:DLG: %s: cstate_en = %d[DML]:DLG: %s: pstate_en = %d[DML]:DLG: %s: vm_en = %d[DML]:DLG: %s: iflip_en = %d[DML]:DLG: %s: lsw = %3.2famdgpuamdgpuamdgpu[DML]:DML: VStartup: %d [DML]:DML: TCalc: %f [DML]:DML: TWait: %f [DML]:DML: LineTime: %f [DML]:DML: Tsetup: %f [DML]:DML: Tdm: %f [DML]:DML: HTotal: %d [DML]: read_bw[%i] = %fBps[DML]: wm_urgent = %fus[DML]: wm_wb_urgent = %fus[DML]: wm_wb_pstate %fusamdgpuamdgpu[DML]:DML: VStartup: %d [DML]:DML: TCalc: %f [DML]:DML: TWait: %f [DML]:DML: LineTime: %f [DML]:DML: Tsetup: %f [DML]:DML: Tdm: %f [DML]:DML: HTotal: %d [DML]: read_bw[%i] = %fBps[DML]: wm_urgent = %fus[DML]: wm_wb_urgent = %fus[DML]: wm_wb_pstate %fusamdgpu[DML]:DML: Trow: %fus amdgpu[DML]:DML: VStartup: %d [DML]:DML: TCalc: %f [DML]:DML: TWait: %f [DML]:DML: LineTime: %f [DML]:DML: Tsetup: %f [DML]:DML: Tdm: %f [DML]:DML: HTotal: %d [DML]:DML: Tvm: %fus [DML]:DML: Tr0: %fus [DML]:DML: Tsw: %fus [DML]:DML: Tpre: %fus [DML]: read_bw[%i] = %fBpsamdgpuamdgpuDC: failed to create dccg! DC: failed to create dpps! DC:failed to create hw i2c!! DC: failed to create tg! DC: failed to create mpc! DC: failed to create hubbub! DC: failed to create dwbc! DC: failed to create dmcu! DC: failed to create abm! DC: skip invalid pipe %d! DC: failed to create tg! [BANDWIDTH_CALCS]:%s: startDC: failed to create dmcu! DC: failed to create abm! DC: failed to create tg! amdgpuFBC status changed to %d%s: wait timed out! OnOff%s: Panel Power action: %s %s: backlight action: %s DC: failed to blank crtc! TG counter is not moving! GSL: enabling trigger-reset GSL: Setting-up... GSL: Set-up complete. amdgpu[BANDWIDTH_CALCS]:%s: startDC: failed to create dmcu! DC: failed to create abm! DC: failed to create tg! amdgpuDC: failed to create dmcu! DC: failed to create abm! DC: failed to create tg! DC: failed to create dmcu! DC: failed to create abm! DC: failed to create tg! DC:failed to create sw i2c!! %s: failed to create dceip %s: failed to create vbios %s: failed to create dcn_soc %s: failed to create dcn_ip %s: failed to create ctx 3.2.48Display Core initialized {%dx%d, %dx%d@%dKhz}%s: %d streams Bad EDID, status%d! Set retimer failedSet default retimer failedSet redriver failedFailed to find device tag! DisconnectedConnectedFailed to create sink! EDID checksum invalid. No EDID read. %s: [Block %d] %sstream_count: %d: %s stream_count: %d: DC: unexpected audio fuse! DC: failed to create audio! amdgpuDC: failed to blank crtc! is_pixel_format_444 %d slice_width %d %s: Link Status changed. Unknown0.5% 30KHzDisabled0.5% 33KHz%sx%d %s VS=%d, PE=%d, DS=%s%s: Read dpcd data failed. Rx Caps: Status: passCR failed lane0CR failed lane1CR failed lane23CR failed in EQEQ failedLQA failedRBRHBRRBR2HBR2HBR3amdgpuDP-DVI passive dongle %dMhz: [IF_TRACE]:Planes %d: [IF_TRACE]: [IF_TRACE]:Update %d amdgpuDC: dc_stream is NULL! DC: attributes is NULL! DC: Cursor address is 0! DC: cursor position is NULL! DC: update_bandwidth failed! link: %d license=GPL and additional rightsdescription=AMD GPUauthor=AMD linux driver teamparmtype=abmlevel:uintparm=abmlevel:ABM level (0 = off (default), 1-4 = backlight reduction level) parmtype=dcfeaturemask:uintparm=dcfeaturemask:all stable DC features enabled (default))parm=queue_preemption_timeout_ms:queue preemption timeout in ms (1 = Minimum, 9000 = default)parmtype=queue_preemption_timeout_ms:intparm=hws_gws_support:MEC FW support gws barriers (false = not supported (Default), true = supported)parmtype=hws_gws_support:boolparm=halt_if_hws_hang:Halt if HWS hang is detected (0 = off (default), 1 = on)parmtype=halt_if_hws_hang:intparm=ignore_crat:Ignore CRAT table during KFD initialization (0 = use CRAT (default), 1 = ignore CRAT)parmtype=ignore_crat:intparm=debug_largebar:Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)parmtype=debug_largebar:intparm=send_sigterm:Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)parmtype=send_sigterm:intparm=max_num_of_queues_per_device:Maximum number of supported queues per device (1 = Minimum, 4096 = default)parmtype=max_num_of_queues_per_device:intparm=cwsr_enable:CWSR enable (0 = Off, 1 = On (Default))parmtype=cwsr_enable:intparm=hws_max_conc_proc:Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))parmtype=hws_max_conc_proc:intparm=sched_policy:Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)parmtype=sched_policy:intparmtype=noretry:intparm=noretry:Disable retry faults (0 = retry enabled (default), 1 = retry disabled)parmtype=mes:intparm=mes:Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)parmtype=discovery:intparm=discovery:Allow driver to discover hardware IPs from IP Discovery table at the top of VRAMparmtype=mcbp:intparm=mcbp:Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)parmtype=async_gfx_ring:intparm=async_gfx_ring:Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))parmtype=smu_memory_pool_size:uintparm=smu_memory_pool_size:reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByteparmtype=cik_support:intparm=cik_support:CIK support (1 = enabled, 0 = disabled (default))parmtype=si_support:intparm=si_support:SI support (1 = enabled, 0 = disabled (default))parmtype=ras_mask:uintparm=ras_mask:Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1parmtype=ras_enable:intparm=ras_enable:Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))parmtype=emu_mode:intparm=emu_mode:Emulation mode, (1 = enable, 0 = disable)parmtype=gpu_recovery:intparm=gpu_recovery:Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)parmtype=compute_multipipe:intparm=compute_multipipe:Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)parmtype=lbpw:intparm=lbpw:Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)parmtype=job_hang_limit:intparm=job_hang_limit:how much time allow a job hang and not drop it (default 0)parmtype=param_buf_per_se:intparm=param_buf_per_se:the size of Off-Chip Parameter Cache per Shader Engine (default depending on gfx)parmtype=cntl_sb_buf_per_se:intparm=cntl_sb_buf_per_se:the size of Control Sideband per Shader Engine (default depending on gfx)parmtype=pos_buf_per_se:intparm=pos_buf_per_se:the size of Position Buffer per Shader Engine (default depending on gfx)parmtype=prim_buf_per_se:intparm=prim_buf_per_se:the size of Primitive Buffer per Shader Engine (default depending on gfx)parmtype=ngg:intparm=ngg:Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))parmtype=virtual_display:charpparm=virtual_display:Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)parmtype=disable_cu:charpparm=disable_cu:Disable CUs (se.sh.cu,...)parmtype=sdma_phase_quantum:uintparm=sdma_phase_quantum:SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))parmtype=pg_mask:uintparm=pg_mask:Powergating flags mask (0 = disable power gating)parmtype=cg_mask:uintparm=cg_mask:Clockgating flags mask (0 = disable clock gating)parmtype=pcie_lane_cap:uintparm=pcie_lane_cap:PCIE Lane Caps (0: autodetect (default))parmtype=pcie_gen_cap:uintparm=pcie_gen_cap:PCIE Gen Caps (0: autodetect (default))parmtype=ppfeaturemask:uintparm=ppfeaturemask:all power features enabled (default))parmtype=sched_hw_submission:intparm=sched_hw_submission:the max number of HW submissions (default 2)parmtype=sched_jobs:intparm=sched_jobs:the max number of jobs supported in the sw queue (default 32)parmtype=dc:intparm=dc:Display Core driver (1 = enable, 0 = disable, -1 = auto (default))parmtype=exp_hw_support:intparm=exp_hw_support:experimental hw support (1 = enable, 0 = disable (default))parmtype=vm_update_mode:intparm=vm_update_mode:VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Bothparmtype=vm_debug:intparm=vm_debug:Debug VM handling (0 = disabled (default), 1 = enabled)parmtype=vm_fault_stop:intparm=vm_fault_stop:Stop on VM fault (0 = never (default), 1 = print first, 2 = always)parmtype=vm_block_size:intparm=vm_block_size:VM page table size in bits (default depending on vm_size)parmtype=vm_fragment_size:intparm=vm_fragment_size:VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)parmtype=vm_size:intparm=vm_size:VM address space size in gigabytes (default 64GB)parmtype=deep_color:intparm=deep_color:Deep Color support (1 = enable, 0 = disable (default))parmtype=bapm:intparm=bapm:BAPM support (1 = enable, 0 = disable, -1 = auto)parmtype=ip_block_mask:uintparm=ip_block_mask:IP Block Mask (all blocks enabled (default))parmtype=runpm:intparm=runpm:PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)parmtype=aspm:intparm=aspm:ASPM support (1 = enable, 0 = disable, -1 = auto)parmtype=fw_load_type:intparm=fw_load_type:firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)parmtype=dpm:intparm=dpm:DPM support (1 = enable, 0 = disable, -1 = auto)parmtype=lockup_timeout:stringparm=lockup_timeout:GPU lockup timeout in ms (default: 10000 for non-compute jobs and infinity timeout for compute jobs. 0: keep default value. negative: infinity timeout), format is [Non-Compute] or [GFX,Compute,SDMA,Video]parmtype=msi:intparm=msi:MSI support (1 = enable, 0 = disable, -1 = auto)parmtype=pcie_gen2:intparm=pcie_gen2:PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)parmtype=hw_i2c:intparm=hw_i2c:hw i2c engine enable (0 = disable)parmtype=disp_priority:intparm=disp_priority:Display Priority (0 = auto, 1 = normal, 2 = high)parmtype=audio:intparm=audio:Audio enable (-1 = auto, 0 = disable, 1 = enable)parmtype=test:intparm=test:Run testsparmtype=benchmark:intparm=benchmark:Run benchmarkparmtype=moverate:intparm=moverate:Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)parmtype=gttsize:intparm=gttsize:Size of the GTT domain in megabytes (-1 = auto)parmtype=gartsize:uintparm=gartsize:Size of GART to setup in megabytes (32, 64, etc., -1=auto)parmtype=vis_vramlimit:intparm=vis_vramlimit:Restrict visible VRAM for testing, in megabytesparmtype=vramlimit:intparm=vramlimit:Restrict VRAM for testing, in megabytesfirmware=amdgpu/navi14_gpu_info.binfirmware=amdgpu/navi10_gpu_info.binfirmware=amdgpu/renoir_gpu_info.binfirmware=amdgpu/raven2_gpu_info.binfirmware=amdgpu/picasso_gpu_info.binfirmware=amdgpu/raven_gpu_info.binfirmware=amdgpu/vega12_gpu_info.binfirmware=amdgpu/vega10_gpu_info.binfirmware=amdgpu/mullins_mec.binfirmware=amdgpu/mullins_rlc.binfirmware=amdgpu/mullins_ce.binfirmware=amdgpu/mullins_me.binfirmware=amdgpu/mullins_pfp.binfirmware=amdgpu/kabini_mec.binfirmware=amdgpu/kabini_rlc.binfirmware=amdgpu/kabini_ce.binfirmware=amdgpu/kabini_me.binfirmware=amdgpu/kabini_pfp.binfirmware=amdgpu/kaveri_mec2.binfirmware=amdgpu/kaveri_mec.binfirmware=amdgpu/kaveri_rlc.binfirmware=amdgpu/kaveri_ce.binfirmware=amdgpu/kaveri_me.binfirmware=amdgpu/kaveri_pfp.binfirmware=amdgpu/hawaii_mec.binfirmware=amdgpu/hawaii_rlc.binfirmware=amdgpu/hawaii_ce.binfirmware=amdgpu/hawaii_me.binfirmware=amdgpu/hawaii_pfp.binfirmware=amdgpu/bonaire_mec.binfirmware=amdgpu/bonaire_rlc.binfirmware=amdgpu/bonaire_ce.binfirmware=amdgpu/bonaire_me.binfirmware=amdgpu/bonaire_pfp.binfirmware=amdgpu/mullins_sdma1.binfirmware=amdgpu/mullins_sdma.binfirmware=amdgpu/kabini_sdma1.binfirmware=amdgpu/kabini_sdma.binfirmware=amdgpu/kaveri_sdma1.binfirmware=amdgpu/kaveri_sdma.binfirmware=amdgpu/hawaii_sdma1.binfirmware=amdgpu/hawaii_sdma.binfirmware=amdgpu/bonaire_sdma1.binfirmware=amdgpu/bonaire_sdma.binfirmware=amdgpu/si58_mc.binfirmware=amdgpu/hainan_mc.binfirmware=amdgpu/oland_mc.binfirmware=amdgpu/verde_mc.binfirmware=amdgpu/pitcairn_mc.binfirmware=amdgpu/tahiti_mc.binfirmware=amdgpu/hainan_rlc.binfirmware=amdgpu/hainan_ce.binfirmware=amdgpu/hainan_me.binfirmware=amdgpu/hainan_pfp.binfirmware=amdgpu/oland_rlc.binfirmware=amdgpu/oland_ce.binfirmware=amdgpu/oland_me.binfirmware=amdgpu/oland_pfp.binfirmware=amdgpu/verde_rlc.binfirmware=amdgpu/verde_ce.binfirmware=amdgpu/verde_me.binfirmware=amdgpu/verde_pfp.binfirmware=amdgpu/pitcairn_rlc.binfirmware=amdgpu/pitcairn_ce.binfirmware=amdgpu/pitcairn_me.binfirmware=amdgpu/pitcairn_pfp.binfirmware=amdgpu/tahiti_rlc.binfirmware=amdgpu/tahiti_ce.binfirmware=amdgpu/tahiti_me.binfirmware=amdgpu/tahiti_pfp.binfirmware=amdgpu/banks_k_2_smc.binfirmware=amdgpu/hainan_k_smc.binfirmware=amdgpu/hainan_smc.binfirmware=amdgpu/oland_k_smc.binfirmware=amdgpu/oland_smc.binfirmware=amdgpu/verde_k_smc.binfirmware=amdgpu/verde_smc.binfirmware=amdgpu/pitcairn_k_smc.binfirmware=amdgpu/pitcairn_smc.binfirmware=amdgpu/tahiti_smc.binfirmware=amdgpu/topaz_mc.binfirmware=amdgpu/hawaii_mc.binfirmware=amdgpu/bonaire_mc.binfirmware=amdgpu/polaris12_k_mc.binfirmware=amdgpu/polaris10_k_mc.binfirmware=amdgpu/polaris11_k_mc.binfirmware=amdgpu/polaris12_mc.binfirmware=amdgpu/polaris10_mc.binfirmware=amdgpu/polaris11_mc.binfirmware=amdgpu/tonga_mc.binfirmware=amdgpu/vega12_asd.binfirmware=amdgpu/vega12_sos.binfirmware=amdgpu/vega10_asd.binfirmware=amdgpu/vega10_sos.binfirmware=amdgpu/raven2_asd.binfirmware=amdgpu/picasso_asd.binfirmware=amdgpu/raven_asd.binfirmware=amdgpu/navi14_asd.binfirmware=amdgpu/navi14_sos.binfirmware=amdgpu/navi10_asd.binfirmware=amdgpu/navi10_sos.binfirmware=amdgpu/vega20_asd.binfirmware=amdgpu/vega20_sos.binfirmware=amdgpu/renoir_asd.binfirmware=amdgpu/vegam_rlc.binfirmware=amdgpu/vegam_mec2.binfirmware=amdgpu/vegam_mec.binfirmware=amdgpu/vegam_me.binfirmware=amdgpu/vegam_pfp.binfirmware=amdgpu/vegam_ce.binfirmware=amdgpu/polaris12_rlc.binfirmware=amdgpu/polaris12_mec2_2.binfirmware=amdgpu/polaris12_mec2.binfirmware=amdgpu/polaris12_mec_2.binfirmware=amdgpu/polaris12_mec.binfirmware=amdgpu/polaris12_me_2.binfirmware=amdgpu/polaris12_me.binfirmware=amdgpu/polaris12_pfp_2.binfirmware=amdgpu/polaris12_pfp.binfirmware=amdgpu/polaris12_ce_2.binfirmware=amdgpu/polaris12_ce.binfirmware=amdgpu/polaris11_rlc.binfirmware=amdgpu/polaris11_mec2_2.binfirmware=amdgpu/polaris11_mec2.binfirmware=amdgpu/polaris11_mec_2.binfirmware=amdgpu/polaris11_mec.binfirmware=amdgpu/polaris11_me_2.binfirmware=amdgpu/polaris11_me.binfirmware=amdgpu/polaris11_pfp_2.binfirmware=amdgpu/polaris11_pfp.binfirmware=amdgpu/polaris11_ce_2.binfirmware=amdgpu/polaris11_ce.binfirmware=amdgpu/polaris10_rlc.binfirmware=amdgpu/polaris10_mec2_2.binfirmware=amdgpu/polaris10_mec2.binfirmware=amdgpu/polaris10_mec_2.binfirmware=amdgpu/polaris10_mec.binfirmware=amdgpu/polaris10_me_2.binfirmware=amdgpu/polaris10_me.binfirmware=amdgpu/polaris10_pfp_2.binfirmware=amdgpu/polaris10_pfp.binfirmware=amdgpu/polaris10_ce_2.binfirmware=amdgpu/polaris10_ce.binfirmware=amdgpu/fiji_rlc.binfirmware=amdgpu/fiji_mec2.binfirmware=amdgpu/fiji_mec.binfirmware=amdgpu/fiji_me.binfirmware=amdgpu/fiji_pfp.binfirmware=amdgpu/fiji_ce.binfirmware=amdgpu/topaz_rlc.binfirmware=amdgpu/topaz_mec.binfirmware=amdgpu/topaz_me.binfirmware=amdgpu/topaz_pfp.binfirmware=amdgpu/topaz_ce.binfirmware=amdgpu/tonga_rlc.binfirmware=amdgpu/tonga_mec2.binfirmware=amdgpu/tonga_mec.binfirmware=amdgpu/tonga_me.binfirmware=amdgpu/tonga_pfp.binfirmware=amdgpu/tonga_ce.binfirmware=amdgpu/stoney_rlc.binfirmware=amdgpu/stoney_mec.binfirmware=amdgpu/stoney_me.binfirmware=amdgpu/stoney_pfp.binfirmware=amdgpu/stoney_ce.binfirmware=amdgpu/carrizo_rlc.binfirmware=amdgpu/carrizo_mec2.binfirmware=amdgpu/carrizo_mec.binfirmware=amdgpu/carrizo_me.binfirmware=amdgpu/carrizo_pfp.binfirmware=amdgpu/carrizo_ce.binfirmware=amdgpu/renoir_rlc.binfirmware=amdgpu/renoir_mec2.binfirmware=amdgpu/renoir_mec.binfirmware=amdgpu/renoir_me.binfirmware=amdgpu/renoir_pfp.binfirmware=amdgpu/renoir_ce.binfirmware=amdgpu/raven_kicker_rlc.binfirmware=amdgpu/raven2_rlc.binfirmware=amdgpu/raven2_mec2.binfirmware=amdgpu/raven2_mec.binfirmware=amdgpu/raven2_me.binfirmware=amdgpu/raven2_pfp.binfirmware=amdgpu/raven2_ce.binfirmware=amdgpu/picasso_rlc_am4.binfirmware=amdgpu/picasso_rlc.binfirmware=amdgpu/picasso_mec2.binfirmware=amdgpu/picasso_mec.binfirmware=amdgpu/picasso_me.binfirmware=amdgpu/picasso_pfp.binfirmware=amdgpu/picasso_ce.binfirmware=amdgpu/raven_rlc.binfirmware=amdgpu/raven_mec2.binfirmware=amdgpu/raven_mec.binfirmware=amdgpu/raven_me.binfirmware=amdgpu/raven_pfp.binfirmware=amdgpu/raven_ce.binfirmware=amdgpu/vega20_rlc.binfirmware=amdgpu/vega20_mec2.binfirmware=amdgpu/vega20_mec.binfirmware=amdgpu/vega20_me.binfirmware=amdgpu/vega20_pfp.binfirmware=amdgpu/vega20_ce.binfirmware=amdgpu/vega12_rlc.binfirmware=amdgpu/vega12_mec2.binfirmware=amdgpu/vega12_mec.binfirmware=amdgpu/vega12_me.binfirmware=amdgpu/vega12_pfp.binfirmware=amdgpu/vega12_ce.binfirmware=amdgpu/vega10_rlc.binfirmware=amdgpu/vega10_mec2.binfirmware=amdgpu/vega10_mec.binfirmware=amdgpu/vega10_me.binfirmware=amdgpu/vega10_pfp.binfirmware=amdgpu/vega10_ce.binfirmware=amdgpu/navi14_rlc.binfirmware=amdgpu/navi14_mec2.binfirmware=amdgpu/navi14_mec.binfirmware=amdgpu/navi14_me.binfirmware=amdgpu/navi14_pfp.binfirmware=amdgpu/navi14_ce.binfirmware=amdgpu/navi14_mec2_wks.binfirmware=amdgpu/navi14_mec_wks.binfirmware=amdgpu/navi14_me_wks.binfirmware=amdgpu/navi14_pfp_wks.binfirmware=amdgpu/navi14_ce_wks.binfirmware=amdgpu/navi10_rlc.binfirmware=amdgpu/navi10_mec2.binfirmware=amdgpu/navi10_mec.binfirmware=amdgpu/navi10_me.binfirmware=amdgpu/navi10_pfp.binfirmware=amdgpu/navi10_ce.binfirmware=amdgpu/topaz_sdma1.binfirmware=amdgpu/topaz_sdma.binfirmware=amdgpu/vegam_sdma1.binfirmware=amdgpu/vegam_sdma.binfirmware=amdgpu/polaris12_sdma1.binfirmware=amdgpu/polaris12_sdma.binfirmware=amdgpu/polaris11_sdma1.binfirmware=amdgpu/polaris11_sdma.binfirmware=amdgpu/polaris10_sdma1.binfirmware=amdgpu/polaris10_sdma.binfirmware=amdgpu/stoney_sdma.binfirmware=amdgpu/fiji_sdma1.binfirmware=amdgpu/fiji_sdma.binfirmware=amdgpu/carrizo_sdma1.binfirmware=amdgpu/carrizo_sdma.binfirmware=amdgpu/tonga_sdma1.binfirmware=amdgpu/tonga_sdma.binfirmware=amdgpu/renoir_sdma.binfirmware=amdgpu/raven2_sdma.binfirmware=amdgpu/picasso_sdma.binfirmware=amdgpu/raven_sdma.binfirmware=amdgpu/vega20_sdma1.binfirmware=amdgpu/vega20_sdma.binfirmware=amdgpu/vega12_sdma1.binfirmware=amdgpu/vega12_sdma.binfirmware=amdgpu/vega10_sdma1.binfirmware=amdgpu/vega10_sdma.binfirmware=amdgpu/navi14_sdma1.binfirmware=amdgpu/navi14_sdma.binfirmware=amdgpu/navi10_sdma1.binfirmware=amdgpu/navi10_sdma.binfirmware=amdgpu/vega20_uvd.binfirmware=amdgpu/vega12_uvd.binfirmware=amdgpu/vega10_uvd.binfirmware=amdgpu/vegam_uvd.binfirmware=amdgpu/polaris12_uvd.binfirmware=amdgpu/polaris11_uvd.binfirmware=amdgpu/polaris10_uvd.binfirmware=amdgpu/stoney_uvd.binfirmware=amdgpu/fiji_uvd.binfirmware=amdgpu/carrizo_uvd.binfirmware=amdgpu/tonga_uvd.binfirmware=amdgpu/mullins_uvd.binfirmware=amdgpu/hawaii_uvd.binfirmware=amdgpu/kaveri_uvd.binfirmware=amdgpu/kabini_uvd.binfirmware=amdgpu/bonaire_uvd.binfirmware=amdgpu/vega20_vce.binfirmware=amdgpu/vega12_vce.binfirmware=amdgpu/vega10_vce.binfirmware=amdgpu/vegam_vce.binfirmware=amdgpu/polaris12_vce.binfirmware=amdgpu/polaris11_vce.binfirmware=amdgpu/polaris10_vce.binfirmware=amdgpu/stoney_vce.binfirmware=amdgpu/fiji_vce.binfirmware=amdgpu/carrizo_vce.binfirmware=amdgpu/tonga_vce.binfirmware=amdgpu/mullins_vce.binfirmware=amdgpu/hawaii_vce.binfirmware=amdgpu/kaveri_vce.binfirmware=amdgpu/kabini_vce.binfirmware=amdgpu/bonaire_vce.binfirmware=amdgpu/navi14_vcn.binfirmware=amdgpu/navi10_vcn.binfirmware=amdgpu/renoir_vcn.binfirmware=amdgpu/raven2_vcn.binfirmware=amdgpu/picasso_vcn.binfirmware=amdgpu/raven_vcn.binfirmware=amdgpu/vega20_smc.binfirmware=amdgpu/vega12_smc.binfirmware=amdgpu/vega10_acg_smc.binfirmware=amdgpu/vega10_smc.binfirmware=amdgpu/vegam_smc.binfirmware=amdgpu/polaris12_k_smc.binfirmware=amdgpu/polaris12_smc.binfirmware=amdgpu/polaris11_k2_smc.binfirmware=amdgpu/polaris11_k_smc.binfirmware=amdgpu/polaris11_smc_sk.binfirmware=amdgpu/polaris11_smc.binfirmware=amdgpu/polaris10_k2_smc.binfirmware=amdgpu/polaris10_k_smc.binfirmware=amdgpu/polaris10_smc_sk.binfirmware=amdgpu/polaris10_smc.binfirmware=amdgpu/fiji_smc.binfirmware=amdgpu/tonga_k_smc.binfirmware=amdgpu/tonga_smc.binfirmware=amdgpu/topaz_k_smc.binfirmware=amdgpu/topaz_smc.binfirmware=amdgpu/hawaii_k_smc.binfirmware=amdgpu/hawaii_smc.binf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bpf_trace_run2Jsdma_fence_signalU,ttm_bo_manager_func!dma_fence_add_callbackJ <__put_task_struct ^ttm_bo_move_memcpy?i2c_bit_add_busB__wake_uptQ^swiotlb_nr_tblk-acpi_evaluate_object>drm_crtc_handle_vblank1flush_delayed_workT=drm_dp_mst_connector_late_registerdrm_atomic_helper_update_planep class_destroyV}drm_fb_helper_setcmapКDmemcmpCEdrm_modeset_lock_all_ctx-cancel_work_sync|generic_handle_irqidrm_is_current_masterJusysfs_create_link΁drm_dp_channel_eq_ok(edrm_dp_mst_reset_vcpi_slots1bkobject_deldrm_dp_mst_topology_mgr_set_mst nAdrm_atomic_private_obj_initk;drm_mode_is_420_also#;(#   $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$"job ring=%s, id=%llu, need pipe sync to fence=%p, context=%llu, seq=%u", __get_str(ring), REC->id, REC->fence, REC->ctx, REC->seqno"bo=%p, from=%d, to=%d, size=%Ld", REC->bo, REC->old_placement, REC->new_placement, REC->bo_size"total_bo_size=%Ld, total_bo_count=%Ld", REC->total_bo, REC->total_size"list=%p, bo=%p, bo_size=%Ld", REC->list, REC->bo, REC->bo_size"pasid=%u", REC->pasid"ring=%s, id=%u, hub=%u, pd_addr=%010Lx", __get_str(ring), REC->vmid, REC->vm_hub,REC->pd_addr"pe=%010Lx, src=%010Lx, count=%u", REC->pe, REC->src, REC->count"pe=%010Lx, addr=%010Lx, incr=%u, flags=%llx, count=%u", REC->pe, REC->addr, REC->incr, REC->flags, REC->count"soffs=%010llx, eoffs=%010llx, flags=%llx", REC->soffset, REC->eoffset, REC->flags"bo=%p, start=%lx, last=%lx, offset=%010llx, flags=%llx", REC->bo, REC->start, REC->last, REC->offset, REC->flags"bo=%p, start=%lx, last=%lx, offset=%010llx, flags=%llx", REC->bo, REC->start, REC->last, REC->offset, REC->flags"pasid=%d, ring=%s, id=%u, hub=%u, pd_addr=%010Lx needs_flush=%u", REC->pasid, __get_str(ring), REC->vmid, REC->vm_hub, REC->pd_addr, REC->needs_flush"sched_job=%llu, timeline=%s, context=%u, seqno=%u, ring_name=%s, num_ibs=%u", REC->sched_job_id, __get_str(timeline), REC->context, REC->seqno, __get_str(ring), REC->num_ibs"sched_job=%llu, timeline=%s, context=%u, seqno=%u, ring_name=%s, num_ibs=%u", REC->sched_job_id, __get_str(timeline), REC->context, REC->seqno, __get_str(ring), REC->num_ibs"bo_list=%p, ring=%u, dw=%u, fences=%u", REC->bo_list, REC->ring, REC->dw, REC->fences"bo=%p, pages=%u, type=%d, preferred=%d, allowed=%d, visible=%d", REC->bo, REC->pages, REC->type, REC->prefer, REC->allow, REC->visible"ih:%u client_id:%u src_id:%u ring:%u vmid:%u timestamp: %llu pasid:%u src_data: %08x %08x %08x %08x", REC->ih, REC->client_id, REC->src_id, REC->ring_id, REC->vmid, REC->timestamp, REC->pasid, REC->src_data[0], REC->src_data[1], REC->src_data[2], REC->src_data[3]"0x%04lx, 0x%08lx, 0x%08lx", (unsigned long)REC->did, (unsigned long)REC->reg, (unsigned long)REC->value"0x%04lx, 0x%08lx, 0x%08lx", (unsigned long)REC->did, (unsigned long)REC->reg, (unsigned long)REC->value$$$$$$$$$$$$$$$$$$$$$$$$$$$$$ )*+"#l .( l >& D&E&F&G&H&I&J&K&L&M&N&O&P&Q&R&S&T&U&V&W&X&Y&Z&[&\&]&^&_&`&a&b&c&=&&Ԡ%%>       @=><()'&$$$$$$$$$$$$$ 0( $$$       dd    2d                                             !"#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNQRSTUVWXYZ]_          "&/ !,3457'680-.129#$%()*+      !# $  "%&'()     $5: ABCD!"78%'2;<=?@)*6(>34+,-.HF.  <;    !"#$%&'()*+,-/0123456789:=>?"%s:%d reads=%08ld (%08ld total), writes=%08ld (%08ld total)", __get_str(func), REC->line, (unsigned long)REC->read_delta, (unsigned long)REC->reads, (unsigned long)REC->write_delta, (unsigned long)REC->writes"reg=0x%08lx, value=0x%08lx", (unsigned long)REC->reg, (unsigned long)REC->value"reg=0x%08lx, value=0x%08lx", (unsigned long)REC->reg, (unsigned long)REC->value  @Z++5@ףp= 7@ףp= 7@ףp= 7@ףp= 7@333333'@+@@@@@(@D@D@D@D@D@D@RQ?I@1@@@P@?@@y@@7@@4@@`e@@@@@@@@j@@@@@@@@n@X@X@X@X@@P@@v@@@@@@@@@0@P@0@z@@@@@@@P@@z@@@@@@@P@@333333!@%@@@@@(@D@D@D@D@D@D@RQ?I@1@@@P@?@@y@@7@@4@@`e@@@@@@@@j@@@@@@@@n@X@X@X@X@@P@@v@@@@@@@@@0@P@0@z@@@@@@@P@@z@@@@@@@P@@T0  ???? 39 @ @?$@? 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g_set_wptrvce_v3_0_ring_get_wptrvce_v3_0_ring_get_rptrvce_v3_0_startvce_v3_0_soft_resetvce_v3_0_hw_initvce_v3_0_hw_init.coldvce_v3_0_resumevce_v3_0_sw_finivce_v3_0_sw_initvce_v3_0_process_interruptvce_v3_0_hw_finivce_v3_0_suspendvce_v3_0_set_powergating_statevce_v3_0_pre_soft_resetvce_v3_0_post_soft_resetvce_v3_0_emit_pipeline_syncvce_v3_0_emit_vm_flushvce_v3_0_ring_emit_ibvce_v3_0_ip_funcsvce_v4_0_set_clockgating_statevce_v4_0_ring_get_wptrvce_v4_0_ring_get_rptrvce_v4_0_stopvce_v4_0_mc_resumevce_v4_0_startvce_v4_0_set_powergating_statevce_v4_0_hw_finivce_v4_0_suspendvce_v4_0_ring_set_wptrvce_v4_0_sw_finivce_v4_0_sw_initvce_v4_0_sw_init.coldvce_v4_0_process_interruptvce_v4_0_set_interrupt_statevce_v4_0_early_initvce_v4_0_ring_vm_funcsvce_v4_0_early_init.coldvce_v4_0_irq_funcsvce_v4_0_ring_insert_endvce_v4_0_emit_wregvce_v4_0_emit_reg_waitvce_v4_0_emit_vm_flushvce_v4_0_ring_emit_ibvce_v4_0_ring_emit_fencevce_v4_0_sriov_startvce_v4_0_hw_initvce_v4_0_hw_init.coldvce_v4_0_resumeamdgpu_vcn_idle_work_handleramdgpu_vcn_dec_send_msgamdgpu_vcn_sw_init.coldvcn_v1_0_set_interrupt_statevcn_v1_0_is_idlevcn_v1_0_dec_ring_get_wptrvcn_v1_0_dec_ring_get_rptrvcn_v1_0_enc_ring_get_wptrvcn_v1_0_enc_ring_get_rptrvcn_v1_0_jpeg_ring_get_wptrvcn_v1_0_jpeg_ring_get_rptrvcn_v1_0_wait_for_idlevcn_v1_0_wait_for_idle.coldvcn_v1_0_stop_dpg_modevcn_v1_0_stop_dpg_mode.coldvcn_v1_0_enable_clock_gatingvcn_v1_0_mc_resume_dpg_modevcn_v1_0_clock_gating_dpg_modevcn_v1_0_disable_clock_gatingvcn_v1_0_mc_resume_spg_modevcn_v1_0_dec_ring_set_wptrvcn_v1_0_enc_ring_set_wptrvcn_v1_0_jpeg_ring_set_wptrvcn_v1_0_sw_finivcn_v1_0_sw_initvcn_v1_0_pause_dpg_modevcn_v1_0_sw_init.coldvcn_v1_0_pause_dpg_mode.coldvcn_v1_0_process_interruptvcn_v1_0_jpeg_ring_patch_wreg.isra.0vcn_v1_0_jpeg_ring_set_patch_ringvcn_v1_0_early_initvcn_v1_0_dec_ring_vm_funcsvcn_v1_0_enc_ring_vm_funcsvcn_v1_0_jpeg_ring_vm_funcsvcn_v1_0_irq_funcsvcn_1_0_enable_static_power_gating.part.0vcn_1_0_enable_static_power_gating.part.0.coldvcn_v1_0_stop_spg_modevcn_v1_0_stop_spg_mode.coldvcn_v1_0_set_clockgating_statevcn_v1_0_start_dpg_modevcn_v1_0_hw_initvcn_v1_0_hw_init.coldvcn_v1_0_resumevcn_v1_0_jpeg_ring_nopvcn_v1_0_dec_ring_insert_nopvcn_v1_0_enc_ring_insert_endvcn_v1_0_enc_ring_emit_wregvcn_v1_0_dec_ring_insert_endvcn_v1_0_enc_ring_emit_reg_waitvcn_v1_0_enc_ring_emit_vm_flushvcn_v1_0_jpeg_ring_insert_endvcn_v1_0_jpeg_ring_insert_startvcn_v1_0_dec_ring_insert_startvcn_v1_0_enc_ring_emit_ibvcn_v1_0_enc_ring_emit_fencevcn_v1_0_dec_ring_emit_wregvcn_v1_0_dec_ring_emit_reg_waitvcn_v1_0_dec_ring_emit_vm_flushvcn_v1_0_dec_ring_emit_ibvcn_v1_0_jpeg_ring_emit_wregvcn_v1_0_dec_ring_emit_fencevcn_v1_0_jpeg_ring_emit_ibvcn_v1_0_jpeg_ring_emit_reg_waitvcn_v1_0_jpeg_ring_emit_vm_flushvcn_v1_0_jpeg_ring_emit_fencevcn_v1_0_start_spg_modevcn_v1_0_start_spg_mode.coldvcn_v1_0_set_powergating_statevcn_v1_0_hw_finivcn_v1_0_suspendvcn_v1_0_ip_funcs.LC28vcn_v2_0_set_interrupt_statevcn_v2_0_is_idlevcn_v2_0_dec_ring_get_wptrvcn_v2_0_dec_ring_get_rptrvcn_v2_0_enc_ring_get_wptrvcn_v2_0_enc_ring_get_rptrvcn_v2_0_jpeg_ring_get_wptrvcn_v2_0_jpeg_ring_get_rptrvcn_v2_0_wait_for_idlevcn_v2_0_wait_for_idle.coldvcn_v2_0_hw_initvcn_v2_0_hw_init.coldvcn_v2_0_stop_dpg_modevcn_v2_0_stop_dpg_mode.coldvcn_v2_0_enable_clock_gatingvcn_v2_0_mc_resume_dpg_modevcn_v2_0_disable_clock_gatingjpeg_v2_0_startjpeg_v2_0_start.coldvcn_v2_0_resumevcn_v2_0_sw_finivcn_v2_0_sw_initvcn_v2_0_pause_dpg_modevcn_v2_0_sw_init.coldvcn_v2_0_pause_dpg_mode.coldvcn_v2_0_dec_ring_set_wptrvcn_v2_0_enc_ring_set_wptrvcn_v2_0_jpeg_ring_set_wptrvcn_v2_0_process_interruptvcn_v2_0_early_initvcn_v2_0_dec_ring_vm_funcsvcn_v2_0_enc_ring_vm_funcsvcn_v2_0_jpeg_ring_vm_funcsvcn_v2_0_irq_funcsvcn_v2_0_enable_static_power_gating.part.0vcn_v2_0_enable_static_power_gating.part.0.coldvcn_v2_0_stopvcn_v2_0_stop.coldvcn_v2_0_set_clockgating_statevcn_v2_0_dec_ring_test_ringvcn_v2_0_start_dpg_modevcn_v2_0_startvcn_v2_0_start.coldvcn_v2_0_set_powergating_statevcn_v2_0_hw_finivcn_v2_0_suspendvcn_v2_0_ip_funcs.LC31vcn_v2_5_set_interrupt_statevcn_v2_5_is_idlevcn_v2_5_dec_ring_get_wptrvcn_v2_5_dec_ring_get_rptrvcn_v2_5_enc_ring_get_wptrvcn_v2_5_enc_ring_get_rptrvcn_v2_5_jpeg_ring_get_wptrvcn_v2_5_jpeg_ring_get_rptrvcn_v2_5_wait_for_idlevcn_v2_5_wait_for_idle.coldvcn_v2_5_hw_initvcn_v2_5_enable_clock_gatingvcn_v2_5_stopvcn_v2_5_stop.coldvcn_v2_5_disable_clock_gatingvcn_v2_5_disable_clock_gating.coldjpeg_v2_5_startvcn_v2_5_startvcn_v2_5_set_powergating_statevcn_v2_5_resumevcn_v2_5_hw_finivcn_v2_5_suspendvcn_v2_5_sw_finivcn_v2_5_sw_initamdgpu_ih_clientid_vcnsvcn_v2_5_sw_init.coldvcn_v2_5_dec_ring_set_wptrvcn_v2_5_enc_ring_set_wptrvcn_v2_5_jpeg_ring_set_wptrvcn_v2_5_process_interruptvcn_v2_5_early_initvcn_v2_5_irq_funcsvcn_v2_5_enc_ring_vm_funcsvcn_v2_5_early_init.coldvcn_v2_5_jpeg_ring_vm_funcsvcn_v2_5_dec_ring_vm_funcsvcn_v2_5_set_clockgating_statevcn_v2_5_ip_funcsamdgpu_amdkfd_device_probe.coldamdgpu_amdkfd_alloc_gtt_mem.coldamdgpu_amdkfd_free_gtt_mem.coldamdgpu_amdkfd_alloc_gws.cold_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ldsmu7_setup_default_pcie_tablesmu7_setup_default_pcie_table.coldsmu7_enable_dpm_taskssmu7_enable_dpm_tasks.coldsmu7_get_sleep_divider_id_from_clock.coldsmu7_hwmgr_funcs__func__.76840__func__.77267__func__.77309smu7_enable_didtPolaris11_DIDTBlock_Infosmu7_program_pt_config_registers.isra.0smu7_program_pt_config_registers.isra.0.coldGCCACConfig_Polaris10DIDTConfig_Polaris10GCCACConfig_Polaris11DIDTConfig_Polaris11_KickerDIDTConfig_Polaris12GCCACConfig_VegaMDIDTConfig_VegaMDIDTConfig_Polaris11smu7_enable_didt_config.coldsmu7_disable_didt_config.coldsmu7_enable_smc_cac.coldsmu7_disable_smc_cac.coldsmu7_enable_power_containment.coldsmu7_disable_power_containment.coldsmu7_fan_ctrl_set_default_mode.part.0smu7_powerup_uvdsmu7_powerup_vcevega10_pp_tables_uninitializecheck_powerplay_tables.isra.0check_powerplay_tables.isra.0.coldget_pix_clk_voltage_dependency_table.isra.0get_pix_clk_voltage_dependency_table.isra.0.coldinit_powerplay_extended_tablesinit_powerplay_extended_tables.coldget_vddc_lookup_table.isra.0get_vddc_lookup_table.isra.0.coldvega10_pp_tables_initialize.coldvega10_get_number_of_powerplay_table_entries.coldvega10_get_powerplay_table_entry.coldvega10_baco_set_cap.coldvega10_get_power_state_sizevega10_patch_boot_statevega10_get_profiling_clk_maskvega10_get_fan_control_modevega10_get_dal_power_levelvega10_get_clock_by_type_with_latencyvega10_get_clock_by_type_with_voltagevega10_check_smc_update_required_for_display_configurationvega10_get_sclk_odvega10_get_mclk_odvega10_display_clock_voltage_request.coldvega10_set_power_profile_modevega10_notify_cac_buffer_infovega10_upload_dpm_bootup_levelvega10_upload_dpm_max_levelvega10_force_clock_levelvega10_force_clock_level.coldvega10_set_ppfeature_status__UNIQUE_ID_ddebug147.74923__UNIQUE_ID_ddebug148.74928vega10_notify_smc_display_config_after_ps_adjustment__UNIQUE_ID_ddebug146.74747vega10_notify_smc_display_config_after_ps_adjustment.coldvega10_get_ppfeature_statusoutput_title.74907ppfeature_name.74906vega10_get_ppfeature_status.coldvega10_get_power_profile_modetitle.75085profile_mode_setting.75083profile_name.75084vega10_get_thermal_temperature_rangeSMU7ThermalWithDelayPolicyvega10_odn_initial_default_settingvega10_print_clock_levelsvega10_read_sensorvega10_set_watermarks_for_clocks_rangesvega10_dpm_force_dpm_levelvega10_dpm_force_dpm_level.coldvega10_populate_single_gfx_levelvega10_populate_single_gfx_level.coldvega10_populate_single_soc_levelvega10_populate_single_soc_level.coldvega10_populate_all_graphic_levelsvega10_populate_vddc_soc_levelsvega10_populate_avfs_parametersvega10_get_pp_table_entryvega10_get_pp_table_entry_callback_funcvega10_hwmgr_backend_finivega10_setup_dpm_led_configvega10_check_dpm_table_updated.isra.0vega10_avfs_enablevega10_avfs_enable.coldvega10_enable_disable_PCC_limit_featurevega10_enable_disable_PCC_limit_feature.coldvega10_set_mp1_statevega10_set_mp1_state.coldvega10_set_fan_control_modevega10_display_configuration_changed_taskvega10_display_configuration_changed_task.coldvega10_populate_single_eclock_levelvega10_populate_single_eclock_level.coldvega10_populate_single_memory_level.isra.0vega10_populate_single_memory_level.isra.0.coldvega10_populate_all_memory_levelsvega10_setup_asic_taskvega10_setup_asic_task.coldvega10_setup_default_dpm_tablesvega10_setup_default_dpm_tables.coldcast_phw_vega10_power_state.part.0vega10_odn_update_power_statevega10_odn_update_power_state.coldvega10_odn_edit_dpm_tablevega10_odn_edit_dpm_table.coldvega10_set_mclk_odvega10_set_mclk_od.coldvega10_set_sclk_odvega10_set_sclk_od.coldvega10_dpm_get_sclkvega10_dpm_get_sclk.coldvega10_dpm_get_mclkvega10_dpm_get_mclk.coldvega10_get_pp_table_entry_callback_func.coldvega10_apply_state_adjust_rulesvega10_apply_state_adjust_rules.coldvega10_disable_dpm_tasksvega10_disable_dpm_tasks.coldvega10_power_off_asicvega10_power_off_asic.coldvega10_trim_voltage_table.isra.0vega10_trim_voltage_table.isra.0.coldvega10_hwmgr_backend_initvega10_hwmgr_backend_init.coldvega10_get_performance_levelvega10_get_performance_level.coldvega10_set_power_state_tasksvega10_set_power_state_tasks.coldvega10_check_states_equalvega10_check_states_equal.coldvega10_init_smc_tablevega10_init_smc_table.coldvega10_enable_dpm_tasksvega10_enable_dpm_tasks.coldcast_phw_vega10_power_state.coldcast_const_phw_vega10_power_state.coldvega10_enable_disable_vce_dpm.coldvega10_power_gate_vcevega10_enable_disable_uvd_dpm.coldvega10_power_gate_uvdvega10_hwmgr_funcs__func__.74748__func__.74924vega10_didt_set_maskvega10_program_gc_didt_config_registers.isra.0vega10_program_didt_config_registers.isra.0vega10_program_didt_config_registers.isra.0.cold__UNIQUE_ID_ddebug130.68670SEDiDtStallCtrlConfig_vega10SEDiDtStallPatternConfig_vega10SEDiDtCtrl3Config_vega10SEDiDtCtrl0Config_Vega10GCDiDtDroopCtrlConfig_vega10AvfsPSMInitConfig_vega10SEDiDtWeightConfig_Vega10SEDiDtCtrl1Config_Vega10SEDiDtCtrl2Config_Vega10SEDiDtTuningCtrlConfig_Vega10SELCacConfig_Vega10SEEDCForceStallPatternConfig_Vega10SEEDCCtrlForceStallConfig_Vega10AvfsPSMResetConfig_vega10PSMSEEDCStallPatternConfig_Vega10PSMSEEDCStallDelayConfig_Vega10PSMSEEDCCtrlResetConfig_Vega10PSMSEEDCCtrlConfig_Vega10PSMGCEDCDroopCtrlConfig_vega10PSMGCEDCCtrlResetConfig_vega10PSMGCEDCCtrlConfig_vega10SEEDCThresholdConfig_Vega10GCDiDtCtrl0Config_vega10vega10_enable_didt_config.cold__UNIQUE_ID_ddebug131.68689vega10_disable_didt_config.coldvega10_enable_power_containment.coldvega10_disable_power_containment.cold__func__.68690__func__.68671vega10_enable_fan_control_featurevega10_enable_fan_control_feature.coldvega10_disable_fan_control_featurevega10_disable_fan_control_feature.coldvega10_fan_ctrl_start_smc_fan_control.coldvega10_fan_ctrl_stop_smc_fan_control.coldvega10_thermal_disable_alert.coldvega10_thermal_setup_fan_table.coldvega10_enable_mgpu_fan_boost.coldvega10_start_thermal_controller.coldsmu10_power_off_asicsmu10_disable_dpm_taskssmu10_enable_dpm_taskssmu10_apply_state_adjust_rulessmu10_dpm_get_mclksmu10_dpm_get_sclksmu10_dpm_patch_boot_statesmu10_dpm_get_pp_table_entry_callbacksmu10_get_power_state_sizesmu10_set_cpu_power_statesmu10_store_cc6_datasmu10_get_dal_power_levelsmu10_get_performance_levelsmu10_get_current_shallow_sleep_clockssmu10_get_clock_by_type_with_latencysmu10_get_clock_by_type_with_voltagesmu10_get_max_high_clockssmu10_asic_resetsmu10_set_hard_min_fclk_by_freqsmu10_set_hard_min_dcefclk_by_freqsmu10_set_min_deep_sleep_dcefclksmu10_set_active_display_countsmu10_setup_asic_tasksmu10_smus_notify_pwesmu10_powergate_mmhubsmu10_force_clock_levelsmu10_force_clock_level.coldsmu10_display_clock_voltage_requestsmu10_display_clock_voltage_request.coldsmu10_dpm_force_dpm_levelsmu10_dpm_force_dpm_level.coldsmu10_get_power_profile_modetitle.72950profile_mode_setting.72948profile_name.72949smu10_print_clock_levelssmu10_set_watermarks_for_clocks_rangessmu10_powergate_vcnsmu10_dpm_get_num_of_pp_table_entriessmu10_dpm_get_pp_table_entrysmu10_hwmgr_backend_finismu10_powergate_sdmasmu10_set_power_state_taskssmu10_set_power_state_tasks.coldsmu10_read_sensorsmu10_disable_gfx_offsmu10_set_power_profile_modesmu10_set_power_profile_mode.coldsmu10_get_clock_voltage_dependency_table.isra.0smu10_gfx_off_controlsmu10_hwmgr_backend_initVddDcfClkVddSocClkVddFClkVddDispClkVddDppClkVddPhyClksmu10_hwmgr_backend_init.coldsmu10_hwmgr_funcspsm_set_statespsm_init_power_state_table.coldvega12_pp_tables_uninitializevega12_pp_tables_initialize.coldvega12_setup_asic_taskvega12_patch_boot_statevega12_dpm_get_sclkvega12_dpm_get_mclkvega12_get_fan_control_modevega12_get_dal_power_levelvega12_get_clock_by_type_with_latencyvega12_get_clock_by_type_with_voltagevega12_apply_clocks_adjust_rulesvega12_check_smc_update_required_for_display_configurationvega12_get_performance_levelvega12_display_clock_voltage_request.coldvega12_notify_cac_buffer_infovega12_upload_dpm_max_levelvega12_upload_dpm_max_level.coldvega12_upload_dpm_min_levelvega12_upload_dpm_min_level.coldvega12_force_clock_levelvega12_force_clock_level.coldvega12_pre_display_configuration_changed_taskvega12_pre_display_configuration_changed_task.coldvega12_disable_dpm_tasksvega12_disable_dpm_tasks.coldvega12_power_off_asicvega12_power_off_asic.coldvega12_set_ppfeature_status__UNIQUE_ID_ddebug130.71427__UNIQUE_ID_ddebug131.71432vega12_get_ppfeature_statusoutput_title.71411ppfeature_name.71410vega12_get_ppfeature_status.coldvega12_get_thermal_temperature_rangevega12_setup_single_dpm_tablevega12_setup_single_dpm_table.coldvega12_get_metrics_tablevega12_get_metrics_table.coldvega12_get_current_activity_percentvega12_get_current_activity_percent.coldvega12_get_gpu_powervega12_set_watermarks_for_clocks_rangesvega12_setup_default_dpm_tablesvega12_setup_default_dpm_tables.coldvega12_enable_dpm_tasksvega12_enable_dpm_tasks.coldvega12_hwmgr_backend_finivega12_find_highest_dpm_levelvega12_find_highest_dpm_level.coldvega12_dpm_force_dpm_levelvega12_dpm_force_dpm_level.coldvega12_set_mp1_statevega12_set_mp1_state.coldvega12_gfx_off_controlvega12_get_current_gfx_clk_freqvega12_get_current_gfx_clk_freq.coldvega12_get_current_mclk_freqvega12_get_current_mclk_freq.coldvega12_print_clock_levelsvega12_print_clock_levels.coldvega12_read_sensorvega12_display_configuration_changed_taskvega12_display_configuration_changed_task.coldvega12_set_fan_control_modevega12_hwmgr_backend_initvega12_notify_smc_display_config_after_ps_adjustmentvega12_notify_smc_display_config_after_ps_adjustment.coldvega12_enable_disable_vce_dpm.coldvega12_power_gate_vcevega12_enable_disable_uvd_dpm.coldvega12_power_gate_uvdvega12_hwmgr_funcs__func__.71428vega12_fan_ctrl_get_fan_speed_rpm.coldvega10_fuses_defaultphm_irq_process.coldphm_wait_for_register_unequal.part.0phm_wait_on_register.coldphm_wait_on_indirect_register.coldphm_trim_voltage_table.coldphm_get_svi2_mvdd_voltage_table.coldphm_get_svi2_vddci_voltage_table.coldphm_get_svi2_vdd_voltage_table.coldphm_get_voltage_index.coldphm_get_voltage_id.cold__UNIQUE_ID_ddebug146.75145__UNIQUE_ID_ddebug147.75173phm_get_sclk_for_voltage_evv.coldphm_initializa_dynamic_state_adjustment_rule_settings.coldphm_apply_dal_min_voltage_request.coldsmu9_irq_funcssmu_get_voltage_dependency_table_ppt_v1.cold__func__.75174__func__.75146vega20_pp_tables_uninitializevega20_pp_tables_initializevega20_pp_tables_initialize.coldvega20_get_sclk_odvega20_get_mclk_odvega20_get_performance_levelvega20_get_fan_control_modevega20_get_dal_power_levelvega20_get_clock_by_type_with_latencyvega20_get_clock_by_type_with_voltagevega20_apply_clocks_adjust_rulesvega20_check_smc_update_required_for_display_configurationvega20_display_clock_voltage_request.coldvega20_notify_cac_buffer_infovega20_upload_dpm_max_levelvega20_upload_dpm_max_level.coldvega20_upload_dpm_min_levelvega20_upload_dpm_min_level.coldvega20_force_clock_levelvega20_force_clock_level.coldvega20_pre_display_configuration_changed_taskvega20_pre_display_configuration_changed_task.coldvega20_notify_smc_display_config_after_ps_adjustmentvega20_notify_smc_display_config_after_ps_adjustment.coldvega20_set_mp1_stateCSWTCH.214vega20_set_mp1_state.coldvega20_enable_mgpu_fan_boostvega20_enable_mgpu_fan_boost.coldvega20_disable_dpm_tasksvega20_disable_dpm_tasks.coldvega20_power_off_asicvega20_power_off_asic.coldvega20_set_ppfeature_status__UNIQUE_ID_ddebug132.71814__UNIQUE_ID_ddebug133.71819vega20_get_ppfeature_statusoutput_title.71795ppfeature_name.71794vega20_get_ppfeature_status.coldvega20_setup_single_dpm_tablevega20_setup_single_dpm_table.coldvega20_setup_gfxclk_dpm_tablevega20_setup_gfxclk_dpm_table.coldvega20_setup_memclk_dpm_tablevega20_setup_memclk_dpm_table.coldvega20_odn_edit_dpm_tablevega20_odn_edit_dpm_table.coldvega20_set_mclk_odvega20_set_mclk_od.coldvega20_get_current_clk_freqvega20_get_current_clk_freq.coldvega20_print_clock_levelsvega20_print_clock_levels.coldvega20_get_max_sustainable_clockvega20_get_max_sustainable_clock.coldvega20_od8_get_gfx_clock_base_voltagevega20_od8_get_gfx_clock_base_voltage.coldvega20_get_power_profile_modetitle.71973profile_name.71972vega20_get_power_profile_mode.coldvega20_set_power_profile_modevega20_set_power_profile_mode.coldvega20_get_thermal_temperature_rangevega20_get_metrics_tablevega20_get_metrics_table.coldvega20_get_current_activity_percentvega20_get_current_activity_percent.coldvega20_get_gpu_powervega20_read_sensorvega20_set_watermarks_for_clocks_rangesvega20_setup_default_dpm_tablesvega20_setup_default_dpm_tables.coldvega20_setup_asic_taskvega20_setup_asic_task.coldvega20_hwmgr_backend_finivega20_enable_dpm_tasksvega20_enable_dpm_tasks.coldvega20_find_highest_dpm_levelvega20_find_highest_dpm_level.coldvega20_dpm_force_dpm_levelvega20_dpm_force_dpm_level.coldvega20_smu_i2c_bus_accessvega20_smu_i2c_bus_access.coldvega20_display_configuration_changed_taskvega20_display_configuration_changed_task.coldvega20_get_clock_rangesvega20_get_clock_ranges.coldvega20_dpm_get_sclkvega20_dpm_get_sclk.coldvega20_dpm_get_mclkvega20_dpm_get_mclk.coldvega20_set_fan_control_modevega20_hwmgr_backend_initvega20_set_sclk_odvega20_set_sclk_od.cold__UNIQUE_ID_ddebug130.71466__UNIQUE_ID_ddebug131.71471vega20_enable_disable_vce_dpm.coldvega20_power_gate_vce__UNIQUE_ID_ddebug134.71906__UNIQUE_ID_ddebug135.71911vega20_enable_disable_uvd_dpm.coldvega20_power_gate_uvdvega20_hwmgr_funcs__func__.71815__func__.71907__func__.71467vega20_disable_fan_control_featurevega20_disable_fan_control_feature.coldvega20_get_current_rpmvega20_get_current_rpm.coldvega20_fan_ctrl_set_static_mode.isra.0vega20_fan_ctrl_start_smc_fan_control.coldsoc15_baco_program_registers.coldexit_baco_tblclean_baco_tblpre_baco_tblenter_baco_tblpp_is_idlepp_wait_for_idlepp_sw_resetpp_set_powergating_statepp_set_clockgating_statepp_dpm_fw_loading_completepp_dpm_get_vce_clock_statepp_dpm_set_mp1_statepp_resumepp_suspendpp_late_finipp_hw_finipp_hw_initpp_hw_init.coldpp_dpm_load_fwpp_dpm_load_fw.coldpp_sw_finipp_sw_init__UNIQUE_ID_ddebug130.67787pp_get_power_limitpp_dpm_dispatch_taskspp_dpm_get_pp_tablepp_dpm_get_fan_speed_rpmpp_late_initpp_set_powergating_by_smu__func__.68234_rs.68232__func__.67908_rs.67906__func__.67916_rs.67914__func__.68226_rs.68224__func__.68250_rs.68248__func__.68242_rs.68240pp_set_powergating_by_smu.coldpp_dpm_switch_power_profile__func__.68141_rs.68139pp_dpm_switch_power_profile.coldpp_set_active_display_countpp_get_display_mode_validation_clockspp_display_clock_voltage_requestpp_set_watermarks_for_clocks_rangespp_get_clock_by_type_with_voltagepp_get_clock_by_type_with_latencypp_get_clock_by_typepp_get_display_power_levelpp_get_current_clocks__UNIQUE_ID_ddebug133.68176pp_display_configuration_changepp_dpm_set_pp_tablepp_dpm_get_pp_num_statespp_dpm_force_performance_levelpp_set_asic_baco_statepp_get_asic_baco_statepp_get_asic_baco_capabilitypp_set_min_deep_sleep_dcefclk__UNIQUE_ID_ddebug134.68282__func__.68283pp_set_hard_min_fclk_by_freq__UNIQUE_ID_ddebug136.68302__func__.68303pp_set_hard_min_dcefclk_by_freq__UNIQUE_ID_ddebug135.68292__func__.68293pp_enable_mgpu_fan_boostpp_dpm_get_current_power_statepp_dpm_get_performance_levelpp_dpm_read_sensorpp_asic_reset_mode_2__func__.68353_rs.68351pp_asic_reset_mode_2.coldpp_set_ppfeature_status__func__.68345_rs.68343pp_set_ppfeature_status.coldpp_get_ppfeature_status__func__.68336_rs.68334pp_get_ppfeature_status.coldpp_notify_smu_enable_pwe__func__.68272_rs.68270pp_notify_smu_enable_pwe.coldpp_dpm_get_mclk__func__.67900_rs.67898pp_dpm_get_mclk.coldpp_dpm_get_sclk__func__.67891_rs.67889pp_dpm_get_sclk.coldpp_smu_i2c_bus_access__func__.68362_rs.68360pp_smu_i2c_bus_access.coldpp_odn_edit_dpm_table__func__.68125_rs.68123pp_odn_edit_dpm_table.coldpp_set_power_profile_mode__UNIQUE_ID_ddebug132.68112__func__.68111_rs.68109pp_set_power_profile_mode.coldpp_set_power_limit__func__.68150_rs.68148pp_set_power_limit.coldpp_set_clockgating_by_smu__func__.67867_rs.67865pp_set_clockgating_by_smu.coldpp_dpm_set_fan_speed_rpm__func__.67983_rs.67981pp_dpm_set_fan_speed_rpm.coldpp_dpm_set_mclk_od__func__.68075_rs.68073pp_dpm_set_mclk_od.coldpp_dpm_get_mclk_od__func__.68066_rs.68064pp_dpm_get_mclk_od.coldpp_dpm_set_sclk_od__func__.68058_rs.68056pp_dpm_set_sclk_od.coldpp_dpm_get_sclk_od__func__.68049_rs.68047pp_dpm_get_sclk_od.coldpp_dpm_print_clock_levels__func__.68041_rs.68039pp_dpm_print_clock_levels.coldpp_dpm_force_clock_level__func__.68027_rs.68025__UNIQUE_ID_ddebug131.68028pp_dpm_force_clock_level.coldpp_dpm_get_fan_speed_percent__func__.67968_rs.67966pp_dpm_get_fan_speed_percent.coldpp_dpm_set_fan_speed_percent__func__.67959_rs.67957pp_dpm_set_fan_speed_percent.coldpp_dpm_get_fan_control_mode__func__.67950_rs.67948pp_dpm_get_fan_control_mode.coldpp_dpm_set_fan_control_mode__func__.67942_rs.67940pp_dpm_set_fan_control_mode.coldpp_get_power_profile_mode__func__.68101_rs.68099pp_get_power_profile_mode.coldpp_early_init__key.67771pp_dpm_funcs__func__.68177__func__.67788pp_ip_funcssmu_get_clock_infosmu_set_clockgating_statesmu_set_powergating_statesmu_sw_finismu_sw_fini.coldsmu_hw_finismu_smc_table_hw_initsmu_smc_table_hw_init.cold__func__.70858smu_resumesmu_early_init__key.70778smu_enable_umd_pstatesmu_feature_update_enable_state.part.0smu_feature_is_enabled.part.0smu_feature_init_dpm.part.0smu_hw_initsmu_hw_init.coldsmu_sw_init__key.70811__key.70812__key.70813__key.70814smu_sw_init.cold__smu_message_names__smu_feature_namessmu_suspendsmu_suspend.coldsmu_sys_set_pp_table.coldsmu_get_current_clocks.coldsmu_adjust_power_state_dynamic.coldsmu_late_initsmu_v11_0_check_fw_statussmu_v11_0_check_pptablesmu_v11_0_populate_smc_pptablesmu_v11_0_set_tool_table_locationsmu_v11_0_get_enabled_masksmu_v11_0_get_current_clk_freqsmu_v11_0_get_max_sustainable_clocks_by_dcsmu_v11_0_setup_pptablesmu_v11_0_get_vbios_bootup_values.coldsmu_v11_0_set_deep_sleep_dcefclksmu_v11_0_set_deep_sleep_dcefclk.coldsmu_v11_0_get_dpm_ultimate_freqsmu_v11_0_baco_get_statesmu_v11_0_baco_set_statesmu_v11_0_set_azalia_d3_pmesmu_v11_0_set_xgmi_pstatesmu_v11_0_get_fan_control_modesmu_v11_0_set_power_limitsmu_v11_0_set_power_limit.cold__func__.75762smu_v11_0_baco_is_supportsmu_v11_0_read_argsmu_v11_0_register_irq_handlersmu_v11_0_irq_funcssmu_v11_0_display_clock_voltage_requestsmu_v11_0_display_clock_voltage_request.cold__func__.75834smu_v11_0_load_microcodesmu_v11_0_write_watermarks_tablesmu_v11_0_write_pptablesmu_v11_0_check_fw_versionsmu_v11_0_check_fw_version.coldsmu_v11_0_get_clk_info_from_vbiossmu_v11_0_fini_smc_tablessmu_v11_0_init_microcodesmu_v11_0_init_microcode.coldsmu_v11_0_init_powersmu_v11_0_notify_memory_pool_locationsmu_v11_0_set_min_dcef_deep_sleepsmu_v11_0_init_display_countsmu_v11_0_irq_processsmu_v11_0_irq_process.coldsmu_v11_0_get_max_sustainable_clocksmu_v11_0_get_max_sustainable_clock.coldsmu_v11_0_init_max_sustainable_clockssmu_v11_0_init_max_sustainable_clocks.cold__func__.75756smu_v11_0_gfx_off_controlsmu_v11_0_baco_resetsmu_v11_0_set_watermarks_for_clock_rangessmu_v11_0_notify_display_changesmu_v11_0_read_sensorsmu_v11_0_set_fan_static_mode.isra.0smu_v11_0_start_thermal_controlsmu11_thermal_policysmu_v11_0_auto_fan_controlsmu_v11_0_auto_fan_control.cold__func__.75863smu_v11_0_set_fan_speed_rpmsmu_v11_0_set_fan_speed_percentsmu_v11_0_set_fan_control_modesmu_v11_0_set_fan_control_mode.cold__func__.75890smu_v11_0_wait_for_response.isra.0smu_v11_0_send_msg_with_paramsmu_v11_0_send_msgsmu_v11_0_fini_powersmu_v11_0_init_smc_tablessmu_v11_0_set_allowed_masksmu_v11_0_system_features_controlsmu_v11_0_system_features_control.cold__func__.5293smu_v11_0_parse_pptablesmu_v11_0_funcssmu_v11_0_set_smu_funcs.coldsmu_v12_0_check_fw_statussmu_v12_0_get_dpm_ultimate_freqsmu_v12_0_get_dpm_ultimate_freq.coldsmu_v12_0_read_argsmu_v12_0_check_fw_versionsmu_v12_0_check_fw_version.coldsmu_v12_0_populate_smc_tablessmu_v12_0_fini_smc_tablessmu_v12_0_powergate_sdmasmu_v12_0_powergate_vcnsmu_v12_0_gfx_off_controlsmu_v12_0_wait_for_response.isra.0smu_v12_0_send_msg_with_paramsmu_v12_0_send_msg_with_param.coldsmu_v12_0_send_msgsmu_v12_0_send_msg.coldsmu_v12_0_set_gfx_cgpgsmu_v12_0_init_smc_tablessmu_v12_0_funcssmu_v12_0_set_smu_funcs.coldvega20_get_smu_table_indexvega20_table_mapvega20_get_pwr_src_indexvega20_pwr_src_mapvega20_get_smu_feature_indexvega20_feature_mask_mapvega20_get_smu_clk_indexvega20_clk_mapvega20_get_smu_msg_indexvega20_message_mapvega20_get_workload_typevega20_workload_mapvega20_run_btc_afllvega20_populate_umd_state_clkvega20_get_od_percentagevega20_get_profiling_clk_maskvega20_set_thermal_fan_tablevega20_overdrive_get_gfx_clk_base_voltagevega20_overdrive_get_gfx_clk_base_voltage.coldvega20_get_fan_speed_rpmvega20_get_fan_speed_rpm.coldvega20_get_fan_speed_percent__func__.73786vega20_set_single_dpm_tablevega20_set_single_dpm_table.coldvega20_check_powerplay_tablevega20_check_powerplay_table.coldvega20_tables_initvega20_upload_dpm_levelvega20_upload_dpm_level.coldvega20_pre_display_config_changedvega20_pre_display_config_changed.cold__func__.73809vega20_notify_smc_dispaly_configvega20_notify_smc_dispaly_config.cold__func__.73840vega20_display_config_changedvega20_display_config_changed.coldvega20_force_clk_levelsvega20_force_clk_levels.coldvega20_get_current_power_statevega20_store_powerplay_tablevega20_set_default_dpm_tablevega20_set_default_dpm_table.coldtitle.73772profile_name.73771__func__.73774vega20_print_clk_levelsvega20_print_clk_levels.coldvega20_set_od_percentagevega20_set_od_percentage.coldvega20_get_allowed_feature_maskvega20_append_powerplay_tablevega20_set_watermarks_table__func__.73852vega20_unforce_dpm_levelsvega20_unforce_dpm_levels.coldvega20_force_dpm_limit_valuevega20_force_dpm_limit_value.coldvega20_dpm_set_vce_enablevega20_dpm_set_uvd_enablevega20_set_default_od8_setttingsvega20_set_default_od_settingsvega20_set_default_od_settings.coldvega20_allocate_dpm_contextvega20_ppt_funcsarcturus_get_smu_msg_indexarcturus_message_maparcturus_get_smu_feature_indexarcturus_feature_mask_maparcturus_check_powerplay_tablearcturus_run_btc_afllarcturus_populate_umd_state_clkarcturus_get_thermal_temperature_rangearcturus_get_profiling_clk_maskarcturus_is_dpm_runningarcturus_get_power_limitarcturus_get_power_limit.cold__func__.73711arcturus_dump_pptablearcturus_upload_dpm_levelarcturus_upload_dpm_level.coldarcturus_set_power_profile_modearcturus_set_power_profile_mode.coldarcturus_set_single_dpm_tablearcturus_set_single_dpm_table.cold__func__.73447arcturus_get_workload_typearcturus_workload_maparcturus_get_workload_type.coldarcturus_get_pwr_src_indexarcturus_pwr_src_maparcturus_get_pwr_src_index.coldarcturus_get_smu_table_indexarcturus_table_maparcturus_get_smu_table_index.coldarcturus_get_smu_clk_indexarcturus_clk_maparcturus_get_smu_clk_index.coldarcturus_force_clk_levelsarcturus_force_clk_levels.coldarcturus_store_powerplay_tablearcturus_set_default_dpm_tablearcturus_set_default_dpm_table.cold__func__.73461arcturus_get_metrics_tablearcturus_get_metrics_table.coldarcturus_get_current_clk_freq_by_tablemetrics.73654arcturus_get_fan_speed_rpmarcturus_get_fan_speed_percentarcturus_get_current_activity_percentarcturus_get_current_activity_percent.coldarcturus_thermal_get_temperaturearcturus_thermal_get_temperature.coldarcturus_read_sensorarcturus_tables_initarcturus_get_power_profile_modetitle.73717profile_name.73716arcturus_print_clk_levelsarcturus_print_clk_levels.coldarcturus_get_allowed_feature_maskarcturus_append_powerplay_tablearcturus_append_powerplay_table.coldarcturus_find_highest_dpm_levelarcturus_find_highest_dpm_level.cold__func__.73673arcturus_unforce_dpm_levelsarcturus_unforce_dpm_levels.coldarcturus_force_dpm_limit_valuearcturus_force_dpm_limit_value.coldarcturus_allocate_dpm_contextarcturus_ppt_funcsnavi10_get_smu_msg_indexnavi10_message_mapnavi10_get_smu_clk_indexnavi10_clk_mapnavi10_get_smu_feature_indexnavi10_feature_mask_mapnavi10_get_smu_table_indexnavi10_table_mapnavi10_get_pwr_src_indexnavi10_pwr_src_mapnavi10_get_workload_typenavi10_workload_mapnavi10_check_powerplay_tablenavi10_set_default_dpm_tablenavi10_is_dpm_runningnavi10_get_uclk_dpm_statesnavi10_get_thermal_temperature_rangenavi10_get_power_limitnavi10_get_power_limit.cold__func__.76431navi10_display_disable_memory_clock_switchnavi10_get_profiling_clk_masknavi10_get_clock_by_type_with_latencynavi10_set_performance_levelnavi10_force_clk_levelsnavi10_set_power_profile_modenavi10_set_power_profile_mode.cold__func__.76308navi10_get_metrics_tablenavi10_get_metrics_table.coldnavi10_get_current_clk_freq_by_tablenavi10_get_fan_speed_rpmnavi10_get_fan_speed_percentnavi10_get_current_activity_percentnavi10_get_current_activity_percent.coldnavi10_thermal_get_temperaturenavi10_thermal_get_temperature.coldnavi10_read_sensornavi10_store_powerplay_tablenavi10_tables_initnavi10_allocate_dpm_contextnavi10_unforce_dpm_levelsnavi10_force_dpm_limit_valuenavi10_pre_display_config_changednavi10_populate_umd_state_clknavi10_notify_smc_dispaly_confignavi10_notify_smc_dispaly_config.cold__func__.76328navi10_get_power_profile_modetitle.76294profile_name.76293navi10_get_power_profile_mode.cold__func__.76296navi10_print_clk_levelsnavi10_get_allowed_feature_masknavi10_append_powerplay_tablenavi10_set_watermarks_tablenavi10_dpm_set_uvd_enablenavi10_display_config_changednavi10_ppt_funcsrenoir_get_smu_msg_indexrenoir_message_maprenoir_get_smu_table_indexrenoir_table_maprenoir_get_dpm_uclk_limitedrenoir_print_clk_levelsrenoir_tables_initrenoir_ppt_funcsdm_is_idledm_wait_for_idledm_check_soft_resetdm_soft_resetdm_set_clockgating_statedm_set_powergating_stateamdgpu_dm_audio_component_bindamdgpu_dm_audio_component_opsamdgpu_dm_audio_component_unbinddm_bandwidth_updateamdgpu_dm_connector_detectdm_crtc_helper_disabledm_crtc_helper_mode_fixupdm_encoder_helper_disabledm_encoder_helper_atomic_checkdm_plane_atomic_async_checkamdgpu_dm_i2c_functrace_event_define_fields_amdgpu_dc_rregtrace_event_define_fields_amdgpu_dc_wregtrace_event_define_fields_amdgpu_dc_performanceperf_trace_amdgpu_dc_rregperf_trace_amdgpu_dc_wregtrace_raw_output_amdgpu_dc_rregtrace_raw_output_amdgpu_dc_wregtrace_raw_output_amdgpu_dc_performance__bpf_trace_amdgpu_dc_rreg__bpf_trace_amdgpu_dc_wreg__bpf_trace_amdgpu_dc_performanceupdate_stream_scaling_settingsdetect_mst_link_for_all_connectorss3_handle_mstemulated_link_detectdm_suspendamdgpu_dm_audio_component_get_eldamdgpu_dm_finiamdgpu_dm_audio_component_bind_opsdm_hw_finifill_dc_scaling_infofill_plane_buffer_attributesdm_atomic_destroy_statefill_dc_plane_info_and_addrupdate_freesync_state_on_streammanage_dm_interruptsamdgpu_dm_enable_crtc_interruptsamdgpu_dm_atomic_commitdm_atomic_duplicate_statedm_plane_atomic_checkdm_plane_helper_prepare_fbdm_plane_helper_prepare_fb.colddm_drm_plane_duplicate_statedm_drm_plane_resetdm_crtc_destroy_stateamdgpu_dm_crtc_destroyamdgpu_dm_encoder_destroyamdgpu_dm_connector_add_common_modesget_modes.coldamdgpu_dm_connector_destroyamdgpu_dm_connector_unregisteramdgpu_dm_backlight_get_brightnessamdgpu_dm_update_backlight_capsamdgpu_dm_backlight_update_statusregister_hpd_handlershandle_hpd_irqdm_crtc_get_scanoutposdm_sw_finidm_sw_initdm_sw_init.colddm_early_initdm_display_funcstrace_event_raw_event_amdgpu_dc_performanceadjust_colour_depth_from_display_info.isra.0fill_stream_properties_from_drm_display_modeCSWTCH.338is_hdr_metadata_different.isra.0is_scaling_state_differentget_crtc_by_otg_inst.isra.0dm_pflip_high_irqdm_vupdate_high_irqdm_crtc_high_irqfill_hdr_info_packetamdgpu_dm_connector_atomic_checkhandle_cursor_update.isra.0__func__.90785__func__.90750dm_plane_atomic_async_updateamdgpu_dm_commit_cursors.isra.0amdgpu_dm_plane_init.isra.0.part.0dm_plane_helper_funcsdm_late_init.part.0dm_late_initdm_vblank_get_counteramdgpu_dm_plane_init.isra.0dm_plane_funcsdm_update_crtc_state__func__.91307dm_crtc_helper_atomic_checkdm_crtc_reset_statetrace_event_raw_event_amdgpu_dc_rregtrace_event_raw_event_amdgpu_dc_wregdm_crtc_duplicate_stateget_fb_info.isra.0get_fb_info.isra.0.coldfill_dc_plane_attributesdm_determine_update_type_for_commitperf_trace_amdgpu_dc_performancedm_plane_helper_cleanup_fbdm_plane_helper_cleanup_fb.colddm_disable_vblankdm_enable_vblankamdgpu_dm_commit_planes.constprop.0__func__.90902amdgpu_dm_commit_planes.constprop.0.colddm_update_plane_stateamdgpu_dm_atomic_checkinitialize_planeamdgpu_dm_i2c_xferamdgpu_dm_atomic_commit_tail__func__.90823__func__.91068__key.90660CSWTCH.574__func__.91606amdgpu_dm_update_connector_after_detectdm_resumeamdgpu_dm_initialize_drm_deviceamdgpu_dm_mode_funcsamdgpu_dm_mode_config_helperfuncsdm_atomic_state_funcsamdgpu_dm_crtc_funcsamdgpu_dm_crtc_helper_funcsamdgpu_dm_encoder_funcs__func__.90701amdgpu_dm_i2c_algoamdgpu_dm_connector_funcsamdgpu_dm_connector_helper_funcsamdgpu_dm_backlight_opsamdgpu_dm_init__key.89238__key.89239amdgpu_dm_init.colddm_hw_initamdgpu_dm_funcs__bpf_trace_tp_map_amdgpu_dc_performance__bpf_trace_tp_map_amdgpu_dc_wreg__bpf_trace_tp_map_amdgpu_dc_rreg__event_amdgpu_dc_performanceprint_fmt_amdgpu_dc_performance__event_amdgpu_dc_wregprint_fmt_amdgpu_dc_wreg__event_amdgpu_dc_rregprint_fmt_amdgpu_dc_rregtrace_event_type_funcs_amdgpu_dc_performancetrace_event_type_funcs_amdgpu_dc_wregtrace_event_type_funcs_amdgpu_dc_rregevent_class_amdgpu_dc_performancestr__amdgpu_dm__trace_system_nameevent_class_amdgpu_dc_wregevent_class_amdgpu_dc_rreg__tpstrtab_amdgpu_dc_performance__tpstrtab_amdgpu_dc_wreg__tpstrtab_amdgpu_dc_rreg.LC19.LC78dm_irq_work_funcamdgpu_dm_set_hpd_irq_stateamdgpu_dm_irq_handleramdgpu_dm_irq_handler.coldamdgpu_dm_set_crtc_irq_state__func__.71908amdgpu_dm_set_vupdate_irq_state__func__.71915amdgpu_dm_set_pflip_irq_state__func__.71901dm_crtc_irq_funcsdm_vupdate_irq_funcsdm_pageflip_irq_funcsdm_hpd_irq_funcsdm_mst_best_encoderdm_dp_destroy_mst_connectordm_dp_mst_register_connectordm_dp_mst_get_modesdm_dp_mst_connector_destroyamdgpu_dm_mst_connector_early_unregisteramdgpu_dm_mst_connector_late_registerdm_dp_mst_detectdm_dp_aux_transferCSWTCH.94dm_dp_add_mst_connectordm_dp_mst_connector_funcsdm_dp_mst_connector_helper_funcsdm_mst_cbs__is_lut_linear__drm_lut_to_dc_gammadm_helpers_parse_edid_caps.colddm_dtn_log_append_v.coldmsg.71823dm_dtn_log_begin.coldmsg.71838dm_dtn_log_end.colddm_h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