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?QQpllnadcmadcndacmdacbdivSampling rate not supported codec_clkinmclkFailed to parse DT node ldoiniovdvavtlv320aic32x4 rstnMissing supply 'iov' Failed to setup regulators Failed to register component Failed to enable clocks tlv320aic32x4-hifiCapturePlaybackHPL Output MixerL_DAC SwitchLeft DACIN1_L SwitchIN1_LHPL PowerHPLLOL Output MixerLOL PowerLOLHPR Output MixerR_DAC SwitchRight DACIN1_R SwitchIN1_RHPR PowerHPRLOR Output MixerLOR PowerLORRight ADC10 kOhm20 kOhm40 kOhmIN2_RIN3_RIN2_LCM_RIN3_LLeft ADCCM_LLeft PlaybackRight PlaybackRight CaptureLeft CaptureMic BiasIN3_L R- SwitchIN1_L R- SwitchCM_R R- SwitchIN2_L R+ SwitchIN3_R R+ SwitchIN2_R R+ SwitchIN1_R R+ SwitchIN3_R L- SwitchIN2_R L- SwitchCM_L L- SwitchIN1_R L+ SwitchIN3_L L+ SwitchIN2_L L+ SwitchIN1_L L+ SwitchOffPCM Playback VolumeHP Driver Gain VolumeLO Driver Gain VolumeHP DAC Playback SwitchLO DAC Playback SwitchMic PGA SwitchADCFGA Left Mute SwitchADCFGA Right Mute SwitchADC Level VolumePGA Level VolumeAuto-mute SwitchAGC Left SwitchAGC Right SwitchAGC Target LevelAGC Gain HysteresisAGC HysteresisAGC Noise ThresholdAGC Max PGAAGC Attack TimeAGC Decay TimeAGC Noise DebounceAGC Signal DebounceP3P2P1Full Chip1.65VMFP5 GPIOMFP4 GPIOMFP3 GPIOMFP2 GPIOMFP1 GPIObclkgpiodinpllcodec_clkinndacmdacnadcmadcbdivmclkCould not set clocks to support sample rate. 3aic32x4: invalid DAI master/slave interface 3aic32x4: invalid DAI interface format 7%s: Mic Bias will be turned ON 7%s: Mic Bias will be turned OFF Missing supply 'dv' or 'ldoin' Missing supply 'av' or 'ldoin' Failed to enable regulator iov Failed to enable regulator ldo Failed to enable regulator dv Failed to enable regulator av 3%s: MFP5 is not configure as a GPIO output 3%s: MFP4 is not configure as a GPIO output 3%s: MFP2 is not configure as a GPIO output IN1_R to Right Mixer Positive ResistorIN2_R to Right Mixer Positive ResistorIN3_R to Right Mixer Positive ResistorIN2_L to Right Mixer Positive ResistorCM_R to Right Mixer Negative ResistorIN1_L to Right Mixer Negative ResistorIN3_L to Right Mixer Negative ResistorIN1_L to Left Mixer Positive ResistorIN2_L to Left Mixer Positive ResistorIN3_L to Left Mixer Positive ResistorIN1_R to Left Mixer Positive ResistorCM_L to Left Mixer Negative ResistorIN2_R to Left Mixer Negative ResistorIN3_R to Left Mixer Negative ResistorDAC Left Playback PowerTune SwitchDAC Right Playback PowerTune SwitchLO Playback Common Mode Switchlicense=GPLauthor=Javier Martin description=ASoC tlv320aic32x4 codec driversrcversion=45326D9424CCB3CCCFFDE2Bdepends=snd-pcm,snd-soc-core,sndretpoline=Yintree=Yname=snd_soc_tlv320aic32x4vermagic=5.4.0-216-generic SMP mod_unload modversions aic32x4_removeaic32x4_probeaic32x4_regmap_configaic32x4_register_clockspmodule_layout6jsnd_pcm_format_widthDclk_hw_register_clkdev2)snd_soc_info_enum_double3devm_clk_registerprintk )snd_soc_add_component_controlsһXMdev_get_regmapLGsnd_soc_dapm_put_volswڶV3_dev_errϢ snd_ctl_boolean_mono_infoSdždevm_gpio_request_one1snd_soc_info_volswphclk_bulk_enableWCclk_round_ratesnd_soc_get_enum_double_Xdevm_regulator_get) __stack_chk_failǖ#clk_set_parent3devm_clk_bulk_getndevm_snd_soc_register_componentsnd_soc_component_writeL6devm_regulator_get_optionalm__fentry__{[devm_clk_getvvclk_set_rate*snd_soc_put_enum_double)cclk_bulk_unprepare-K@gpiod_set_raw_valueK}Gclk_bulk_disablersnd_soc_component_read32Ydevm_kmallocc}regmap_writedregulator_enable%e$snd_soc_dapm_put_enum_double\d[cZbYaX`W_W_V^V^^^VV@@__((STRRRR00ABP2d222  snd_soc_tlv320aic32x4GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0snd-soc-tlv320aic32x4.koUo#!0 = U j}7  %>*K0] g,~P,,Pq5,@* p*":fPGgPT`gPagPn hP{@ OXk9`0e%W@@Oeeu <  7C, ]0@)5(J\d[P~[ [PQPPP@PPOPOP) OPANPY WPqVP`VPVPUP@UPTP`QhQh"`Rh2RhC`ShTShe`Thv[ WhXhXhYhYhZhZhhh&h<hRhhh~hehehh h h h fh  h5 hK ham h  h h hhhh h* h@ hV hl h h h e f 3 P! 6< P<U *q ' )  * P- ) + K/ 0[K Kn N 0Q  @    0C   j*  ? jW l @i| ` h      _    / }K \ p t       (:IZo@0+JQc|  0Gd p{__UNIQUE_ID_srcversion43__UNIQUE_ID_depends42____versions__UNIQUE_ID_retpoline41__UNIQUE_ID_intree40__UNIQUE_ID_name39__UNIQUE_ID_vermagic38_note_6__ksymtab_aic32x4_regmap_config__kstrtab_aic32x4_regmap_config__ksymtab_aic32x4_probe__kstrtab_aic32x4_probe__ksymtab_aic32x4_remove__kstrtab_aic32x4_removeaic32x4_muteaic32x4_hw_paramsCSWTCH.39aic32x4_hw_params.coldaic32x4_set_dai_fmtaic32x4_set_dai_fmt.coldmic_bias_event__func__.44797aic32x4_set_dai_sysclkaic32x4_get_mfp5_gpioaic32x4_get_mfp3_gpioaic32x4_get_mfp1_gpioaic32x4_component_probeaic32x4_mfp5aic32x4_mfp4aic32x4_mfp3aic32x4_mfp2aic32x4_mfp1aic32x4_disable_regulatorsaic32x4_daisoc_component_dev_aic32x4aic32x4_probe.coldaic32x4_set_mfp5_gpioaic32x4_set_mfp5_gpio.cold__func__.44841aic32x4_set_mfp4_gpioaic32x4_set_mfp4_gpio.cold__func__.44827aic32x4_set_mfp2_gpioaic32x4_set_mfp2_gpio.cold__func__.44813aic32x4_set_bias_level__UNIQUE_ID_license91__UNIQUE_ID_author90__UNIQUE_ID_description89aic32x4_snd_controlsaic32x4_dapm_widgetsaic32x4_dapm_routesaic32x4_opsaic32x4_regmap_pageshpl_output_mixer_controlslol_output_mixer_controlshpr_output_mixer_controlslor_output_mixer_controlsin1r_to_rmixer_controlsin2r_to_rmixer_controlsin3r_to_rmixer_controlsin2l_to_rmixer_controlscmr_to_rmixer_controlsin1l_to_rmixer_controlsin3l_to_rmixer_controlsin1l_to_lmixer_controlsin2l_to_lmixer_controlsin3l_to_lmixer_controlsin1r_to_lmixer_controlscml_to_lmixer_controlsin2r_to_lmixer_controlsin3r_to_lmixer_controlsin3l_rpga_n_enumin1l_rpga_n_enumcmr_rpga_n_enumin2l_rpga_p_enumin3r_rpga_p_enumin2r_rpga_p_enumin1r_rpga_p_enumresistor_textin3r_lpga_n_enumin2r_lpga_n_enumcml_lpga_n_enumin1r_lpga_p_enumin3l_lpga_p_enumin2l_lpga_p_enumin1l_lpga_p_enum__compound_literal.31__compound_literal.30__compound_literal.28__compound_literal.29__compound_literal.26__compound_literal.27tlv_pcm__compound_literal.4l_ptm_enumr_ptm_enumtlv_driver_gain__compound_literal.5__compound_literal.6__compound_literal.7__compound_literal.8lo_cm_enum__compound_literal.9__compound_literal.10__compound_literal.11tlv_adc_vol__compound_literal.12tlv_step_0_5__compound_literal.13__compound_literal.14__compound_literal.15__compound_literal.16__compound_literal.17__compound_literal.18__compound_literal.19__compound_literal.20__compound_literal.21__compound_literal.22__compound_literal.23__compound_literal.24__compound_literal.25ptm_textlo_cm_text__ksymtab_aic32x4_register_clocks__kstrtab_aic32x4_register_clocksclk_aic32x4_pll_round_rateclk_aic32x4_div_round_rateclk_aic32x4_div_set_rateclk_aic32x4_bdiv_set_parentclk_aic32x4_div_unprepareclk_aic32x4_div_prepareclk_aic32x4_codec_clkin_set_parentclk_aic32x4_pll_set_parentclk_aic32x4_pll_unprepareclk_aic32x4_pll_prepareclk_aic32x4_bdiv_get_parentclk_aic32x4_div_recalc_rateclk_aic32x4_codec_clkin_get_parentclk_aic32x4_pll_get_parentclk_aic32x4_pll_is_preparedaic32x4_register_clkaic32x4_clkdesc_arrayclk_aic32x4_pll_recalc_rateclk_aic32x4_pll_set_rate__compound_literal.0aic32x4_pll_ops__compound_literal.1aic32x4_codec_clkin_ops__compound_literal.2aic32x4_div_ops__compound_literal.3aic32x4_bdiv_opssnd_soc_dapm_put_enum_doubleregulator_enable__crc_aic32x4_register_clocksregmap_writedevm_kmalloc__this_modulesnd_soc_component_read32__crc_aic32x4_regmap_configclk_bulk_disablegpiod_set_raw_value__crc_aic32x4_probeclk_bulk_unpreparesnd_soc_put_enum_doubleclk_set_ratedevm_clk_get__fentry__devm_regulator_get_optionalsnd_soc_component_writedevm_snd_soc_register_componentdevm_clk_bulk_getclk_set_parent__stack_chk_fail__crc_aic32x4_removedevm_regulator_getsnd_soc_get_enum_doubleclk_round_rateclk_bulk_enablesnd_soc_info_volswdevm_gpio_request_onesnd_ctl_boolean_mono_info_dev_errsnd_soc_dapm_put_volswdev_get_regmapsnd_soc_add_component_controlsprintkdevm_clk_registersnd_soc_info_enum_doublesnd_soc_get_volswregmap_readsnd_soc_put_volswclk_get_parentsnd_soc_component_update_bits__const_udelaygpio_to_descregmap_update_bits_baseregulator_disableclk_bulk_preparesnd_soc_dapm_get_volswsnd_soc_dapm_get_enum_doubleclk_hw_register_clkdevsnd_pcm_format_width"1      !3 ,<Qcz *<BQ(D>I>Q     *AZq :    9 , H U j z        ' B N fV h t g|   `g   g    h 8 A R d v     F F A dI P j\ c no y q        6 A e l t   t  FuTC Kry K51QYSqi  r {  />HQQ!DQw '1\ *1Z}2=gq @D : ? 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