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_unops390_insn_bfp128_compares390_insn_bfp128_converts390_insn_bfp128_convert_tos390_insn_bfp128_convert_froms390_insn_dfp_binops390_insn_dfp_unops390_insn_dfp_intops390_insn_dfp_compares390_insn_dfp_converts390_insn_dfp_rerounds390_insn_fp_converts390_insn_fp128_converts390_insn_dfp128_binops390_insn_dfp128_unops390_insn_dfp128_intops390_insn_dfp128_compares390_insn_dfp128_convert_tos390_insn_dfp128_convert_froms390_insn_dfp128_rerounds390_insn_mfences390_insn_mimms390_insn_madds390_insn_set_fpc_bfprms390_insn_set_fpc_dfprms390_insn_xdirects390_insn_xindirs390_insn_xassisteds390_insn_evchecks390_insn_profincs390_insn_vec_amodeops390_insn_vec_amodeintops390_insn_vec_binops390_insn_vec_triops390_insn_as_stringppS390Instremit_S390InstrevCheckSzB_S390patchProfInc_S390chainXDirect_S390unchainXDirect_S390s390x_vec_op_tiselSB_S390s390x_vec_op_ts390_disasmgetRRegUniverse_MIPSppHRegMIPSshowMIPSCondCodeshowMIPSFpOpshowMIPSFpGpMoveOpshowMIPSMoveCondOpMIPSAMode_IRMIPSAMode_RRdopyMIPSAModenextMIPSAModeFloatnextMIPSAModeIntppMIPSAModeMIPSRH_ImmMIPSRH_RegppMIPSRHshowMIPSUnaryOpshowMIPSAluOpshowMIPSShftOpshowMIPSMaccOpshowMsaDFshowMsaDFFshowMsaMI10opshowMsaElmOpshowMsa2ROpshowRotxOpshowMsa2RFOpshowMsa3ROpshowMsaVecOpshowMsaBitOpshowMsa3RFOpMIPSInstr_LIMIPSInstr_AluMIPSInstr_ShftMIPSInstr_UnaryMIPSInstr_CmpMIPSInstr_MulMIPSInstr_MultMIPSInstr_ExtMIPSInstr_Mulr6MIPSInstr_MsubMIPSInstr_MaddMIPSInstr_DivMIPSInstr_Divr6MIPSInstr_CallMIPSInstr_CallAlwaysMIPSInstr_XDirectMIPSInstr_XIndirMIPSInstr_XAssistedMIPSInstr_LoadMIPSInstr_StoreMIPSInstr_LoadLMIPSInstr_CasMIPSInstr_StoreCMIPSInstr_MthiMIPSInstr_MtloMIPSInstr_MfhiMIPSInstr_MfloMIPSInstr_RdWrLRMIPSInstr_FpLdStMIPSInstr_FpUnaryMIPSInstr_FpBinaryMIPSInstr_FpTernaryMIPSInstr_FpConvertMIPSInstr_FpCompareMIPSInstr_FpMinMaxMIPSInstr_MtFCSRMIPSInstr_MfFCSRMIPSInstr_FpGpMoveMIPSInstr_MoveCondMIPSInstr_EvCheckMIPSInstr_ProfIncMIPSInstr_MsaMi10MIPSInstr_MsaElmMIPSInstr_Msa2RMIPSInstr_Msa3RMIPSInstr_MsaVecMIPSInstr_MsaBitMIPSInstr_Msa3RFMIPSInstr_Msa2RFMIPSInstr_BitswapppMIPSInstrgetRegUsage_MIPSInstrmapRegs_MIPSInstrgenSpill_MIPSgenReload_MIPSgenMove_MIPSemit_MIPSInstrevCheckSzB_MIPSchainXDirect_MIPSunchainXDirect_MIPSpatchProfInc_MIPSiselSB_MIPS// 1842 ` libvex_amd64_linux_a-main_globals.o/ libvex_amd64_linux_a-main_main.o/ libvex_amd64_linux_a-main_util.o/ libvex_amd64_linux_a-ir_defs.o/ libvex_amd64_linux_a-ir_inject.o/ libvex_amd64_linux_a-ir_match.o/ libvex_amd64_linux_a-ir_opt.o/ libvex_amd64_linux_a-guest_generic_bb_to_IR.o/ libvex_amd64_linux_a-guest_generic_x87.o/ libvex_amd64_linux_a-guest_x86_helpers.o/ libvex_amd64_linux_a-guest_x86_toIR.o/ libvex_amd64_linux_a-guest_amd64_helpers.o/ libvex_amd64_linux_a-guest_amd64_toIR.o/ libvex_amd64_linux_a-guest_ppc_helpers.o/ libvex_amd64_linux_a-guest_ppc_toIR.o/ libvex_amd64_linux_a-guest_arm_helpers.o/ libvex_amd64_linux_a-guest_arm_toIR.o/ libvex_amd64_linux_a-guest_arm64_helpers.o/ libvex_amd64_linux_a-guest_arm64_toIR.o/ libvex_amd64_linux_a-guest_s390_helpers.o/ libvex_amd64_linux_a-guest_s390_toIR.o/ libvex_amd64_linux_a-guest_mips_helpers.o/ libvex_amd64_linux_a-guest_mipsdsp_toIR.o/ libvex_amd64_linux_a-guest_mips_toIR.o/ libvex_amd64_linux_a-host_generic_regs.o/ libvex_amd64_linux_a-host_generic_simd64.o/ libvex_amd64_linux_a-host_generic_simd128.o/ libvex_amd64_linux_a-host_generic_simd256.o/ libvex_amd64_linux_a-host_generic_maddf.o/ libvex_amd64_linux_a-host_generic_reg_alloc2.o/ libvex_amd64_linux_a-host_generic_reg_alloc3.o/ libvex_amd64_linux_a-host_x86_defs.o/ libvex_amd64_linux_a-host_x86_isel.o/ libvex_amd64_linux_a-host_amd64_defs.o/ libvex_amd64_linux_a-host_amd64_isel.o/ libvex_amd64_linux_a-host_ppc_defs.o/ libvex_amd64_linux_a-host_ppc_isel.o/ libvex_amd64_linux_a-host_arm_defs.o/ libvex_amd64_linux_a-host_arm_isel.o/ libvex_amd64_linux_a-host_arm64_defs.o/ libvex_amd64_linux_a-host_arm64_isel.o/ libvex_amd64_linux_a-host_s390_defs.o/ libvex_amd64_linux_a-host_s390_isel.o/ libvex_amd64_linux_a-s390_disasm.o/ libvex_amd64_linux_a-host_mips_defs.o/ libvex_amd64_linux_a-host_mips_isel.o/ /0 0 0 0 644 1128 ` ELF>(@@ GNU  $+(90J8vex_controlvex_traceflagsvex_debuglevelvex_log_bytesvex_failure_exitvex_initdone.symtab.strtab.shstrtab.text.data.bss.note.GNU-stack.note.gnu.property@!@'@9 ,@<@ `  WO/37 0 0 0 644 54712 ` ELF>8@@f.AWAVAUATUHSHHHcH>%=-H=H= H= H=HHcHDH%= tkH= t]HctFH=u8@HH@HEHHHD@HH=1=L-HҀ=L-H뵀=L-H똀=L%Hx=L%txH\=L%t H@LH1?H5ItHH5L1HH5L1L-H AM}@%= `-H% ti=tbH iftD1H Hz9t,t 9tHH9B 9uHA @ NE4tttH?r@8h7WH^fD8%{/=v%wH@Hf%)u=- bHif= ==HDgHfD?tHfDH=%tVzH=-HL@@$H+=tH@t=OH=HHHHH{HjHYHHH7H&HH@PXH=1HH H5H=ff.ff.S HCHHHxHCH< HCC[H=H=H5]HtHAЅAA = A!d8QM9ey{A~dgdO7oD1oI HfDH H5H=fH H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H !H5H=AWAVAUATUSHH-L HHIHHcH>@AAG@- HHcH>A=II !IIH+IUAAO@u AGHAi H5HcH>DADA;DHItH \H5H=f.AG -" D$ E1D$D$D$HD$(HD$8HD$0AG׉L$ T$ƉD$$T$L$ HHC9uD$$A;GH=AGLA9G OE-HMHS HD$(IHsPD$,PD$0PD$0PIAAATPIGPAPAPAGLPAAAMHIMYIrFfML9 1DH9 f|B'vH QH5H=@A }D$ E1D$D$D$HD$(HD$8HD$07AG -D$ E1D$D$`D$XHD$(HD$8HD$0A *D$ E1D$D$D$HD$(HD$8HD$0A D$ E1D$D$`D$XHD$(HD$8HD$0/A <D$ E1D$DD$tD$pHD$(HD$8HD$0A hHD$ L5HD$(HD$HD$8HD$pD$hHD$0rfA H yH5H=AG -D$ E1D$D$XD$PHD$(HD$8HD$0H XH5H=fH=1DE-LDH51EMLMHT$8Ht$0I@IHt*HLMGHEIIAUHT$8Y^IIHt*HLMGHEIIAUHT$8IXZ I!LLIHDLH5]HHL[]A\A]A^A_H SH5H=fH TH5H=H UH5H=fH=1IH [H5H=H YH5H=IDH -H5H=fH NH5H=H OH5H=H=1LH=1zH=1LH=1H=1LH=1EH H5H=H !H5H=DBLH=1IDDD$DD$Et`A@Dd$ E1HDDl$EHl$HHDDe1EHH=DE1H9uEDd$ Dl$Hl$DH=1$H UH5H=xH5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H= H=AWfAVAUIATUSHxHT$|H$D$|)$= I  IAI\$|ItBHY I$AE-e HHcH>@H I$tH H5H=f.D$ E1E1DA}@ HHcH>@AEL-6 E1HD$(HD$HD$0HD$hHD$HD$`HD$XHD$PHD$HHD$@HD$8AuHLD$:LD$LLHIHtLIA|$$HAu@AIUHSAELIPD$PHD$PHH HD$(D$H$HD$8H$HD$@H$HD$HH$HD$PH$HD$XH$HD$`H$D$ $HD$H$HD$hH$GH$HHPS NAE11M$HD${L$HD$DHN,D${GLEOLLA AAADD$ H|$8HD$0H AOB|-A;|${IE~"Au1H)@A  HHH9uID9c Hc6fDA}LqAAEL-vH H5H=D$ E1E1D$ hE1E1pD$ LE1L@D$ E1E10D$ E1E1D$ E1E1D$ E1E1D$ 0A($E1DA}LH H5H=A}LH H5H=LD$A}LHD$(A}@HALD$HD$HHD$0HHD$hHHD$HHD$`HHD$XHHD$PHHD$HHHD$@HHD$8?A}LH eH5H=AEL-tH H5H=A}L\H H5H=H H5H=fH$HHH=1EE1K H-~LL,$MELd$DH1HDJH5H=H=H=@H%AHHLLIcL>@DHH H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=DH%AHHLLIcL>@DHH H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=DtÐHHHcH>HH %H5H=H !H5H=H 1H5H=H /H5H=H )H5H=H -H5H=H +H5H=H 'H5H=H 3H5H=DH%AHHH HcH>DHH UH5H=H LH5H=H RH5H=H OH5H=H IH5H=H FH5H=H @H5H=H XH5H=H [H5H=D[HHcH>HHHHHHHHHHHHHHHHHHHHHPH=ff. HHcH>@HHHHHHHHHHHHt'HtHHHDDAVAUATUSHHcH>fHH H HHHcHDDH tmH t^HctGHu8@HH@HE@HHHD[]A\A]A^=L%[H]A\A]A^@=L%L[H]A\A]A^@=L%[H]A\A]A^@=H-H\=H-|H<=H-t[H]A\A]A^ÉHH1?H5HtHH5H1HH5H1AIH-L5Lm= 0vcon->iropt_verbosity >= 0vcon->iropt_level >= 0vcon->iropt_level <= 2vcon->guest_max_insns >= 1vcon->guest_max_insns <= 100vcon->guest_chase_thresh >= 0udiv32(100, 7) == 14sdiv32(100, 7) == 14sdiv32(-100, 7) == -14sdiv32(100, -7) == -14sdiv32(-100, -7) == 14vex_initdonevta->needs_self_check != NULLvta->disp_cp_xindir != NULLvta->disp_cp_xindir == NULLGuestBytes %lx %u %02x %08x initial IR irsb->offsIP >= 16%3d %02x vta->addProfIncres->offs_profInc == -1out_used >= 0noneUnmasking SSE FP exceptionsUnmasking x87 FP exceptionsVexArch???INVALIDAMD64ARMARM64PPC32PPC64S390XMIPS32MIPS64X86VexEndness???BigEndianLittleEndian11LibVEX_PatchProfIncLibVEX_evCheckSzBLibVEX_UnChainLibVEX_Chainlibvex_BackEnd@ldispeimmgiedfpfgxstfleetf2 etf3@stckffpextlscpfpos390xneonvfpARM@FXGX vmxDFPISA2_07@ISA3_0ppc64-int-fltfltvmxFXGXVXDFPISA2_07 ISA3_0ppc32-int@cx16lzcntrdtscp sse3ssse3avxavx2bmi@f16c rdrandamd64mmxextsse1sse2sse3 lzcntx86arch_word_sizeLibVEX_FrontEndLibVEX_InitSupport for SSSE3 requires SSE3 capabilities Support for AVX requires SSSE3 capabilities Support for AVX2 requires AVX capabilities Support for BMI requires AVX capabilities Missing floating point capability DFP requires VMX and FX and GX capabilities VX requires VMX and FX and GX capabilities ISA2_07 requires VMX and FX and GX capabilities ISA 3.0 not supported in 32-bit mode ISA2_07 requires VX capabilities ISA2_07 requires DFP capabilities ISA3_0 requires ISA2_07 capabilities ISA3_0 requires VMX and FX and GX capabilities NEON instructions are not supported for ARMv5. NEON instructions are not supported for ARMv6. NEON and VFP3 are required for ARMv8. ARM architecture level is not supported. Unsupported hardware capabilities. Host does not have long displacement facility. Fatal: unknown arch in arch_word_size vcon->iropt_unroll_thresh >= 0vcon->iropt_unroll_thresh <= 400vcon->guest_chase_thresh < vcon->guest_max_insnsvcon->guest_chase_cond == True || vcon->guest_chase_cond == Falsevcon->regalloc_version == 2 || vcon->regalloc_version == 3vta->disp_cp_xassisted != NULLvta->disp_cp_chain_me_to_fastEP != NULLvta->disp_cp_chain_me_to_fastEP == NULLvta->archinfo_guest.endness == VexEndnessLE0 == sizeof(VexGuestX86State) % LibVEX_GUEST_STATE_ALIGNvta->archinfo_guest.endness == VexEndnessBEvta->archinfo_guest.endness == VexEndnessBE || vta->archinfo_guest.endness == VexEndnessLEvta->archinfo_guest.endness == VexEndnessLE || vta->archinfo_guest.endness == VexEndnessBELibVEX_Translate: unsupported guest insn setvta->archinfo_guest.hwcaps == vta->archinfo_host.hwcapsvta->archinfo_guest.endness == vta->archinfo_host.endness ------------------------ Front end ------------------------ *pxControl >= VexRegUpdSpAtMemAccess && *pxControl <= VexRegUpdAllregsAtEachInsnvta->guest_extents->n_used >= 1 && vta->guest_extents->n_used <= 3vta->guest_extents->base[0] == vta->guest_bytes_addrvta->guest_extents->len[i] < 10000can't show code due to extents > 1 ------------------------ After pre-instr IR optimisation ------------------------ ------------------------ After instrumentation ------------------------ after post-instrumentation cleanup ------------------------ After post-instr IR optimisation ------------------------ LibVEX_Codegen: unsupported guest insn setvta->archinfo_host.endness == VexEndnessLEvta->archinfo_host.endness == VexEndnessBEvta->archinfo_host.endness == VexEndnessBE || vta->archinfo_host.endness == VexEndnessLEvta->archinfo_host.endness == VexEndnessLE || vta->archinfo_host.endness == VexEndnessBELibVEX_Translate: unsupported host insn set ------------------------ After tree-building ------------------------ ------------------------ Instruction selection ------------------------ ------------------------ Register-allocated code ------------------------ ------------------------ Assembly ------------------------ VexExpansionRatio %d %d %d :10 Encountered an instruction that requires the vector facility. That facility is not available on this hostSelection of non-80-bit x87 FP precisionSetting %mxcsr.fz (SSE flush-underflows-to-zero mode)Setting %mxcsr.daz (SSE treat-denormals-as-zero mode)Setting %eflags.ac (setting noted but ignored)Unmasking PPC32/64 FP exceptionsPPC64 function redirection stack overflowPPC64 function redirection stack underflowThe specified rounding mode cannot be supported. That feature requires the floating point extension facility which is not available on this host. Continuing using the rounding mode from FPC. Results may differ!The specified rounding mode is invalid. Continuing using 'round to nearest'. Results may differ!Instruction stfle is not supported on this hostInstruction stckf is not supported on this hostInstruction ecag is not supported on this hostInstruction pfpo is not supported on this hostDFP instructions are not supported on this hostEncountered an instruction that requires the floating point extension facility. That facility is not available on this hostThe rounding mode in GPR 0 for the PFPO instruction is invalidThe function code in GPR 0 for the PFPO instruction is invalidLibVEX_EmNote_string: unknown warningGNUzRx 00BHB B(A0D8D@ zRx @( J D  F 3AAMHEB HE K ( FBB B(A0A8D<ZEEENGBAEDIEGGGPZHAXZKAc 8D0A(B BBBD x FFB E(A0A8GLVFN7GGGU 8A0A(B BBBE X[Nq E t[Nq E [Zi A [Nq E ui;LBB A(A0+ (A BBBD U (H BBBE U (H BBBE U (H BBBE Q (H BBBA zRx 0(PEJ2ElS!E+ [5`W?-ISX`@r<@x0`H  ` !.; 3QkP ~0  x h P'0AY_ed0iTns x@}w<  P  0        HR ! ' 0- 3 9 ? E `K `QgWx]cziou{N  0   Pcx  0  B     H # H) / 5 @ ;MA G pM S Y _3e9k q w p}  `   (   b  li h    H Or   0   p @  ' . 5 < C 8J Q X _ f H m  t{  p  p(!D:,    ):AL\` Hv  %4=O^ ,<IUbu0&[ '[  ([' 8 P*[L _ +ut 0- -; 0. 3P 42 sdiv32invalid_hwcapsbuf.14274buf.14288buf.14320buf.14260buf.14246buf.14302prefix.14297hwcaps_list.14301prefix.14241hwcaps_list.14245prefix.14255hwcaps_list.14259prefix.14315hwcaps_list.14319prefix.14283hwcaps_list.14287prefix.14269hwcaps_list.14273invalid_hwcaps.coldcheck_hwcapsextras.14356arch_word_size.part.0__PRETTY_FUNCTION__.14237udiv32.constprop.0__PRETTY_FUNCTION__.13918__PRETTY_FUNCTION__.13944__PRETTY_FUNCTION__.14044__PRETTY_FUNCTION__.14107__PRETTY_FUNCTION__.14125cached.14138__PRETTY_FUNCTION__.14140__PRETTY_FUNCTION__.14158LibVEX_ppVexHwCaps.cold.LC12.LC6.LC3.LC5.LC2.LC1.LC4.LC13.LC11.LC0.LC20.LC18.LC16.LC14.LC15.LC19.LC10.LC9.LC8.LC7.LC17.LC42.LC26.LC36.LC33.LC41.LC31.LC37.LC38.LC22.LC32.LC34.LC30.LC43.LC39.LC29.LC24.LC23.LC40.LC28.LC27.LC25.LC44.LC45.LC46.LC53.LC47.LC48.LC49.LC50.LC51.LC52.LC62.LC54.LC55.LC56.LC57.LC58.LC59.LC60.LC61.LC63.LC64.LC65.LC66.LC73.LC86.LC75.LC70.LC82.LC91.LC95.LC67.LC68.LC69.LC87.LC72.LC71.LC83.LC84.LC85.LC96.LC93.LC94.LC92.LC80.LC81.LC88.LC89.LC90.LC74.LC78.LC76.LC77.LC79.LC101.LC98.LC100.LC99.LC107.LC106.LC108.LC110.LC109.LC104.LC103.LC114.LC105.LC111.LC112.LC113.LC102.LC97.LC134.LC133.LC132.LC131.LC130.LC129.LC128.LC127.LC126.LC125.LC124.LC123.LC122.LC121.LC120.LC119.LC118.LC117.LC135.LC116.LC115.LC136.LC147.LC138.LC146.LC139.LC144.LC145.LC140.LC141.LC142.LC143.LC137.LC150.LC149.LC148_GLOBAL_OFFSET_TABLE_vfatalvex_sprintfs390_host_hwcapsvpanicvex_printfvex_assert_failLibVEX_default_VexControlvex_bzeroLibVEX_Initvex_initdonevex_failure_exitvex_log_bytesvex_debuglevelvex_controlvexSetAllocModeLibVEX_FrontEndvexSetAllocModeTEMP_and_clearvexAllocSanityCheckvex_traceflagsbb_to_IRamd64guest_layoutdisInstr_AMD64guest_amd64_state_requires_precise_mem_exnsguest_amd64_spechelpersanityCheckIRSBdo_iropt_BBdo_deadcode_BBcprop_BBppIRSBLibVEX_Translateado_treebuild_BBdoRegisterAllocation_v2getRRegUniverse_AMD64emit_AMD64InstriselSB_AMD64ppHRegAMD64ppAMD64InstrdirectReload_AMD64genMove_AMD64genReload_AMD64genSpill_AMD64mapRegs_AMD64InstrgetRegUsage_AMD64InstrdoRegisterAllocation_v3LibVEX_ChainLibVEX_UnChainunchainXDirect_AMD64LibVEX_evCheckSzBevCheckSzB_AMD64LibVEX_PatchProfIncpatchProfInc_AMD64LibVEX_EmNote_stringLibVEX_ppVexArchLibVEX_ppVexEndnessLibVEX_ppVexHwCapsLibVEX_default_VexArchInfoLibVEX_default_VexAbiInfos390x_vec_op_t3X(j)|*+,-)*-,./-041F2MS[hpx[\\{||T39L@4JSZ5dkr4645<4"43,?5FKZ45\45 #4Rh7o4y89:;<@4& c==[>?@"0ABCD+EFFGH7 I< C JT Ke Kv L M N H @ O P O Q R '  3 S: T? n         , S U# 3 ,? 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""F"Q"d"k""""z"%#z*#0#H#i##z##z#######z##$$S$p$#$/$S6$r;$Q$V$\$$$$$$S$$$$S%l %%%S&%+%3%?%SF%K%S%_%Sf%k%s%%S%t%%%S%%%%S%%%%S%%%&S &T&&&#&(&V&w&t&S&T&&t&S&T&&t&S&T&&t&S&T&&t&S'T ''t'S%'T*'1't='SD'TI'P't\'Sc'Th'o't{'S'T'''d'S'T''d(S (T((d!(S((T-(4(d@(SG(TL(S(d_(Sf(Tk(r(d~(S(T((d(S(T((d(S(T((d(S(T(()@%)+)7)LC)SJ)TO)V)Lb)Si)Tn)u)L)S)T))L)S)T))L)S)T))L)S)T))L)S*T **L*S#*T(*/*L;*SB*TG*s*d*,*S*T**,*S*T**,*S*T**,+S+T ++,+S&+T++2+,>+SE+TJ+Q+,]+Sd+Ti+p+,|+S+T++,+S+T+++++,,#,3,C,S,c,s,,,,,,,,,---!-F-[-c-s----------..".N.w.(.).*.+.,.-.)/*/-(/,=/.D//]/0d/1z//////////[/\0\00'020{:0|D0|X0Td03i00L0400050004 11"15,1A1@M1411,15111412 252%2\,24a2u2|252224227242 38,39E3:L3;c3<j34t3363@34334, p&'*G.< h/ 4a_ $(,x04P8<8@TDHLPTX\`dhlptx | @D,@ 0Tx, ! Plx.'l&'& &&&&m' ($'(w(,\(0A(4&(8 (<'@(DS)H()L<)P*T)X)\)`)d)hN+l*p7+t+x+|***+-,,,,,,,,,,|,p,d,X,L,@,4,(,,`-`-\---------0 /80d/// /$|.(/ 4 P `  ,\0&x'(P*+0-- 0.34.symtab.strtab.shstrtab.rela.text.data.bss.rodata.str1.1.rela.text.unlikely.rela.rodata.rodata.str1.8.note.GNU-stack.note.gnu.property.rela.eh_frame @B4@uK&4,4 124QE8@@`0Y9< T@ a2@>pOO O@ S k /71 0 0 0 644 17744 ` ELF>@@@USt H1LcIHE1H1DHIA0SHHL9sIcH@tQ-DHcAHAACHT AA<9~DAIL9uHc1 4@4H H9}[]fHJfDHHP@8HfDHcHJ @ tgHc@<~LH1=HtfDH<0uH=HHc ff.D1?tDH<uDff.@1f. u fDH8t1ff.f@t(Hu@HHH@uHHHFHHDfDHGGGH9uH tHJHH|HH9uHtHHH9uDHHHwfATIHHt$(HT$0HL$8LD$@LL$Ht7)D$P)L$`)T$p)$)$)$)$)$H$LHT$D$HD$HD$ H=sD$ 0HD$Hc5Aą~ H=HDA\HH5H=1H5HHH=H)1PX1IHH=ff.@HHSH9L L9$H LL9LL9LH=I9&H5H96tTBM9zL9)@AH[fDI9OL9tH hH5H=H bH5H=fH `H5H=H aH5H=H cH5H=H dH5H=H eH5H=H uH5H=H xH5H=H lH5H=H gH5H=H mH5H=H zH5H=H {H5H=H |H5H=H pH5H=fHH+HHHHSuZHHt_H[HHHHHuIHHuH[HHHHHH H5H=H H5H=@AWAVAUATUSHHT$HHE1IA>@tI^@%t-IAA>@uDHĨ[]A\A]A^A_fDAFE1<-uAFI^AD$ <0u D$0CH<*Ht$/ƒHVD"ECHHL$/SƒHQHHD$HYtHL$1DH<uIcH9rA)EE~Dt$EDAuEHD$E1:kHL$@/ƒHQH2Lt$0E1 LD$01ҐHA<uIcH9sAEE~,Dt$Ef.DAuE|$7|$A'H|$HD$@fHt$HNHAHF1EE@E^E EGEusE4EaH H5H=0AտxD$0|$AEDt$EfDDAuE1fDPX1HHH=ff.@HHUH-H9tHH-H9H5HDH=1LH1HH H=MHI)H=ff.HHHHH;=sH=PPXHIHt$(HT$0HL$8LD$@LL$Ht7)D$P)L$`)T$p)$)$)$)$)$H$LHT$D$HD$HD$ H=SD$ 0HD$Hc5~ H=H=1@SHHHT$0HL$8LD$@LL$Ht7)D$P)L$`)T$p)$)$)$)$)$H$HT$HHD$H=bHD$ D$D$ 0HD$HHJ1Ҁ;H tH<uHcH9uH[DH uH5H=GG  @WHWHH GHH HHGH HH 7fH7vex storage: T total %lld bytes allocated vex storage: P total %lld bytes allocated vex: %s:%d (%s): Assertion `%s' failed. temporary_first <= temporary_currtemporary_curr <= temporary_lastpermanent_first <= permanent_currpermanent_curr <= permanent_lastprivate_LibVEX_alloc_first <= private_LibVEX_alloc_currprivate_LibVEX_alloc_curr <= private_LibVEX_alloc_lastprivate_LibVEX_alloc_first == temporary_firstprivate_LibVEX_alloc_last == temporary_lastprivate_LibVEX_alloc_first == permanent_firstprivate_LibVEX_alloc_last == permanent_lastIS_WORD_ALIGNED(temporary_curr)IS_WORD_ALIGNED(permanent_curr)IS_WORD_ALIGNED(private_LibVEX_alloc_first)IS_WORD_ALIGNED(private_LibVEX_alloc_curr)IS_WORD_ALIGNED(private_LibVEX_alloc_last+1) vex: the `impossible' happened: %s VEX temporary storage exhausted. Pool = %s, start %p curr %p end %p (size %lld) VEX temporary storage exhausted. Increase N_{TEMPORARY,PERMANENT}_BYTES and recompile.priv/main_util.c0(null)fwidth >= 0is_sizet == False???TEMPPERMCannot continue. Good-bye vex_strlen(buf) == retvex_sprintfvprintf_wrkvexSetAllocModevexAllocSanityCheckGNUzRx $AD AC DXx@p !3 FJE@H`!EAIS G 8= LE l j d HpBBB B(A0A8GN 8A0A(B BBBG !EAIS-hEAG EJ AF DX9l #2FH UZpf + ' (+@KL   0!`&+16;@E0JhO`U[ag0msy&0<8AXFb    !3 @+!;L@` {  0=p !P- 59NPg`convert_intadd_to_vg_sprintf_bufvg_sprintf_ptradd_to_myprintf_bufn_myprintf_bufmodevprintf_wrktemporary_bytes_allocd_TOTpermanent_currpermanenttemporary_currtemporary__PRETTY_FUNCTION__.3581__PRETTY_FUNCTION__.3585__PRETTY_FUNCTION__.3686__PRETTY_FUNCTION__.3804.LC0.LC1.LC2.LC3.LC11.LC6.LC4.LC5.LC7.LC8.LC9.LC15.LC16.LC12.LC10.LC13.LC17.LC18.LC19.LC14.LC21.LC20.LC22.LC23.LC25.LC24.LC26.LC27.LC28.LC29.LC30.LC31vex_log_bytesvexGetAllocModevex_strlenvex_streqvex_bzerovex_printfLibVEX_ShowAllocStatsvex_assert_failvex_failure_exitvexAllocSanityCheckprivate_LibVEX_alloc_firstprivate_LibVEX_alloc_currprivate_LibVEX_alloc_lastvexSetAllocModeTEMP_and_clearvexSetAllocModevpanicprivate_LibVEX_alloc_OOMLibVEX_Allocvfatalvex_sprintfread_misaligned_UInt_LEread_misaligned_ULong_LEwrite_misaligned_UInt_LEwrite_misaligned_ULong_LE,4<MU\<+A "'A-DGN$+_cvLov +FGH)5<ACKW^cCsCCCC C&!+C3?F"KCS_f#kCs$C%C&C'C( C%)*C7G>FDO+V$+]dGxE~GE FG+HGE$+ FG"cvL)H1=D)ICP\c)hC| HT[*`C+,C2-7A=DWF^$+f.r y/01AHFG2A3KGHG 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ppIRType%d:I10x%x:I80x%x:I160x%x:I320x%llx:I64F32{0x%x}F32i{0x%x}F64{0x%llx}F64i{0x%llx}V128{0x%04x}V256{0x%08x}ppIRConst%s[rp=%d][mcx=0x%x]{%p}(%d:%dx)IRTemp_INVALIDt%uNotAddMulOrAndXorShlShrSarCmpEQCmpNECasCmpEQCasCmpNEExpCmpNESub8Uto168Uto3216Uto328Sto168Sto3216Sto3232Sto6432Uto6432to816Uto6416Sto648Uto648Sto6464to1664to8Not132to164to11Uto81Uto321Uto641Sto81Sto161Sto321Sto64MullS8MullS16MullS32MullS64MullU8MullU16MullU32MullU64Clz64Clz32Ctz64Ctz32ClzNat64ClzNat32CtzNat64CtzNat32PopCount64PopCount32CmpLT32SCmpLE32SCmpLT32UCmpLE32UCmpLT64SCmpLE64SCmpLT64UCmpLE64UCmpNEZ8CmpNEZ16CmpNEZ32CmpNEZ64CmpwNEZ32CmpwNEZ64Left8Left16Left32Left64Max32UCmpORD32UCmpORD32SCmpORD64UCmpORD64SDivU32DivS32DivU64DivS64DivU64EDivS64EDivU32EDivS32EDivModU64to32DivModS64to32DivModU32to32DivModS32to32DivModU128to64DivModS128to64DivModS64to64DivModU64to6416HIto816to88HLto1632HIto1632to1616HLto3264HIto3264to3232HLto64128HIto64128to6464HLto128CmpF32F32toI32SF32toI64SI32StoF32I64StoF32AddF64SubF64MulF64DivF64AddF64r32SubF64r32MulF64r32DivF64r32AddF32SubF32MulF32DivF32AddF128SubF128MulF128DivF128TruncF128toI64STruncF128toI32STruncF128toI64UTruncF128toI32UMAddF128MSubF128NegMAddF128NegMSubF128AbsF128NegF128SqrtF128CmpF128F64HLtoF128F128HItoF64F128LOtoF64I32StoF128I64StoF128I32UtoF128I64UtoF128F128toI32SF128toI64SF128toI32UF128toI64UF32toF128F64toF128F128toF64F128toF32F128toI128RndF128s390_MAddF32s390_MSubF32ScaleF64AtanF64Yl2xF64Yl2xp1F64PRemF64PRemC3210F64PRem1F64PRem1C3210F64NegF64AbsF64NegF32AbsF32SqrtF64SqrtF32SinF64CosF64TanF642xm1F64MAddF64MSubF64MAddF64r32MSubF64r32RSqrtEst5GoodF64RoundF64toF64_NEARESTRoundF64toF64_NegINFRoundF64toF64_PosINFRoundF64toF64_ZEROTruncF64asF32RecpExpF64RecpExpF32MaxNumF64MinNumF64MaxNumF32MinNumF32F16toF64F64toF16F16toF32F32toF16QAdd32SQSub32SAdd16x2Sub16x2QAdd16Sx2QAdd16Ux2QSub16Sx2QSub16Ux2HAdd16Ux2HAdd16Sx2HSub16Ux2HSub16Sx2Add8x4Sub8x4QAdd8Sx4QAdd8Ux4QSub8Sx4QSub8Ux4HAdd8Ux4HAdd8Sx4HSub8Ux4HSub8Sx4Sad8Ux4CmpNEZ16x2CmpNEZ8x4Reverse8sIn32_x1CmpF64F64toI16SF64toI32SF64toI64SF64toI64UF32toI32UF32toI64UF64toI32UI32StoF64I64StoF64I64UtoF64I32UtoF32I64UtoF32I32UtoF64F32toF64F64toF32RoundF128toIntRoundF64toIntRoundF32toIntRoundF64toF32ReinterpF64asI64ReinterpI64asF64ReinterpF32asI32ReinterpI32asF32I32UtoF32x4_DEPI32StoF32x4_DEPI32StoF32x4F32toI32Sx4F32toF16x4_DEPF32toF16x4F16toF32x4F16toF64x2F64toF16x2_DEPRSqrtEst32Fx4RSqrtEst32Ux4RSqrtEst32Fx2RSqrtEst32Ux2QF32toI32Ux4_RZQF32toI32Sx4_RZF32toI32Ux4_RZF32toI32Sx4_RZI32UtoF32x2_DEPI32StoF32x2_DEPF32toI32Ux2_RZF32toI32Sx2_RZRoundF32x4_RMRoundF32x4_RPRoundF32x4_RNRoundF32x4_RZAbs8x8Abs16x4Abs32x2Add8x8Add16x4Add32x2QAdd8Ux8QAdd16Ux4QAdd32Ux2QAdd64Ux1QAdd8Sx8QAdd16Sx4QAdd32Sx2QAdd64Sx1PwAdd8x8PwAdd16x4PwAdd32x2PwAdd32Fx2PwAddL8Ux8PwAddL16Ux4PwAddL32Ux2PwAddL8Sx8PwAddL16Sx4PwAddL32Sx2Sub8x8Sub16x4Sub32x2QSub8Ux8QSub16Ux4QSub32Ux2QSub64Ux1QSub8Sx8QSub16Sx4QSub32Sx2QSub64Sx1Mul8x8Mul16x4Mul32x2Mul32Fx2PolynomialMul8x8MulHi16Ux4MulHi16Sx4QDMulHi16Sx4QDMulHi32Sx2QRDMulHi16Sx4QRDMulHi32Sx2QDMull16Sx4QDMull32Sx2Avg8Ux8Avg16Ux4Max8Sx8Max16Sx4Max32Sx2Max8Ux8Max16Ux4Max32Ux2Min8Sx8Min16Sx4Min32Sx2Min8Ux8Min16Ux4Min32Ux2PwMax8Sx8PwMax16Sx4PwMax32Sx2PwMax8Ux8PwMax16Ux4PwMax32Ux2PwMin8Sx8PwMin16Sx4PwMin32Sx2PwMin8Ux8PwMin16Ux4PwMin32Ux2CmpEQ8x8CmpEQ16x4CmpEQ32x2CmpGT8Ux8CmpGT16Ux4CmpGT32Ux2CmpGT8Sx8CmpGT16Sx4CmpGT32Sx2Cnt8x8Clz8x8Clz16x4Clz32x2Cls8x8Cls16x4Cls32x2ShlN8x8ShlN16x4ShlN32x2ShrN8x8ShrN16x4ShrN32x2SarN8x8SarN16x4SarN32x2QNarrowBin16Sto8Ux8QNarrowBin16Sto8Sx8QNarrowBin32Sto16Sx4QNarrowBin64Sto32Sx4QNarrowBin64Uto32Ux4NarrowBin16to8x8NarrowBin32to16x4NarrowBin64to32x4InterleaveHI8x8InterleaveHI16x4InterleaveHI32x2InterleaveLO8x8InterleaveLO16x4InterleaveLO32x2CatOddLanes8x8CatOddLanes16x4CatEvenLanes8x8CatEvenLanes16x4InterleaveOddLanes8x8InterleaveOddLanes16x4InterleaveEvenLanes8x8InterleaveEvenLanes16x4Shl8x8Shl16x4Shl32x2Shr8x8Shr16x4Shr32x2QShl8x8QShl16x4QShl32x2QShl64x1QSal8x8QSal16x4QSal32x2QSal64x1QShlNsatUU8x8QShlNsatUU16x4QShlNsatUU32x2QShlNsatUU64x1QShlNsatSU8x8QShlNsatSU16x4QShlNsatSU32x2QShlNsatSU64x1QShlNsatSS8x8QShlNsatSS16x4QShlNsatSS32x2QShlNsatSS64x1Sar8x8Sar16x4Sar32x2Sal8x8Sal16x4Sal32x2Sal64x1Perm8x8PermOrZero8x8Reverse8sIn16_x4Reverse8sIn32_x2Reverse16sIn32_x2Reverse8sIn64_x1Reverse16sIn64_x1Reverse32sIn64_x1Abs32Fx2GetMSBs8x8GetMSBs8x16CmpNEZ32x2CmpNEZ16x4CmpNEZ8x8Add32Fx4Add32Fx2Add32F0x4Add64Fx2Add64F0x2Div32Fx4Div32F0x4Div64Fx2Div64F0x2Max32Fx8Max32Fx4Max32Fx2PwMax32Fx4PwMax32Fx2Max32F0x4Max64Fx4Max64Fx2Max64F0x2Min32Fx8Min32Fx4Min32Fx2PwMin32Fx4PwMin32Fx2Min32F0x4Min64Fx4Min64Fx2Min64F0x2Mul32Fx4Mul32F0x4Mul64Fx2Mul64F0x2RecipEst32Ux2RecipEst32Fx2RecipEst32Fx4RecipEst32Fx8RecipEst32Ux4RecipEst32F0x4RecipStep32Fx2RecipStep32Fx4RecipEst64Fx2RecipStep64Fx2Abs32Fx4Abs64Fx2RSqrtStep32Fx4RSqrtStep64Fx2RSqrtStep32Fx2RSqrtEst64Fx2RSqrtEst32F0x4RSqrtEst32Fx8Sqrt32Fx4Sqrt32F0x4Sqrt64Fx2Sqrt64F0x2Sqrt32Fx8Sqrt64Fx4Scale2_32Fx4Scale2_64Fx2Log2_32Fx4Log2_64Fx2Sub32Fx4Sub32Fx2Sub32F0x4Sub64Fx2Sub64F0x2CmpEQ32Fx4CmpLT32Fx4CmpLE32Fx4CmpGT32Fx4CmpGE32Fx4CmpUN32Fx4CmpEQ64Fx2CmpLT64Fx2CmpLE64Fx2CmpUN64Fx2CmpGT32Fx2CmpEQ32Fx2CmpGE32Fx2CmpEQ32F0x4CmpLT32F0x4CmpLE32F0x4CmpUN32F0x4CmpEQ64F0x2CmpLT64F0x2CmpLE64F0x2CmpUN64F0x2Neg64Fx2Neg32Fx4Neg32Fx2F32x4_2toQ16x8F64x2_2toQ32x4V128to64V128HIto6464HLtoV12864UtoV128SetV128lo64ZeroHI64ofV128ZeroHI96ofV128ZeroHI112ofV128ZeroHI120ofV12832UtoV128V128to32SetV128lo32Dup8x16Dup16x8Dup32x4Dup8x8Dup16x4Dup32x2NotV128AndV128OrV128XorV128CmpNEZ8x16CmpNEZ16x8CmpNEZ32x4CmpNEZ64x2CmpNEZ128x1Abs8x16Abs16x8Abs32x4Abs64x2Add8x16Add16x8Add32x4Add64x2Add128x1QAdd8Ux16QAdd16Ux8QAdd32Ux4QAdd8Sx16QAdd16Sx8QAdd32Sx4QAdd64Ux2QAdd64Sx2QAddExtUSsatSS8x16QAddExtUSsatSS16x8QAddExtUSsatSS32x4QAddExtUSsatSS64x2QAddExtSUsatUU8x16QAddExtSUsatUU16x8QAddExtSUsatUU32x4QAddExtSUsatUU64x2PwAdd8x16PwAdd16x8PwAdd32x4PwAddL8Ux16PwAddL16Ux8PwAddL32Ux4PwAddL64Ux2PwAddL8Sx16PwAddL16Sx8PwAddL32Sx4PwExtUSMulQAdd8x16Sub8x16Sub16x8Sub32x4Sub64x2Sub128x1QSub8Ux16QSub16Ux8QSub32Ux4QSub8Sx16QSub16Sx8QSub32Sx4QSub64Ux2QSub64Sx2Mul8x16Mul16x8Mul32x4Mull8Ux8Mull8Sx8Mull16Ux4Mull16Sx4Mull32Ux2Mull32Sx2PolynomialMul8x16PolynomialMull8x8MulHi8Ux16MulHi16Ux8MulHi32Ux4MulHi8Sx16MulHi16Sx8MulHi32Sx4QDMulHi16Sx8QDMulHi32Sx4QRDMulHi16Sx8QRDMulHi32Sx4MullEven8Ux16MullEven16Ux8MullEven32Ux4MullEven8Sx16MullEven16Sx8MullEven32Sx4PolynomialMulAdd8x16PolynomialMulAdd16x8PolynomialMulAdd32x4PolynomialMulAdd64x2Avg8Ux16Avg16Ux8Avg32Ux4Avg64Ux2Avg8Sx16Avg16Sx8Avg32Sx4Avg64Sx2Max8Sx16Max16Sx8Max32Sx4Max64Sx2Max8Ux16Max16Ux8Max32Ux4Max64Ux2Min8Sx16Min16Sx8Min32Sx4Min64Sx2Min8Ux16Min16Ux8Min32Ux4Min64Ux2CmpEQ8x16CmpEQ16x8CmpEQ32x4CmpEQ64x2CmpGT8Sx16CmpGT16Sx8CmpGT32Sx4CmpGT64Sx2CmpGT8Ux16CmpGT16Ux8CmpGT32Ux4CmpGT64Ux2Cnt8x16Clz8x16Clz16x8Clz32x4Clz64x2Cls8x16Cls16x8Cls32x4Iop_Ctz8x16Iop_Ctz16x8Iop_Ctz32x4Iop_Ctz64x2ShlV128ShrV128SarV128ShlN8x16ShlN16x8ShlN32x4ShlN64x2ShrN8x16ShrN16x8ShrN32x4ShrN64x2SarN8x16SarN16x8SarN32x4SarN64x2Shl8x16Shl16x8Shl32x4Shl64x2QSal8x16QSal16x8QSal32x4QSal64x2QShl8x16QShl16x8QShl32x4QShl64x2QShlNsatSS8x16QShlNsatSS16x8QShlNsatSS32x4QShlNsatSS64x2QShlNsatUU8x16QShlNsatUU16x8QShlNsatUU32x4QShlNsatUU64x2QShlNsatSU8x16QShlNsatSU16x8QShlNsatSU32x4QShlNsatSU64x2Shr8x16Shr16x8Shr32x4Shr64x2Sar8x16Sar16x8Sar32x4Sar64x2Sal8x16Sal16x8Sal32x4Sal64x2Rol8x16Rol16x8Rol32x4Rol64x2QandUQsh8x16QandUQsh16x8QandUQsh32x4QandUQsh64x2QandSQsh8x16QandSQsh16x8QandSQsh32x4QandSQsh64x2QandUQRsh8x16QandUQRsh16x8QandUQRsh32x4QandUQRsh64x2QandSQRsh8x16QandSQRsh16x8QandSQRsh32x4QandSQRsh64x2Sh8Sx16Sh16Sx8Sh32Sx4Sh64Sx2Sh8Ux16Sh16Ux8Sh32Ux4Sh64Ux2Rsh8Sx16Rsh16Sx8Rsh32Sx4Rsh64Sx2Rsh8Ux16Rsh16Ux8Rsh32Ux4Rsh64Ux2QandQShrNnarrow16Uto8Ux8QandQShrNnarrow32Uto16Ux4QandQShrNnarrow64Uto32Ux2QandQSarNnarrow16Sto8Sx8QandQSarNnarrow32Sto16Sx4QandQSarNnarrow64Sto32Sx2QandQSarNnarrow16Sto8Ux8QandQSarNnarrow32Sto16Ux4QandQSarNnarrow64Sto32Ux2QandQRShrNnarrow16Uto8Ux8QandQRShrNnarrow32Uto16Ux4QandQRShrNnarrow64Uto32Ux2QandQRSarNnarrow16Sto8Sx8QandQRSarNnarrow32Sto16Sx4QandQRSarNnarrow64Sto32Sx2QandQRSarNnarrow16Sto8Ux8QandQRSarNnarrow32Sto16Ux4QandQRSarNnarrow64Sto32Ux2NarrowBin16to8x16NarrowBin32to16x8QNarrowBin16Uto8Ux16QNarrowBin32Sto16Ux8QNarrowBin16Sto8Ux16QNarrowBin32Uto16Ux8QNarrowBin16Sto8Sx16QNarrowBin32Sto16Sx8NarrowUn16to8x8NarrowUn32to16x4NarrowUn64to32x2QNarrowUn16Uto8Ux8QNarrowUn32Uto16Ux4QNarrowUn64Uto32Ux2QNarrowUn16Sto8Sx8QNarrowUn32Sto16Sx4QNarrowUn64Sto32Sx2QNarrowUn16Sto8Ux8QNarrowUn32Sto16Ux4QNarrowUn64Sto32Ux2Widen8Uto16x8Widen16Uto32x4Widen32Uto64x2Widen8Sto16x8Widen16Sto32x4Widen32Sto64x2InterleaveHI8x16InterleaveHI16x8InterleaveHI32x4InterleaveHI64x2InterleaveLO8x16InterleaveLO16x8InterleaveLO32x4InterleaveLO64x2CatOddLanes8x16CatOddLanes16x8CatOddLanes32x4CatEvenLanes8x16CatEvenLanes16x8CatEvenLanes32x4InterleaveOddLanes8x16InterleaveOddLanes16x8InterleaveOddLanes32x4InterleaveEvenLanes8x16InterleaveEvenLanes16x8InterleaveEvenLanes32x4InterleavePackOddLanes8x16InterleavePackOddLanes16x8InterleavePackOddLanes32x4InterleavePackEvenLanes8x16InterleavePackEvenLanes16x8InterleavePackEvenLanes32x4GetElem8x16GetElem16x8GetElem32x4GetElem64x2SetElem8x16SetElem16x8SetElem32x4SetElem64x2GetElem8x8GetElem16x4GetElem32x2SetElem8x8SetElem16x4SetElem32x2Slice64SliceV128Perm8x16PermOrZero8x16Perm32x4Perm8x16x2Reverse8sIn16_x8Reverse8sIn32_x4Reverse16sIn32_x4Reverse8sIn64_x2Reverse16sIn64_x2Reverse32sIn64_x2Reverse1sIn8_x16F32ToFixed32Ux4_RZF32ToFixed32Sx4_RZFixed32UToF32x4_RNFixed32SToF32x4_RNF32ToFixed32Ux2_RZF32ToFixed32Sx2_RZFixed32UToF32x2_RNFixed32SToF32x2_RND32toD64D64toD32AddD64SubD64MulD64DivD64ShlD64ShrD64D64toI32SD64toI32UD64toI64SD64toI64UI32StoD64I32UtoD64I64StoD64I64UtoD64I32StoD128I32UtoD128I64StoD128I64UtoD128D64toD128D128toD64D128toI32SD128toI32UD128toI64SD128toI64UF32toD32F32toD64F32toD128F64toD32F64toD64F64toD128F128toD32F128toD64F128toD128D32toF32D32toF64D32toF128D64toF32D64toF64D64toF128D128toF32D128toF64D128toF128AddD128SubD128MulD128DivD128ShlD128ShrD128RoundD64toIntRoundD128toIntQuantizeD64QuantizeD128ExtractExpD64ExtractExpD128ExtractSigD64ExtractSigD128InsertExpD64InsertExpD128CmpD64CmpD128CmpExpD64CmpExpD128D64HLtoD128D128HItoD64D128LOtoD64SignificanceRoundD64SignificanceRoundD128ReinterpI64asD64ReinterpD64asI64V256to64_0V256to64_1V256to64_2V256to64_364x4toV256V256toV128_0V256toV128_1V128HLtoV256DPBtoBCDBCDtoDPBAdd64Fx4Sub64Fx4Mul64Fx4Div64Fx4Add32Fx8Sub32Fx8Mul32Fx8Div32Fx8I32StoF32x8F32toI32Sx8F32toF16x8F16toF32x8AndV256OrV256XorV256NotV256CmpNEZ64x4CmpNEZ32x8CmpNEZ16x16CmpNEZ8x32Add8x32Add16x16Add32x8Add64x4Sub8x32Sub16x16Sub32x8Sub64x4QAdd8Ux32QAdd16Ux16QAdd8Sx32QAdd16Sx16QSub8Ux32QSub16Ux16QSub8Sx32QSub16Sx16Mul16x16Mul32x8MulHi16Ux16MulHi16Sx16Avg8Ux32Avg16Ux16Max8Sx32Max16Sx16Max32Sx8Max8Ux32Max16Ux16Max32Ux8Min8Sx32Min16Sx16Min32Sx8Min8Ux32Min16Ux16Min32Ux8CmpEQ8x32CmpEQ16x16CmpEQ32x8CmpEQ64x4CmpGT8Sx32CmpGT16Sx16CmpGT32Sx8CmpGT64Sx4ShlN16x16ShlN32x8ShlN64x4ShrN16x16ShrN32x8ShrN64x4SarN16x16SarN32x8Perm32x8CipherV128CipherLV128NCipherV128NCipherLV128CipherSV128SHA256SHA512BCDAddBCDSubbcdcfsq.bcdctsq.bitswapdbitswapBitMatrixTranspose64x2ppIROp(1)8163264ppIROp(2)lebeBIND-%dGET:(%d)GETI[,%d](,LD%s:):ITE(VECRETGSPTRppIRExprnoFXRdFXWrFXMoFXppIREffect = DIRTY -mem(,%d) ::: -gst(%u,%u,reps%u,step%u = CAS%s(::->PUTI,%d] = if () { ST%s() = }ILGop_INVALIDIdentV128Ident64Ident32ppIRLoadGOp = if-strict () (LD%s()) else BoringCallReturnClientReqYieldEmWarnEmFailNoDecodeMapFailInvalICacheFlushDCacheNoRedirSigILLSigTRAPSigSEGVSigBUSSigFPESigFPE_IntDivSigFPE_IntOvfSys_syscallSys_int32Sys_int128Sys_int129Sys_int130Sys_int145Sys_int210Sys_sysenterppIRJumpKindFenceCancelReservationppIRMBusEvent!!! IRStmt* which is NULL !!!IR-NoOp====== AbiHint(, %d, ) ======PUT(%d) = ST%s( = LD%s-Linked( = ( ST%s-Cond( )IR-) { PUT(%d) = ; exit- } ppIRStmt :IRSB { PUT(%d) = } IR SANITY CHECK FAILURE IN STATEMENT: ERROR = %s out of range Temp in IRExpruseBeforeDef_Exprpriv/ir_defs.cbit == False || bit == Truename != NULLaddr != 0!(arr->elemTy == Ity_I1)deepCopyIRConstdeepCopyIRExprdeepCopyIRStmttypeOfPrimopenvenv->types_used >= 0env->types_size >= 0tmp < env->types_usedtypeOfIRConsttypeOfIRLoadGOptypeOfIRExpr op name: op type is () -> arg tys are () Iex.Unop: wrong arity opIex.CCall.cee: bad IRCalleeIex.CCall: > 32 argsIex.CCall.arg: arg :: Ity_I1Iex.Const.con: invalid constIex.ITE.cond: cond :: Ity_I1tcExprisFlatIRStmt(e)isFlatIRStmt(st)IRStmt: is NULLIRStmt: is not flatbb->next is not an atomuseBeforeDef_StmtIRStmt.IMark.len: implausibleIRStmt.CAS: ill-formedIst.LLSC(LL).result :: bogusIRStmt.Dirty.dst :: Ity_I1IRStmt.Dirty: > 32 argsIRStmt.Dirty.arg[i] :: Ity_I1IRStmt.Dirty: ill-formedIRStmt.MBE.event: unknownIRStmt.Exit.dst: bad dstIRStmt.Exit.offsIP: too lowtcStmtbb->next field has wrong typebb->offsIP: too loweqIRConstsizeofIRTypeintegerIRTypeOfSizeisIRAtom(a1)isIRAtom(a2)   eqIRAtomsanityCheckIRSBtypeOfIRTempnewIRTempaddStmtToIRSBIRStmt_StoreGIRStmt_StoreIRExpr_LoadmkIRRegArraymkIRCalleeIRConst_U1------ IMark(0x%lx, %u, %u) ------sanityCheckFail: exiting due to bad IRIRTemp use before def in IRExprIRExprP__* value in CCall arg listregparms >= 0 && regparms <= 3!(arr->base < 0 || arr->base > 10000 )!(arr->nElems <= 0 || arr->nElems > 500 )end == Iend_LE || end == Iend_BEbb->stmts_used < bb->stmts_sizeenv->types_used <= env->types_sizetypeOfIRExpr: Binder is not a valid expressiontypeOfIRExpr: VECRET is not a valid expressiontypeOfIRExpr: GSPTR is not a valid expressionIRExpr.GetI.ix: not :: Ity_I32IRExpr.GetI.descr: invalid descrIex.Qop: wrong arity op ... name of op precedes BB printout Iex.Qop: arg tys don't match op tys ... additional details precede BB printout Iex.Triop: wrong arity op ... name of op precedes BB printout Iex.Triop: arg tys don't match op tys ... additional details precede BB printout Iex.Binop: wrong arity op ... name of op precedes BB printout Iex.Binop: arg tys don't match op tys ... additional details precede BB printout Iex.Unop: arg ty doesn't match op tyIex.Load.addr: not :: guest word typeIex.Load.end: bogus endiannessIex.CCall.cee: #regparms > #argsIex.CCall.args: is VECRET/GSPTRIex.CCall.retty: cannot return :: Ity_I1Iex.ITE: iftrue/iffalse mismatchguest_word_size == Ity_I32 || guest_word_size == Ity_I64sanityCheckIRSB: stmts array limits weirdTemp t%d declared with implausible type 0x%x Temp declared with implausible typeIRStmt.Tmp: destination tmp is out of rangeIRStmt.Tmp: destination tmp is assigned more than onceIRStmt.LoadG: destination tmp is out of rangeIRStmt.LoadG: destination tmp is assigned more than onceIRStmt.Dirty: destination tmp is out of rangeIRStmt.Dirty: destination tmp is assigned more than onceIRStmt.CAS: destination tmpHi is out of rangeIRStmt.CAS: destination tmpHi is assigned more than onceIRStmt.CAS: destination tmpLo is out of rangeIRStmt.CAS: destination tmpLo is assigned more than onceIRStmt.LLSC: destination tmp is out of rangeIRStmt.LLSC: destination tmp is assigned more than onceIRStmt.IMark.delta: implausibleIRStmt.AbiHint.base: not :: guest word typeIRStmt.AbiHint.nia: not :: guest word typeIRStmt.Put.data: cannot Put :: Ity_I1IRStmt.PutI.data: cannot PutI :: Ity_I1IRStmt.PutI.data: data ty != elem tyIRStmt.PutI.ix: not :: Ity_I32IRStmt.PutI.descr: invalid descrIRStmt.Put.Tmp: tmp and expr do not matchIRStmt.Store.addr: not :: guest word typeIRStmt.Store.data: cannot Store :: Ity_I1Ist.Store.end: bogus endiannessIRStmtG...addr: not :: guest word typeIRStmtG...data: cannot Store :: Ity_I1IRStmtG...guard: not :: Ity_I1IRStmtG...end: bogus endiannessIRStmt.LoadG.guard: not :: Ity_I1IRStmt.LoadG.addr: not :: guest word typeIRStmt.LoadG: dst/alt type mismatchIRStmt.LoadG: dst/loaded type mismatchIRStmt.LLSC.addr: not :: guest word typeIst.LLSC.end: bogus endiannessIst.LLSC(SC).result: not :: Ity_I1Ist.LLSC(SC).result :: storedata bogusIRStmt.Dirty.guard not :: Ity_I1IRStmt.Dirty.args: > 1 GSPTR argIRStmt.Dirty.args: VECRET present, but fn does not return V128 or V256IRStmt.Dirty.args: VECRET not present, but fn returns V128 or V256IRStmt.Dirty.args: > 1 VECRET presentIRStmt.Dirty.args: GSPTR requested, but no fxState declaredIRStmt.Exit.guard: not :: Ity_I1IRStmt.Exit.dst: not :: guest word typeGNUzRx K/47+L`E~ M hES H .PAJNf E  E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E M E 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LmI|$H4HHuID$LHpmID$LHpmIt$It$LmfIvLTwH$IAFn H$fDfofoZHH )R@)ZPI9uH$H$L‰$L$Ƅ$Ƅ$HDŽ$A~HD$HDA== =dD$[D$ D$4D$=- D$(HT$@$Lt$ML,$IQ@T$(AuS|$t|$[uwHD$= tb=t[IGM9IIwHtAGuAt€|$tAL$ EO9WD9L$ ~t|$[tDIFHcL,A?IE;$5IGIGM9zL,$HL$hML1Hxt#foHcփH)foH)H H9u̓ 8 Hc)HHHHIDIT(fDHH H9uIGH|$HHcH<ЍC$D9H uH5H=HD$HA=fIFH;|$ {|$ T$\D$CtHD$PЋL$|$ D$D$[CDD$4AGI^LHs)tSHsLHD$T$tHL$T$H;HHHD$H3ANEFLIvI^L$DD$sDD$L$HHDHD$HIvLsIvLHsA~HHHD$HI^LHs esHsLHD$TsHsLHD$CsSsLL$LD$H;HD$HgI^LHssHsLHD$rHsLHD$rHL$HT$;HHD$HI^LHs0rHD$HC(HD$HtHLrHD$Hs LrLCIMtLLHD$ trLL$ IHsLLD$(LL$ VrsSt$;t$HLL$0LD$8HHD$X^_hI^HtHL rHIvLqAv A~HHHD$H(I^o#I okhos Axp o{0x0oc@`@okPhPHC`I@`tIp LLD$}qLD$I@ IpLLD$^qLD$IPI@H2HtSLt$ILLl$IfD- vLqHSIEN,2IIuHuLt$Ll$ILHD$H,IvLpIvA^LHD$pHT$HHD$HAVAvI~HD$HIvLpA~HHD$H@9|$49H _H5H=A^IvI?\$ T$\ߍDD$4HD$PD$D$[AD$(== eI^CD$(-Z >DI^HCHHthHfHHHtT: uD$[D$ D$4D$D$(H H5H=K,E11Lt$Ll$(AILd$xMD$4D$ D$L|$p/@D$ D9DND$49D|$ M؉\$4IE9e,IcfA|0tCT7CD6G|2CT4DD\T$\HD$PЄDEA9|$w\$4D|$ D$IvLfHCsI>8D$ADˆD$AAH=-fDIE9~vALDd$E |$" LDIDLHHHHI A~ IF8 H@ DHAvL9L$ lI~HfHVHHt: Az4HRDA = R9 H9T$LL$HT$zÃLINj@* IOLL$HHT$ H L4MtA>  IF0 IO9 t HI9DA> 9  QDHI~HIFCt  D$8t1D$8D$Hl$(Ll$0Dd$fDHHH蕁IAL]L= H{HG=t = .HwHHH- H H5H=HC=t = HCHC=6= +H H5H=@HCHp6t .Hp6@ 4H H5H=DHCHp6t HpH(Hp 6S GH H5H=HCHp6t  Hp6 H H5H=DHC=t = HC== H H5H=DHC=t = 0HC=W= LH H5H=DHC==  H H5H=DHC== H H5H=DD$fDH@== |H H5H=DH@ =G= H5H=H =H5H=H :H5H=H 7H5H=H 4H5H=H=1Lt$LD$LH=1H=H TH5H=priv/ir_opt.ch->used < h->size addUses_ExpraoccCount_ExprdeltaIRExprisIRAtom(ex->Iex.GetI.ix)isIRAtom(qop->arg1)isIRAtom(qop->arg2)isIRAtom(qop->arg3)isIRAtom(qop->arg4)isIRAtom(triop->arg1)isIRAtom(triop->arg2)isIRAtom(triop->arg3)isIRAtom(ex->Iex.Binop.arg1)isIRAtom(ex->Iex.Binop.arg2)isIRAtom(ex->Iex.Unop.arg)isIRAtom(ex->Iex.Load.addr)isIRAtom(args2[i])isIRAtom(ex->Iex.ITE.cond)isIRAtom(ex->Iex.ITE.iftrue)isIRAtom(ex->Iex.ITE.iffalse) subst_ExpratbSubst_Exprflatten_Exprd2->mAddr == NULLflatten_Stmtk_lo <= k_hie_lo <= e_hicollapseChainlow <= highsetHints_Expr(*minoff & ~0xFFFF) == 0(*maxoff & ~0xFFFF) == 0*minoff <= *maxoffisIRAtom(ix1)isIRAtom(ix2)descr1->base == descr2->basegetAliasingRelation: itersc1->tag == c2->tag(minoff & ~0xFFFF) == 0(maxoff & ~0xFFFF) == 0isIRAtom(st->Ist.Put.data)isIRAtom(st->Ist.AbiHint.nia)isIRAtom(st->Ist.Store.addr)isIRAtom(st->Ist.Store.data)isIRAtom(sg->addr)isIRAtom(sg->data)isIRAtom(sg->guard)isIRAtom(lg->addr)isIRAtom(lg->alt)isIRAtom(lg->guard)isIRAtom(st->Ist.Exit.guard)handle_gets_Stmt0do_cse_BB(1)do_cse_BB(2)irExpr_to_TmpOrConsteqTmpOrConsteq_AvailExprn >= 0tmpOrConst_to_IRExpravailExpr_to_IRExprnotBoolisOnesUisZeroUisIRAtom(puti->ix)isIRAtom(puti->data)isIRAtom(cas->addr)isIRAtom(cas->expdLo)isIRAtom(cas->dataLo)isIRAtom(st->Ist.LLSC.addr)isIRAtom(d2->mAddr)isIRAtom(d2->guard)isIRAtom(arg)subst_and_fold_Stmtnop->tag == Ist_NoOplgu->tag == Ist_LoadGcprop_BB: unhandled ILGOpaddUses_Stmtrelation != ExactAliasrelation == ExactAliaspi->tag == Ist_PutIisIRAtom(s2->Ist.Put.data)isIRAtom(p2->ix)isIRAtom(p2->data)isIRAtom(s2->Ist.Store.addr)isIRAtom(s2->Ist.Store.data)aoccCount_Stmtj <= ienv[A_NENV-1].bindee == NULLatbSubst_Stmtj <= i+1isIRAtom(d->guard)isIRAtom(d->mAddr)considerExpensivesst->tag == Ist_Exitudst->tag == Iex_ConstdeltaIRStmti >= 0mkZeroOfPrimopResultType: bad primopmkOnesOfPrimopResultType: bad primopvex iropt: 8 x unrolling (%d sts -> %d sts) vex iropt: 4 x unrolling (%d sts -> %d sts) vex iropt: 2 x unrolling (%d sts -> %d sts) vex iropt: not unrolling (%d sts) descr1->nElems == descr2->nElemsdescr1->elemTy == descr2->elemTybias1 >= 0 && bias1 < descr1->nElemsbias2 >= 0 && bias2 < descr1->nElemspxControl < VexRegUpdAllregsAtEachInsnisIRAtom(st->Ist.PutI.details->ix)isIRAtom(st->Ist.PutI.details->data)isIRAtom(st->Ist.AbiHint.base)cee1->regparms == cee2->regparmscee1->mcx_mask == cee2->mcx_maska1->u.CCall.retty == a2->u.CCall.rettye->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U8e->Iex.ITE.cond->Iex.Const.con->tag == Ico_U1vex iropt: fold_Expr: no ident rule for: vex iropt: fold_Expr: no const rule for: fguard->Iex.Const.con->tag == Ico_U1fguard->Iex.Const.con->Ico.U1 == Truecas->expdHi == NULL || isIRAtom(cas->expdHi)cas->dataHi == NULL || isIRAtom(cas->dataHi)isIRAtom(st->Ist.LLSC.storedata)fcond->Iex.Const.con->tag == Ico_U1fcond->Iex.Const.con->Ico.U1 == Truevex iropt: IRStmt_Exit became unconditional env[(Int)(st2->Ist.WrTmp.tmp)] == NULLguard->Iex.Const.con->tag == Ico_U1guard->Iex.Const.con->Ico.U1 == Truen_fixups >= 0 && n_fixups <= N_FIXUPSix >= 0 && ix+1 < out->stmts_usedi_unconditional_exit >= 0 && i_unconditional_exit < bb->stmts_usedguestAccessWhichMightOverlapPutIcon->tag == Ico_U32 || con->tag == Ico_U64con->tag == udst->Iex.Const.con->tagudst->Iex.Const.con->tag == Ico_U32 || udst->Iex.Const.con->tag == Ico_U64unroll_factor == 2 || unroll_factor == 4 || unroll_factor == 8yw}availExpr_to_IRExpreqIRCalleeeq_AvailExprredundant_get_removal_BBguestAccessWhichMightOverlapPutIidenticalPutIsgetAliasingRelation_IIfindPutImaybe_loop_unroll_BBconsiderExpensivesinvalidateOverlapshandle_gets_StmtaddToHHWgetArrayBoundsmk_key_GetPutredundant_put_removal_BBflatten_Stmtupdate_intervaladdToEnvFrontado_treebuild_BBdo_deadcode_BBsubst_ExprsameIRExprs_aux2fold_Clz64fold_Clz32fold_Exprsubst_and_fold_Stmtcprop_BB1GNUzRx 4BAD  AAH I 8TDI H b H K H K H K H K M K8UBDD @ ABC  ABA 8[BDD @ ABC  ABA 8CBDD { ABH  ABA 4DDj H N H N H N H N H P|1BBB A(D0Q (A BBBE  (D EBBJ 7 (D BBBG d (D BBBJ + (D EBBH g (D EEBI l (D EBBO { (D EEBE K (A BBBN PBBB D(A0i (A BBBE } (A BBBL S (D EBBH B (D BBBL  (A BBBG P (I EBDL v (D MBBM L (D BBBJ j (D EEBN ` nBBB B(D0D8D@I 8D0A(B BBBF } 8A0A(B BBBI X|BBB B(D0A8D@~8A0A(B BBBG@HHPV8O@Dp D B J A E P<?BBE H(D0S (A BBBA 3 (A BBBF 8BEA C(D0P (A ABBK (AAD n CAH H BEB B(D0C8G` 8A0A(B BBBK HDBBB E(A0A8D@ 8D0A(B BBBC 4FAKG0y AAB \ CAH zRx 0 HmBBB B(A0A8DP 8A0A(B BBBH LDpBBB B(A0A8D 8A0A(B BBBA 83%BBB D(D0{ (D BBBE \FBB B(A0A8G{ 8D0A(B BBBA G[Ad0FBB B(A0A8DP 8A0A(B BBBH  8A0A(B BBBG L BBB B(D0A8D 8D0A(B BBBI H}BBB B(A0A8Dp6 8D0A(B BBBG \4^FBB B(A0A8G 8A0A(B BBBA F`AdFEB E(D0D8G 8D0A(B BBBE  8G0G(B BBBE  H #<UI[X@Cd}1  n| p( =?Kd0"X## & 'F' = +mV0oh3p(  I3% H %8 >( W b`{x  `! }(@AZs "/>(gx !J&z,02K8>DdIOU[ag m%syP2@LZs0X 6J!'9-Q39o? EKQW]ciou{h@YfL{HuE Hp$ +/18a?(ELPSxYx`fmt{+?~Zk(8`O;r#f*   1Ke{   ' < H T ` m x              % 3 ; F R _ l x           @n    / 0^@ L Y f addToHHW__PRETTY_FUNCTION__.3627mkZeroOfPrimopResultTypeaddUses_ExpraoccCount_ExprdeltaIRExprmkOnesOfPrimopResultTypesubst_Expr__PRETTY_FUNCTION__.4227atbSubst_Exprflatten_Exprflatten_Stmt__PRETTY_FUNCTION__.3684invalidateOverlaps__PRETTY_FUNCTION__.3730calc_unroll_factor.isra.0collapseChain.isra.0setHints_Expr__PRETTY_FUNCTION__.4944getAliasingRelation_IC.isra.0__PRETTY_FUNCTION__.3708mk_key_GetIPutIgetAliasingRelation_II__PRETTY_FUNCTION__.4451spec_helpers_BBsameIRExprs_aux2num_nodes_visited__PRETTY_FUNCTION__.3872sameIRExprs_aux2.coldredundant_put_removal_BB__PRETTY_FUNCTION__.3786__PRETTY_FUNCTION__.3834__PRETTY_FUNCTION__.3715do_cse_BB.constprop.0__PRETTY_FUNCTION__.4627__PRETTY_FUNCTION__.4604__PRETTY_FUNCTION__.4477fold_Expr__PRETTY_FUNCTION__.4128__PRETTY_FUNCTION__.3976__PRETTY_FUNCTION__.3968CSWTCH.265__PRETTY_FUNCTION__.4248__PRETTY_FUNCTION__.4300__PRETTY_FUNCTION__.4403expensive_transformations__PRETTY_FUNCTION__.4793__PRETTY_FUNCTION__.4773__PRETTY_FUNCTION__.4782cheap_transformations__PRETTY_FUNCTION__.3750__PRETTY_FUNCTION__.5225__PRETTY_FUNCTION__.4991n_total.5437n_expensive.5438__PRETTY_FUNCTION__.5379__PRETTY_FUNCTION__.4917.LC0.LC1.LC2.LC3.LC4.LC5.LC6.LC7.LC20.LC10.LC14.LC17.LC22.LC11.LC23.LC15.LC12.LC8.LC21.LC18.LC19.LC16.LC13.LC9.LC24.LC25.LC26.LC27.LC28.LC29.LC31.LC30.LC35.LC32.LC34.LC33.LC36.LC37.LC38.LC39.LC40.LC41.LC47.LC49.LC42.LC43.LC44.LC45.LC46.LC48.LC50.LC56.LC68.LC64.LC67.LC57.LC55.LC53.LC70.LC54.LC52.LC69.LC59.LC65.LC60.LC58.LC62.LC66.LC63.LC61.LC79.LC80.LC78.LC77.LC81.LC75.LC74.LC72.LC73.LC71.LC76.LC88.LC87.LC85.LC86.LC83.LC84.LC82.LC102.LC107.LC105.LC101.LC93.LC89.LC98.LC95.LC90.LC96.LC110.LC111.LC108.LC94.LC109.LC97.LC112.LC100.LC99.LC113.LC103.LC91.LC104.LC92.LC106.LC114.LC116.LC115.LC125.LC124.LC118.LC119.LC117.LC120.LC123.LC121.LC122.LC130.LC127.LC129.LC128.LC126.LC132.LC133.LC131.LC135.LC134.LC138.LC137.LC136.LC141.LC140.LC139private_LibVEX_alloc_currprivate_LibVEX_alloc_last_GLOBAL_OFFSET_TABLE_vex_assert_failprivate_LibVEX_alloc_OOMIRConst_V256IRExpr_ConstvpanicIRConst_U1IRConst_U64IRConst_U32IRConst_U8IRConst_U16IRConst_V128vex_printfppIRExprppIROpshallowCopyIRExprVecIRExpr_GetIIRExpr_LoadIRExpr_UnopIRExpr_BinopIRExpr_ITEIRExpr_TriopIRExpr_QopIRExpr_CCalltypeOfIRExprnewIRTempIRStmt_WrTmpaddStmtToIRSBIRExpr_RdTmpIRStmt_AbiHintIRStmt_PutmkIRPutIIRStmt_PutIIRStmt_StoreIRStmt_LoadGIRStmt_StoreGmkIRCASIRStmt_CASIRStmt_LLSCemptyIRDirtyIRStmt_DirtyIRStmt_ExitppIRStmtvex_controlsizeofIRTypeeqIRRegArrayeqIRAtomemptyIRSBdeepCopyIRTypeEnvIRStmt_NoOpeqIRConstIRConst_F64icprop_BBIRStmt_MBEtypeOfIRLoadGOpIRStmt_IMarkdo_deadcode_BBado_treebuild_BBdo_iropt_BBtypeOfIRTempdeepCopyIRSBdeepCopyIRExprTD`>g?lx}@%8KcABA$A+2C7MVA]elAszDE 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<$!6(%6,)60;4R:856<9@V8DY7H.>L>P=TSAX>>\->`$Ad=hAlAp=tBx:|DY?;@BC@C@9< DD OKOO%K)KPP5K9K=KAKPPPPPPPPKKKKuK yKPPKK rQ$P(K,K0Q4P8K<K@QDQHKLKP$OTKXK\K`KdKhKlKpKtKxK|KKKKKKLL L LLLLL!L%L)L-L1L5L9L=LALELILMLQLULYL]LaLeLiLmLqLuL yL}LLLL L$L(g ag 3g g  b b b b b f g g |h h wh  b b b b b 8h h h h jh h$  b( b, b0 b4 b8 h< h@ iD 8iH (iL 6iP  bT bX b\ b` bd Dih Otl vp 0st Mxx *w| w s u t nr q .o uw W ( C  K  Ƃ  m A      0 ,  |  ߉  L  , X B ޔ #  t  j E$ )( ӕ, =0 x4 8 < @ >D H ϟL /P gT X \ ț`  d %h  l p t x |  ԡ X  0  إ | H d 0 4 r ] Ҭ a @  8 ݪ   ` ݬ( X @HT $p  @0"##H&' +H3I@n480.symtab.strtab.shstrtab.rela.text.data.bss.rodata.str1.1.rodata.str1.8.rela.rodata.rela.text.unlikely.note.GNU-stack.note.gnu.property.rela.eh_frame @)@&i,l 12ly@2T O@ (Saa\@H phh @`  u /235 0 0 0 644 20592 ` ELF>pL@@1fSHHIE11fDHHYIH LYLQH1HHH1HL1IHL1MHML1IwHVHHHHHtH4H HH1IHL1H9uL[HE11fDHHHH1Hff.HHwHH 2H1HH1HH1Hff.HLGHHJ L1HH49H1H1HH1HH1Hf.HHGLGHwH HH1LHHL1HH1HH1HHHGLOLGH HH H1LHLL1H49H1HL1HH1HH1HfDHL_HGLWJ HLO H(L1HHLH1N L1HLI48L1H1HH1HH1HH1HfUSHoHH_L_LW H*HLO(H0H1HHLH1NL1[HK4M1]L1H >H1HH1HL1HH1HH1HUHSHoH_LW H*HLO(LG0H1L_Hw8HHK H1LL[HH]L1HL1HH1HL1HL1HH1HH1Hff.ATUSLgHHoL_ HG(N"HLO0H_L1LG8I4IHLIH@H1LHLM1H1H >H1[H]A\L1HH1HL1HL1HH1HH1HfDAVAUATUSLwHLoHo L_(J2HHG0LgL1LW8NDLHILLO@L1MHHHIH1L1K4M1HH >H1H1[]HA\A]L1A^HH1HL1HL1HH1HH1Hff.AWAVAUATUSLHLwLoHo(N$:HH_0L_8L1MLW@LOPHK,Lg I1HD$II ,L3d$M1HILM1HHGHINL1L1I4L1HJ<L1H1HI1[]IA\A]L1A^A_HH1HH1HH1HAWHAVAUATUSHHLyLqLi L$:HHi(HY0H1MLQ@LIHHMLY8LAPL1LID-HqXHL1K HL1LLHLHH1HL1HH1HH1[]HA\A]L1A^A_HH1HL1HL1HH1HH1Hff.AWAVAUATUSHD5Ht$D$HT$HL$(LD$LL$ EAdA9$0-I$0D$`u$`V $X 1fGH$fWHHD$H$IHD$HD$XHAGD$df.HLuH$@tH|$L$@D$`Dt$hMD$`AHD$0%D$lH$HD$8AĉD$@D$PD$`9D$HHP:A^ Ld$0L$$AoAL1HLH$`$X H$1fOHHD$fw$IHD$HD$XfD1L1LHD\$`E~ |$PdI 1EHLHD$HP$P$@$@$@PATt$hHD$`L$0LD$HH|$xЋ$$H@B  H$JL$xHD$pHt u E>$ Z3A9o)IOHcL$HH 8 DPE $pL$|I A  EO$E IcG9 IOHDH 8 $X9H( AFI FAf=0 D$`fA|$x|$HJ1Ht$pH|$A)ӄ AFfAFf HT$pE1L$`HIfEDF9L$hH+$HT$0@fA~HF$fA~D$HH=1HL%LHM11MHHHLfH7LH LwLGH1LHL1HL1IHL1MHLH1H9uHM׃HHD$@HZ M LH;D$@ Lt$0$0I>$0I>D$h$0D$xH|$HH|$PIILLD$H|$hHƋD$8D4HD$0Dt$dMcHPILHT$(HT$(LD$HHL|$xHHD$0H@JT0HT$(HT$(|$hH$HHHD$0H@JT0HT$(HT$(|$xH$PHHD$0H@JT0HT$(HT$(HH$(xHHHHLHHLIHH|$@HH,HHT$X $XHHD$0H@J\0 L LhHLHD$I@D9,L|$0IX |$lHD$T$`HĸL[]A\A]A^A_DH H5H=fH H5H=H H5H=H H5H=H H5H=H H5H=!L$hND$hH H5H=H|$pZ|$|-T$`9T$hHt$0\H H5H=|$|M$0$XIGD$|AG $XAG$Ht$(H|$L$8AMD$ AfSD$ 1LL:L Ll$L|$0I׋D$ D|$8DHD$HD$BTxT$(Hf|$(zHT$HD$PJIHDHT$HIHI9L)HHHHH=H w^IcL>HL%LMLH11H= 1vex_control.guest_max_insns <= 100vex_control.guest_chase_thresh >= 0vex_control.guest_chase_thresh < vex_control.guest_max_insnsguest_word_type == Ity_I32 || guest_word_type == Ity_I64n_instrs < guest_max_insns_reallyn_cond_resteers_allowed >= 0 && n_cond_resteers_allowed <= 2dres.whatNext == Dis_StopHere || dres.whatNext == Dis_Continue || dres.whatNext == Dis_ResteerU || dres.whatNext == Dis_ResteerCdres.len >= 0 && dres.len <= 24first_stmt_idx >= 0 && first_stmt_idx < irsb->stmts_usedfirst_stmt_idx < irsb->stmts_usedst->Ist.Put.offset == offB_GUEST_IPvge->len[vge->n_used-1] < 5000dres.jk_StopHere == Ijk_INVALIDdres.jk_StopHere != Ijk_INVALIDresteerOKfn(callback_opaque,dres.continueAt)vge->n_used >= 1 && vge->n_used <= 3(extents_needing_check >> vge->n_used) == 0len2check >= 0 && len2check < 2000hWs_to_check > 0 && hWs_to_check < 2004 / host_word_szBexpectedhW == fn_spec( first_hW )priv/guest_generic_bb_to_IR.cszB_GUEST_IP == 4(offB_GUEST_IP % 4) == 0szB_GUEST_IP == 8(offB_GUEST_IP % 8) == 0 irsb->next == NULLdres.continueAt == 0dres.whatNext != Dis_ResteerCdres.hint == Dis_HintVerboseimarkimark->tag == Ist_IMarkimark->Ist.IMark.len == 0 irsb->jumpkind == Ijk_Boringirsb->offsIP == 0stst->tag == Ist_PutresteerOKvge->n_used <= 3first_hW <= last_hWnm_spec!nm_specirsb->next != NULLPUT(%d) = ; exit-genericg_compute_checksum_8albb_to_IRGNUzRx 0E A Pd%x69J^ pEAyK uEDzG(FAA WDB8<FBB A(A0i(A EBE@xFBB B(A0A80A(E BEB@FEB B(A0A80A(E BEBpFBB B(A0A8GEHGGHBDk 8D0A(B BBBF  +K%k6P9J^@p u+0Klp08 t8XP #x). 3H8p=BGLQWe]cIio[u{v0 =OR0@o pPx#)/   5>JYoy*7CS^gu~const_Falsegenericg_compute_checksum_8algenericg_compute_checksum_8al_1genericg_compute_checksum_8al_2genericg_compute_checksum_8al_3genericg_compute_checksum_8al_4genericg_compute_checksum_8al_5genericg_compute_checksum_8al_6genericg_compute_checksum_8al_7genericg_compute_checksum_8al_8genericg_compute_checksum_8al_9genericg_compute_checksum_8al_10genericg_compute_checksum_8al_11genericg_compute_checksum_8al_12n_resteers.3721__PRETTY_FUNCTION__.3731.LC24.LC9.LC10.LC12.LC13.LC14.LC15.LC16.LC17.LC31.LC18.LC28.LC7.LC11.LC8.LC1.LC2.LC3.LC4.LC5.LC6.LC0.LC29.LC45.LC22.LC20.LC23.LC21.LC35.LC25.LC26.LC27.LC19.LC32.LC33.LC34.LC36.LC37.LC38.LC39.LC40.LC41.LC42.LC59.LC55.LC50.LC52.LC30.LC47.LC46.LC49.LC51.LC48.LC44.LC43.LC54.LC53.LC57.LC58.LC56bb_to_IRvex_controlvex_traceflags_GLOBAL_OFFSET_TABLE_emptyIRSBIRConst_U64IRStmt_NoOpaddStmtToIRSBIRStmt_IMarkIRConst_U32vex_printfnewIRTempIRExpr_ConstIRStmt_WrTmpIRExpr_RdTmpIRStmt_PutmkIRExpr_HWordmkIRExprVec_1mkIRExprCCallIRExpr_BinopIRStmt_Exitvex_assert_failIRExpr_GetppIRStmtmkIRExprVec_2ppIRExprppIRJumpKindW SWXZ[\']W^]RZl_^] X   `-  a a [ [' bX cm b c d e d e* f2 gJ hW [_ bo i j   4#k34?FKkS4_fkkr4~k4k4k4kA4MTYk}l !"#-$@%S&f'y()4*k4+k4,k4-k!4-4.9k@4LS/Xk{0`m`41k42k 43"k)45<4AkH4T[5`kg4sz6k47k41k48k49k4:k!4-4;9k@4LS<Xk_4kr=wk~4>kffn?h__4$+@0k74CJAOkV4biBnku4Ck4Dk4Ek4Fk4 Gk4$+H0k74CJIOkV4biJnku4k4Kk4Lk0`M`oN` p` '`34?FOKkal  ;  |$m(^,O0@ 4Th|P@0@|p0.symtab.strtab.shstrtab.rela.text.data.bss.rodata.str1.8.rodata.str1.1.rela.rodata.note.GNU-stack.note.gnu.property.rela.eh_frame @@p1 &,12@2TpAO@@I8 \l p@xJh H" V ,K/282 0 0 0 644 14152 ` ELF>3@@D$AʋL$ЄDL$E{AAEAAAEˉʃAEAAAEWʃAEAAAEWʃAEAAAEщW 1҅‰у@EEщрɀEE % ЉfL$tct@DAAD⍊AL AAD!)ʃGHGfft݉H!DAAD⍊AL AAD!)ʃ GHGf.4DDD14DD$AʋL$\cЄIDL$EAAEAAAEAAAEAAAEˉʃAEAAAEAAAEAAAEWʃAEAAAEAAAEAAAE WʃAEAAAEAAAEAAAEщW 1҅‰у@EEщрɀEE % ЉÐL$tstPDAAF\ D⍊AL AAD!)ʃGHG^ft݉H!ʍDAAF\ D⍊AL AAD!)ʃ GHGf.5fD1DOGAAE A%=<ˆFA DV GWx FGW ЈFGW ЈFGW ЈFGW ЈFG ЈFFf.t{AVDV UHSFGA3D)‰DуA4uں<[])A^A ҈FDV {qg]S?JuCDV HFÐADV tHFHÐHFHAFHDV Hú3A?A)f.A,AADAIAA)AAAD!A EuG WO.WDGAD ˆAWDOAD ʈVWDOAD ʈVWDOAD ʈVWDOAD ʈVWDOAD AVWA EɈFD ʈVG<AADfuSuMuGuAu;u5u/?u*E1FfDNFfD@t=E1ۈFfD^FF1fFFfAFfDVFFE1HD[]A\A]A^A_DEEDAAADL$ Dt$JE1AuEDE1AE D AADAEt31AAAtD2D84wHHuAHAuHDDD$ PD$PD$$PH AE1AEEĻAAAE E AAfE1A)AAEtH9tD4D84 uHHuADAE ADAE>HHu/fDE1AcfDEE18 AHE HuDDHDD D AAE!D1!D$ A1PD$APD$$PaH AfDAAHAE AB~DH H5H=fH H5H=H H5H=EDE1AA۽E D AEDAEt<1AAEA!E9uDD8wD:TvNHHuAHAuHDDD$ PD$PD$$PH AEDAE 뮃~vEDE1AA۽E D ADEDAEp1@AAEA!E9uDD8D:T~HHuAHAu+EDAE fAWHAVAUATUSH(\$hL$`\$ fDEwEEAKwLAOc M>AE1H(D[]A\A]A^A_AAɉAAAADL$\$AZEE1ɃtEDE1ۻAE D AADEAEt61DAAAtF> 16) == 0(zmaskR >> 16) == 0(zmaskL >> 8) == 0(zmaskR >> 8) == 0compute_PCMPxSTRx_widecompute_PCMPxSTRxGNUzRx 08DEH HADW <GlDA u ABA Vr x~FBB B(A0A8DPZ 8D0A(B BBBA XL`EhEpIPXd`IhEpIP+XL`EhEpIPPFEB B(A0A8D`U 8D0A(B BBBA hLpExEI` hIpExEI AhdpIxEI`hFpExEO`#@ Yrw|%9M`  G`  ~compute_PCMPxSTRx_gen_output_widecompute_PCMPxSTRx_gen_output__PRETTY_FUNCTION__.1674__PRETTY_FUNCTION__.1787.LC0.LC1.LC2.LC3.LC4.LC5convert_f64le_to_f80leconvert_f80le_to_f64lex86amd64g_calculate_FXTRACTcompute_PCMPxSTRx_GLOBAL_OFFSET_TABLE_vex_assert_failcompute_PCMPxSTRx_wideq  & +3?FKS_f ks          $ ( , 0 4 8 < @ D H L P T X \ ` d h l p t x |        ! % ) - 1 5 9 = A Z I M Q j Y ] a z i  q u y }           $ ( , 0 4 8 < @ D H L P T X \ ` d h l p t x | "!%)-159=AZIb $#<+D3L;? CGKdS W$[(_,c0|4k8<s@wD{HLPTX\`dhlptx| ,#'+D 4H`  T.symtab.strtab.shstrtab.rela.text.data.bss.rodata.str1.1.rela.rodata.note.GNU-stack.note.gnu.property.rela.eh_frame @u@p &,12sE02@@x  Mb]h up@`2 hp  )3/324 0 0 0 644 31872 ` ELF>x@@USH' H=HcH>fDH5Ӊщff9<1f@% H[]D@Ӊщf8H5<1Є@%  fDAH D‰H1AH  D1E@% VfH51Ӊ<1f@ @Ӊ+@1É% % É1% % lj1% 1؃%É% ^f. @ @@ΉH=<1Ʌ É1% fD׃H @Ɖ1f É1% 1H @ƃ@ @1%  cH @Ɖ1Ʌ !@.1H=@@ʼn1@<Ӊ% f.HD΃F F1A1AAD D oDVE1ۃ@A1HAfD AAfD@D @ D D@H1DV1@@lj‰%@@ D @ HD΃F F1A1AA1f.DVE1ۃA1@HAfD AAf@H1DV1@@lj‰%@ D@H 1҉% @@H 1҉f% @H 1҉@% RfDAу1A)A)ɅE19AAAH1E1DEA1AE@1D!؁ %D D fDA1A)ɉA)х@E1f9AAAH1E1DEA1AfE1D!؁ %D D S1H=A)9A1ED1A1A@D 1D % ÉD!% fA1A)AA)҅G1@8@AAHE1D1҉DD1ɃED1AD!A E %D o1D AAɅ1D9@AAH1E1DD1҃ED1ADD!% D fD1D AAɅ1fA9@AAH1E1DD1ڃfED1ADD!%yD1D AAɅ1A8@AAHE1D1҉DD1ED1AA D!E %D  E1H=Af9AA1D1EA1Af@1D!%DD D f.H=E1)@8AD 11AA1A@1!ЉD D %D 8@E1H=AAA1ED1A1A@1D!%.f1H=A)f9A1ED1A1Af@D 1D % ÉD!% %p@HcHcH5HӉHH 9<1@Ɖ E1H=A@8AA1D1EA1A@1DD D! D % fDE1Һ@/E19Auf.1A8@*f1@8@fE1f9A1D9@ f1fA9@zA1щH=H=ff.AWHVHAVLAULoHATUSHHDE1HfDPH9uGI1fCDA Afs %8fDC fDKfC % fHClHD$,f.ɺLAI L9|$t/DDA<I|tLAI L9|$ufkH[]A\A]A^A_ff.wGwLIcL>1DH?Hȃf.191@81f9AVAAUADATEUDSDH5HcH> 11[]A\A]A^ []1A\A]A^[]1A\A]A^[]A\A] A^1ȃ[]1A\A]A^[]1A\A]A^‰[ ]A\1A]A^ 1ȃH=EADD1H=SHW0O4w,(S8tu*D{<u {@t[@ [ÐH H5H=t F8% t F<%t F@F(~,HF0f.USHHV0N4{(v,C(ƒHC0E‰C,H[]fAVAUATIUSH>HHH|uH5LHS: t1[]A\A]A^HRHHkLc:uۃzzQfDzrfDzu 8 Yzu 8 qzu 8 zu 8 zu 8 kzu 8 zu 8 $zu 8  zu 8 e zu 8  zu 8  zzuzz1zzzzz)z zB z z~ z z z z7 z r z  z @ z j z z z zAzhrz2zz8 H@8x t x 1x @HIHIHHHLHƿLH@'[]HA\A]A^fH5LJH8 HPHkLc:zzz+z!z zHC}zsJ%z\LHHSHf.H5L H8 H@8@HkHHH¿?8 HH9y1HLHILHE8 HH9yLH8 HH9xynLH+8 "HH9y H1IHLHILHƿOHLH[]A\A]A^@H5H IH5H=HH9y LHOHH9y uHLHI6HH9WyMLHQHH9?y5HLHQI1[]HA\A]A^8 HH9oyeL濈HIL&HHH9yLHS8  HH9yL濈HIL*Hf8 HH9yL濃HIL%H8 zHH9jy`L濃HIL)HHH9y{LHU8 HH9yHHHIHLHLSHHH9yHLHUI_8 UHH9Ey;A<$ -IL$9DAEHIHHHLH8 HH9y A<$ IL$9yHIHIHHHLHLH,H5LH H5H=8 HH9y1HHHHH9yHLHSIZHLHIHHHLSH~HH9yA<$ sIL$9bDQEUHI8 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H-#HLH1H5pKA11I1H"HLH1HS5KAue11I1H"HLH1H5JH=1H=1MH=1A11I 1H!HLH1Hw4BJL$PDDAH$LPDHAJcD$H>H=1i10HILHHH51H@ILAD$( ID$ H=HJ/]ILH=1GIopHH8AHH 1DIH@ILAD$( ID$ H=H ,DHH,5HLH=1yHv1/IHILHL⿱HILHH=H-G1w.IHILHL⿱HILHH=HbG1-IHL⿱HILHH=H,FLH=1tLH=1LH=1_u])HHH3sF@H=1H=1FLH=1AE~AD$@AFHHcH>AE~AAT$8AmH HcH>t$AHH5HEH=1 lH H81,HH=HY; A~lH H8AHD$1HH1AH@HƁDHLD$HHLDHH=HD1H.HDIHLHH-\D kH H8 \kH H8Ak1*HH=Ht*DHH=HDI1IHLLH1H-DI1IHLLHHH=H!C IjH H8 !jH H8 AiH H8AiHH8iHH8D$}iHH8AtH=11(HH=HHHH=H1HHHH 1HI|$HH=HHHHH 1HIDHH=H|$HDHH=HDHDHH=HD1H*#DH(-@H=11 'I&1IHLLHH]*&#@u >gH H81A&DHH=HD5 fH H8DADI1IHLHILLHDHH=HD1HP) #HHJ@HIHLHHi'>H=1.H=1x1%I %1IHLLHHk($1>uK1$1IHLH1H%(=H=1\H=1uS!1HH8*=u9 H9B.?HH*q=H=1H=11#1IHL⿫H1HA' =uc1#I#1IHLLHH&"u[HyPD?HH 3u9H-DT! @HHS3H=1H=1u[uH+eG?HH3u9CHqy O @HHd2H=1H=1H4HHz2 HH1HHHHI1LHwHHHH 1HIHH=H1H=11H=1EHIH1IH1ILHLHLHHH=H0u61oH1H0H=1-H=1AAAFE1H<AFAHcHLHH=1gH WH5H=b LD$efDDǠIHHH8=uLǠH=HE~/|ACDAAHDPjAXZD/AAFE1H<AFAAA딽HHcH=LHcH41LF1[H1H.A UH H8 AUH H81ADHH=HDHH=HD1HDH-H=1H=1A TH H8DHH=HH--L$PDH$DL?~H$DDAHcH>DH=1ASHH 1HIHILHH=HT,ILHHH51H@I8I|$0ID$ HID$(fAD$4LAD$0AD$8fAD$<AD$@fAD$DAD$HfAD$LH=H+LH=1p+LH=1RHH8AYRHH8AHyHHH 1HIDHH=HDHHH=HDHDHH=HDHHHH8=H@H=H1IHDIL+HDLHH=H)PHH8AILHHH51HD`I@8I}0IE HIE(AE0LfAE4AE8fAE<AE@fAEDAEHfAELH=HDHHHH8=~H@H=H1IHDHHڿ+HDLHH=H'LH=1'LH=1 1]IHILHLHILHH=H( C'1 IHILHLHILHH=H&LH=1LH=1Xu^ HHHM&H=1H=1&LH=1uQV HHu%H=1H=1%&LH=1uu17 IHL⿲HILHH=H$ ?%LH=1黴LH=1uE1LH5$E1LH5$E1LH5$EHIHIHH1I LHLHLHHH=H #EHIHIHH1I5 LHLHLHHH=HD#E1LH5&#E1LH5 #LH=1FE1LH5 "LH=1ff.AWAVAUATUSHXH$D$$=nH5HIHt$/IEDዔ$D$/H|$0HH+$DHt$ AW$$L L$LLD$0H|$(DKH D9t$/H|$LD$AHKHcEHA)HT$HN LAN\1f.L A9 ADHL9u@8HD$@foD$0IELAEHX[]A\A]A^A_f.H <H5H=H <H5H=@tPDLAW$$L$ Ht$8XH H=HD$DL%RLAW$$L$ Ht$8 HD$0Ll$(H Hl(HL1HCJ<(IH=1I9uk# $ *"&(jmp_litdisAModedis_MMX_shiftE_immdis_MMX_shiftG_byEdis_SHLRD_Gv_EvgetIRegmkU8integerGuestRegOffsetputIRegnewTempdis_push_segregdis_pop_segregpositiveIse_X86Condcodejcc_01dis_bt_G_Emath_BSWAPdis_bs_E_Gdis_Grp8_Immdis_Grp5setFlags_DEP1_DEP2_shiftdis_Grp2dis_Grp1codegen_xchg_eAX_RegcasLEdis_retdis_REP_opset_EFLAGS_from_valuedis_op2_G_Edis_op2_E_Ghelper_SBBhelper_ADCdis_op_imm_Adis_mov_Sw_Ewdis_imul_I_E_GmkAnd1mkSizedOpput_ST_TAGput_ST_UNCHECKEDdis_FPUjmp_tregputSRegmkU16putXMMRegLane32FputXMMRegLane64FputXMMRegputMMXRegput_ftopdis_PABS_helperdis_PSIGN_helperbreakup128to32sdis_MMXop_regmem_to_regdis_SSE_shiftG_byEdis_SSE_shiftE_immbreakup64to16sputXMMRegLane64xmmGuestRegLane64offsetxmmGuestRegLane16offsetputXMMRegLane16xmmGuestRegLane32offsetputXMMRegLane32dis_SSEcmp_E_to_Gput_emwarnput_sse_roundingmodedisInstr_X86_WRKdisInstr_X86priv/guest_x86_toIR.cfindSSECmpOp(x86,guest)%es:%ss:%ds%fs:%gs:sorbTxt(x86,guest)nameIReg(X86)ALWAYSobnbznzbenbesnspnplnllenlenoname_X86Condcodex86g_calculate_eflags_allx86g_calculate_conditiondres->len == 0dres->continueAt == 0ty == Ity_I8ty == Ity_I16ty == Ity_I32putIReg(x86)archreg < 8host_endness == VexEndnessLEisPlausibleIRType(ty) src, dst tys are: , narrowTo(x86)widenUto32i < 256sz == 1 || sz == 2 || sz == 4szToITy(x86)fucomi%s %%st(0),%%st(%u) f%s%c %s getUDisp(x86)nameISize(x86)%s%c %gs%es%ss%fs%cssz == 2 || sz == 4push%c %s pop%c %s tyE == tyN0handleSegOverride(x86,guest)x86g_use_seg_selectorx86g_calculate_eflags_csetFlags_DEP1_DEP2(x86)setFlags_DEP1(x86)i < 65536codegen_div(x86)guardsetFlags_DEP1_DEP2_shift(x86)t0 && *t0 == IRTemp_INVALIDt1 && *t1 == IRTemp_INVALIDt2 && *t2 == IRTemp_INVALIDt3 && *t3 == IRTemp_INVALIDrestart_point == 0%ax%eax%al!carryingdis_op_imm_A(x86,guest)%s%c $0x%x, %s epartIsReg(rm)%s $%d,%s imulmul%s%c %s %s(%s)%s%d(%s)%s0x%x(%s)disAMode(x86): not an addr!%s(0x%x)%s(%s,%s,%d)%s0x%x(,%s,%d)%s(%s,,)%s0x%x(,,)%s%d(%s,,)%s%d(%s,%s,%d)%s %s,%s sz == 4 || sz == 8%s $%d,%s,%s qdwx86g_calculate_mmx_pmaddwdx86g_calculate_mmx_psadbw 0x%x dis_MMXop_regmem_to_reghName == NULLhAddr == NULLhName != NULLhAddr != NULL%s%s %s, %s getSDisp(x86)imul %d, %s, %s mov%c %s,%s mkWidenOp(x86,guest)mov%c%c%c %s,%s sz == 4 || sz == 2bs%c%c %s, %s sh%cd%c %s, %s, %s xadd%c %s, %s keep%s%c %s,%s am_sz == 1x86g_calculate_RCRx86g_calculate_RCLwidenSto32%s%c %s, %s rcbt%s%c %s, %s cmpxchg%c %s,%s test%c $0x%x, %s not%c %s neg%c %s div%c %s idiv%c %s movd %s, %s movq %s, %s mov(nt)q %s, %s paddpaddspadduspsubpsubspsubuspmulhwpmullwpmaddwdpcmpeqpcmpgtpackssdwpacksswbpackuswbpunpckhpunpcklpandpandnporpxorpsllwpslldpsllqpsrlwpsrldpsrlqpsrawpsradmaskmovq %s,%s tt0t1ntat2hmapdupddqaaddsubsubdsubwaddswadddsubswaddwaam aad cwdq cdqq fsinfcosneex86g_dirtyhelper_CPUID_sse3x86g_dirtyhelper_CPUID_sse2x86g_dirtyhelper_CPUID_sse1x86g_dirtyhelper_CPUID_mmxextx86g_dirtyhelper_CPUID_sse0(assumed not taken)(assumed taken) 0x%x: dres.whatNext == Dis_StopHere%%eax = guest_NRADDR call-noredir *%%eax IR injection %%es:%%cs:%%fs:%%gs:nop nopw %%cs:0x0(%%eax,%%eax,1) nop%c nop%c %s lock !epartIsReg(modrm)fxsave %s x86g_dirtyhelper_FXSAVEfxrstor %s x86g_dirtyhelper_FXRSTORaddpssz == 4addssandnpsandpscmppscmpss[u]comiss %s,%s cvtpi2ps %s,%s cvtsi2ss %s,%s cvt%sps2pi %s,%s cvt%sss2si %s,%s divpsdivssldmxcsr %s x86g_check_ldmxcsrmovntq %s,%s pavgbpavgwpextrw $%d,%s,%s pinsrw $%d,%s,%s pmaxswpmaxubpminswpminubpmovmskb %s,%s pmuluhprefetch%s %s psadbwpshufw $%d,%s,%s sfence maxpsmaxssminpsminssmov[ua]ps %s,%s movhps %s,%s movhlps %s, %s movlps %s, %s movmskps %s,%s movntp%s %s,%s movss %s,%s mulpsmulssorpsrcppsrcpssrsqrtpsrsqrtssshufps $%d,%s,%s sqrtpssqrtssstmxcsr %s x86g_create_mxcsrsubpssubssunpck%sps %s,%s xorpsaddpdaddsdandnpdandpdcmppdcmpsd[u]comisd %s,%s cvtdq2pd %s,%s cvtdq2ps %s,%s cvtpd2dq %s,%s cvt%spd2pi %s,%s cvt%spf2pi %s,%s cvtpd2ps %s,%s cvtpi2pd %s,%s cvtps2dq %s,%s cvtps2pd %s,%s cvt%ssd2si %s,%s cvtsd2ss %s,%s cvtsi2sd %s,%s cvtss2sd %s,%s cvttpd2dq %s,%s cvttps2dq %s,%s divpddivsd%sfence maxpdmaxsdminpdminsdmov%s %s,%s movdqa %s, %s movdqu %s,%s movdqu %s, %s movdq2q %s,%s movhpd %s,%s movlpd %s, %s movmskpd %s,%s maskmovdqu %s,%s movntdq %s,%s movnti %s,%s movq %s,%s movq2dq %s,%s movsd %s,%s mulpdmulsdorpdshufpd $%d,%s,%s sqrtpdsqrtsdsubpdsubsdxorpdpaddbpadddpaddqpaddwpaddsbpaddswpaddusbpadduswpcmpeqbpcmpeqdpcmpeqwpcmpgtbpcmpgtdpcmpgtwpmaddwd %s,%s pmulhuwpmuludq %s,%s psadbw %s,%s pshufd $%d,%s,%s pshufhw $%d,%s,%s pshuflw $%d,%s,%s pslldq $%d,%s psrldq $%d,%s psubbpsubdpsubqpsubwpsubsbpsubswpsubusbpsubuswpunpckhbwpunpckhdqpunpckhqdqpunpckhwdpunpcklbwpunpckldqpunpcklqdqpunpcklwdclflush %s movs%cdup %s,%s movddup %s,%s addsubps %s,%s addsubpd %s,%s h%sps %s,%s h%spd %s,%s lddqu %s,%s pmaddubsw %s,%s ph%s %s,%s pmulhrsw %s,%s psign%s %s,%s pabs%s %s,%s palignr $%u,%s,%s palignr $%u%s,%s pshufb %s,%s movbe %s,%s rounds%c $%d,%s,%s roundsd $%d,%s,%s lzcnt%c %s, %s jcxz 0x%x ret %u ret iret (very kludgey) call 0x%x ; popl %s call 0x%x leave daa das aaa aas x86g_calculate_aad_aamcwde sz == 2cbw sahf lahf fwait fcoms %s fcomps %s subrdivdivrf%s%s st(%u), st(%u) fcom %%st(0),%%st(%u) fcomp %%st(0),%%st(%u) flds %s fsts %s fstps %s x86g_dirtyhelper_FLDENVfldenv %s fldcw %s x86g_check_fldcwx86g_dirtyhelper_FSTENVfnstenv %s fnstcw %s x86g_create_fpucwunhandled opc_aux = 0x%2x first_opcode == 0xD9 fld %%st(%u) fxch %%st(%u) fchs fabs ftst x86g_calculate_FXAMfxam fld1 fldl2t fldl2e fldpi fldlg2 fldln2 fldz f2xm1 fyl2x fptan fpatan fxtract x86amd64g_calculate_FXTRACTfprem1 fprem fyl2xp1 fsqrt fsincos frndint fscale %s fiaddl %s fimull %s ficoml %s ficompl %s fisubl %s fisubrl %s fidivl %s fidivrl %s fcmovb %%st(%u), %%st(0) fcmovz %%st(%u), %%st(0) fcmovbe %%st(%u), %%st(0) fcmovu %%st(%u), %%st(0) fucompp %%st(0),%%st(1) fildl %s fisttpl %s fistl %s fistpl %s x86g_dirtyhelper_loadF80lefldt %s x86g_dirtyhelper_storeF80lefstpt %sfirst_opcode == 0xDB fcmovnb %%st(%u), %%st(0) fcmovnz %%st(%u), %%st(0) fcmovnbe %%st(%u), %%st(0) fcmovnu %%st(%u), %%st(0) fnclex x86g_dirtyhelper_FINITfninit fcoml %s fcompl %s fldl %s fistppll %s fstl %s fstpl %s x86g_dirtyhelper_FRSTORfrstor %s x86g_dirtyhelper_FSAVEfnsave %s fnstsw %s first_opcode == 0xDD ffree %%st(%u) fst %%st(0),%%st(%u) fstp %%st(0),%%st(%u) fucom %%st(0),%%st(%u) fucomp %%st(0),%%st(%u) fiaddw %s fimulw %s ficomw %s ficompw %s fisubw %s fisubrw %s fidivrw %s fuompp %%st(0),%%st(1) fildw %s fisttps %s fistp %s fistps %s fildll %s fistpll %s first_opcode == 0xDF ffreep %%st(%d) fnstsw %%ax inc%c %s dec%c %s int $0x3 int $0x%x jmp-8 0x%x jmp 0x%x j%s-8 0x%x %s jecxz 0x%x loop%s 0x%x lea%c %s, %s segmentGuestRegOffset(x86)nameSReg(x86)mov %s,%s movw %s,%s mov%c %s0x%x, %s mov%c %s, %s0x%x movb $0x%x,%s mov%c $0x%x,%s mov%c $0x%x, %s oradcsbbandxorcmptestpopf%c popa%c push%c $0x%x pushf%c pusha%c movscmpsstoslodsscascld std clc stc cmc disInstr(x86)(clc/stc/cmc)salc repne movsrepne cmpsrepne stosrepne scasrep movsrepe cmpsrep stosrep lodsrepe scasrep nop (P4 pause) rep ret xchg%c %s, %s nop xlat%c [ebx] in%c $%d,%s %dxin%c %s,%s x86g_dirtyhelper_INout%c %s,$%d out%c %s,%s x86g_dirtyhelper_OUT%clnameGrp4(x86)%sb %s nameGrp5(x86)nameGrp8(x86)bswapl %s cmov%c%s %s,%s cmpxchg8b %s disInstr(x86)(cpuid)cpuid imul%c %s, %s j%s-32 0x%x %s x86g_dirtyhelper_RDTSCrdtsc set%s %s $%dsysenter{f}emms sgdt %s sidt %s x86g_dirtyhelper_SxDTsyscall ud2 guest_arch == VexArchX86x2 >= x1 %dl%bl%ah{sp}%ch{bp}%dh{si}%bh{di}%cx%bx%sp%bp%si%di%ecx%edx%ebx%esp%ebp%esi%edi???btbtsbtrbtcincdeccall*jmp*pushrolrorrclrcrshlshrsar%xmm0%xmm1%xmm2%xmm3%xmm4%xmm5%xmm6%xmm7%mm0%mm1%mm2%mm3%mm4%mm5%mm6%mm7ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32op8 == Iop_Add8 || op8 == Iop_Sub8 || op8 == Iop_Mul8 || op8 == Iop_Or8 || op8 == Iop_And8 || op8 == Iop_Xor8 || op8 == Iop_Shl8 || op8 == Iop_Shr8 || op8 == Iop_Sar8 || op8 == Iop_CmpEQ8 || op8 == Iop_CmpNE8 || op8 == Iop_CasCmpNE8 || op8 == Iop_ExpCmpNE8 || op8 == Iop_Not8typeOfIRExpr(irsb->tyenv,x) == Ity_I1typeOfIRExpr(irsb->tyenv,y) == Ity_I1dres->whatNext == Dis_Continuedres->jk_StopHere == Ijk_INVALIDcond >= X86CondO && cond <= X86CondNLEarchreg >= 4 && archreg < 8 && sz == 1typeOfIRExpr(irsb->tyenv,e) == Ity_I64typeOfIRExpr(irsb->tyenv,e) == Ity_V128typeOfIRExpr(irsb->tyenv, value) == Ity_I8typeOfIRExpr(irsb->tyenv, e) == Ity_I32typeOfIRExpr(irsb->tyenv, value) == Ity_F64typeOfIRExpr(irsb->tyenv,e) == Ity_I32typeOfIRExpr(irsb->tyenv,e) == Ity_F32typeOfIRExpr(irsb->tyenv,e) == Ity_F64dres->whatNext == Dis_StopHeretypeOfIRExpr(irsb->tyenv,e) == Ity_I16tyE == Ity_I32 || tyE == Ity_I16 || tyE == Ity_I8typeOfIRTemp(irsb->tyenv,t1) == Ity_I32typeOfIRTemp(irsb->tyenv, tres) == tytypeOfIRTemp(irsb->tyenv, texpVal) == tygregOfRM(rm) == 2 || gregOfRM(rm) == 4 || gregOfRM(rm) == 6size == 1 || size == 2 || size == 4op8 == Iop_Add8 || op8 == Iop_Sub8dis_Grp2(Reg): unhandled case(x86)vbi->guest_stack_redzone_size == 0guest_EIP_bbstart + delta == guest_EIP_curr_instr%%edx = client_request ( %%eax ) typeOfIRExpr(irsb->tyenv, sseround) == Ity_I32opc == 0x27 || opc == 0x2F || opc == 0x37 || opc == 0x3Fx86g_calculate_daa_das_aaa_aastypeOfIRExpr(irsb->tyenv, sw) == Ity_I16vex x86->IR: unhandled instruction bytes: 0x%x 0x%x 0x%x 0x%x disInstr_X86: inconsistency in LOCK prefix handling?GNUzRx 0J} I LPhui_US5)(BLA uBB8Bn( BGG ` FEE 88BOB A(A0(A BBB4tuBEE A(H0I(I EBB4uBEE A(H0I(I EBB4BBB A(F0|(A EBBDM O ,8BBA  EBI hDP,IDF  DBE 'D[DY K CdCd  ?AU J @<IBD r JBK D BBH A JBE $eHA G I G D?DQ K (gADF p ADH (oADF t ADL ,IED V EBI (LBFD c AEK (xBAD h AEK OGk N ] K (BCD  AEJ 8BBB B(N0(E BBBH0?BBA C(F0 (A ABBC D(A ABB(|BBI yEB8BQA A(D0 (A ABBG ,IBD s BEG 8BBD C(G0z (C DBBI 8PBBD C(G0z (C DBBI 4BBB N(D0w(C EBB(BGB GEPP4BEA J(F0`(I DBB(@IGD x DBN (lIGD x DBN (IGD x DBN (IGD x DBN 8FEB A(F0% (K EBBK <,_BBB I(A0 (A BBBK 8loFBE A(F0 (K EBBI 8BBB I(D0b (D BBBA LBBE I(A0 (A BBBH F (D DIBG `4 BBB B(A0H8F@/ 8A0A(B BBBH q 8J0A(B BBBE L OBBB A(H0K (A BBBG k (D IDBE 8 FBE A(D0j (K EBBH X$ BEB B(D0D8DPXJ`RXAPB 8A0D(B BBBH H BBE B(I0A8DP9 8C0D(B BBBO H BBB J(A0A8FPl 8I0D(B BBBG H BBB E(A0A8D@2 8F0D(B BBBK Hd 0BBB B(A0A8F` 8I0D(B BBBI < FBB B(D0 (E BBBE d ?BBB B(A0C8HP 8A0A(B BBBC  8A0D(B BBBK (X BFF W AEE H FEB B(A0C8D@W 8K0D(B BBBK H [FBB B(A0C8D@ 8K0D(B BBBG  UA2 M (< BDF A AEM dh oBBB E(D0I8FpV 8A0A(B BBBB N 8J0A(B BBBO H 7BBB B(A0A8D` 8I0D(B BBBI $D[ Q S M S M HDBEF I(A0C8KP 8A0A(B BBBI H@BGE E(D0A8D@{ 8A0D(B BBBL HBBE B(D0H8GP; 8A0D(B BBBJ H(BBE B(D0H8GP; 8A0D(B BBBJ LtBBB B(D0A8F 8A0D(B BBBF LBBB B(D0A8F 8A0D(B BBBF dkBBB B(A0C8Fp 8C0A(B BBBG jxNQxApxNQxApH|BJB B(D0D8DP 8C0A(B BBBH HBJB B(A0C8GP 8D0A(B BBBA H~BBB B(A0E8F@ 8D0A(B BBBE d`bBBB B(D0C8FP 8A0A(B BBBH   8C0A(B BBBK d BEB B(A0G8F@ 8D0A(B BBBE 0HKPHHA@LHKPHHA@d0?BEE B(A0A8G 8C0A(B BBBH  8D0A(B BBBK dBJB E(A0A8G, 8C0A(B BBBD n 8D0A(B BBBE LBBB B(D0D8F 8C0A(B BBBK dPoBEE B(D0D8D 8A0C(B BBBF  8D0A(B BBBI dBJB E(A0A8G, 8C0A(B BBBD n 8D0A(B BBBE d BJB B(A0C8G 8D0A(B BBBC  8C0A(B BBBF LBEB B(A0C8GR 8A0A(B BBBF LBEB B(A0A8J 8C0A(B BBBA H(BMB B(A0A8G 8D0A(B BBBF LtBEB B(A0C8G 8A0A(B BBBA LBEB E(D0A8F 8D0A(B BBBC L_BED D(D (A CBBG  (A ABBE ddBEE E(A0C8G! 8C0A(B BBBG  8D0A(B BBBE LBBB B(D0C8D 8A0A(B BBBF dBEB B(A0C8G 8C0A(B BBBI s 8A0A(B BBBC LBBB E(A0C8I 8A0A(B BBBH LBEB B(A0D8I 8A0A(B BBBK $BBB B(A0C8JNgA2NgA] 8A0A(B BBBF T NV  NY BBE B(A0C8JNjB^ 8A0A(B BBBK DUADUA Nb l HL l HL PBBB E(A0C8G- 8D0A(B BBBH DUAzMSBODUANSBM HL D HL LBEE E(D0A8Jy 8A0A(B BBBE LH BEB B(A0A8G6 8D0A(B BBBI \BBB E(A0A8I' 8D0A(B BBBF GAH BEE B(D0C8G 8D0A(B BBBD HDBEI B(A0D8F~ 8D0A(B BBBH BBB B(A0A8Gf 8A0A(B BBBA +pYAARoSAAHD LBB  RBAE MUBLL[AVNGBYQGBZMWA$KFA\DWBgHFBhHFAdKFAVDWBgHFBhHFAdKFAq XBAE y OBAE MWBLaGBhBFAkBFBLaFBYQFAkBGBZMXBLaGAYQGDaIAIQYA^OGB^RGAaFBLdGB[RFB^RGBFA' TLATEUA}TIBWEVB MXALaFBYQIAhBFAxMXBLaIAVQFBkBGBkBIAh!MUALXBHGBXBFB 9BIAFBB B(A0A8DVXGGu 8A0A(B BBBK FHGG`\EGGj " ;@HuPP_Y @j @| @@58`u(u5`Pe n0  p  8 @ 'p 7`CO!hC! ?@` e?g @o# <G P` yOp?P0  20=F]m!P Pp p!  0"_@-#o6%[&u (P@*O`@ ,p.5P0,2< U5n80 ;=?`" AC E[GU$@I1Jo<H U`N7iSmH PTPX@[ ^X!a  9PgD ]lkj `q @@!@t @@@w~   yb. 0 7  P Ѝ?j ~  " o   `  ! P1 !J \ o    0_  0    " / ;  T ` x y  p  @   `  @     )   > R *c  u P"  @@    @  0" ! !+  @;  T ( m  h"   0   3 B < = . 8 G Z  h o  q svx {~%+17=CIOHUp[agmsy-:Fcy0X 0X!'- 369M?*E:K&Q2W.]Xciboum{o\$@x(P %, 3:-A"HOIV]dRkwr_ynY! /=Kft !(/6=DKJRPYS`g,nu?|Y[]8l}|F$NV[$++=2p9@GNU\cj4qexvaj _  p f 6`F1 S  Y  E '.5<`C0JQ&X_ f m t]{     H     O k  % A  6  # */ 1 8 ? F M T [ bf i p w ~   JM ,  7   V C < U     I  &U-4;yBHIePTW^el~sz$^yt/;Ys(  v A f  y d   ;"")0* 7> E L^ S< Zv ahov}  s /#   0 Y_ 3  %,3::ARHQOV ]dkxry>/^   !+ ( /6 =!Du K RY` g nFu|{l    k$4+&29N@GNU\cjqxzWcho$k  j'N.25<aC3JCQZXx_fomt{j     ~  x#*18`?UFIM>T3[lb(ipw~ wPTl&{5m &-4+;IBYIP;Wj^ee`l[sAzu^RG%;0i Fb"")=07 >ElLS Zahov} ;$~vnN bhHB%<,-3:AHOV]odkrey\ S+J4    (4AN[gu   + 7 B Q ] j r }          !3!F!Y!b!p!|!!!!!!!" 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$lengthAModeguest_codemkSizedOp__PRETTY_FUNCTION__.4232findSSECmpOpsorbTxtnameIRegireg8_names.4436ireg32_names.4434ireg16_names.4435name_X86CondcodegetXMMRegmk_x86g_calculate_eflags_allget_sse_roundingmodemkAnd1irsb__PRETTY_FUNCTION__.4242mk_x86g_calculate_conditionmk64from16smk128from32sgen_SEGV_if_not_16_alignedguest_EIP_curr_instrjmp_treg__PRETTY_FUNCTION__.4485jcc_01__PRETTY_FUNCTION__.4494__PRETTY_FUNCTION__.4377assignputIReghost_endness__PRETTY_FUNCTION__.4109__PRETTY_FUNCTION__.4045storeLEjmp_lit__PRETTY_FUNCTION__.4479xmmGuestRegLane32offset__PRETTY_FUNCTION__.4091xmmGuestRegLane64offset__PRETTY_FUNCTION__.4096getMMXRegnewTemp__PRETTY_FUNCTION__.3979narrowTowidenUto32mkU8__PRETTY_FUNCTION__.4205putMMXReg__PRETTY_FUNCTION__.5435putXMMReg__PRETTY_FUNCTION__.4145put_ST_TAG__PRETTY_FUNCTION__.5095__PRETTY_FUNCTION__.5071maybe_fp_pushgetIReg__PRETTY_FUNCTION__.4101fp_popget_STfp_do_ucomi_ST0_STiset_C2do_MMX_preambleput_ST_UNCHECKED__PRETTY_FUNCTION__.5105fp_do_op_mem_ST_0fp_do_oprev_mem_ST_0get_FPU_swgetUDispdis_PALIGNR_XMM_helperputXMMRegLane32__PRETTY_FUNCTION__.4169putXMMRegLane32F__PRETTY_FUNCTION__.4163putXMMRegLane64F__PRETTY_FUNCTION__.4157putXMMRegLane64__PRETTY_FUNCTION__.4151dis_STOSdis_ret__PRETTY_FUNCTION__.5828dis_LODSmath_IS_TRIG_ARG_FINITE_AND_IN_RANGEdis_string_op.constprop.0dis_push_segregCSWTCH.1424__PRETTY_FUNCTION__.5814dis_pop_segreg__PRETTY_FUNCTION__.5821__PRETTY_FUNCTION__.4121dis_MOVScasLE__PRETTY_FUNCTION__.4254maybe_put_ST.constprop.0dis_PABS_helper__PRETTY_FUNCTION__.6136handleSegOverride.part.0dis_PSIGN_helper__PRETTY_FUNCTION__.6119setFlags_INC_DECset_EFLAGS_from_value__PRETTY_FUNCTION__.6087__PRETTY_FUNCTION__.5061setFlags_DEP1_DEP2dis_SCASdis_CMPSsetFlags_DEP1setFlags_MULdis_REP_op__PRETTY_FUNCTION__.5019dis_PMULHRSW_helpermkU__PRETTY_FUNCTION__.4209codegen_divsetFlags_DEP1_DEP2_shift__PRETTY_FUNCTION__.4327breakup128to32s__PRETTY_FUNCTION__.6059breakup64to16s__PRETTY_FUNCTION__.6075helper_SBB__PRETTY_FUNCTION__.4409helper_ADC__PRETTY_FUNCTION__.4393dis_op_imm_A__PRETTY_FUNCTION__.4696dis_SSE_shiftE_immxmm_names.4458__PRETTY_FUNCTION__.6032dis_MMX_shiftE_imm__PRETTY_FUNCTION__.5549mmx_names.4454math_BSWAP__PRETTY_FUNCTION__.6192codegen_mulL_A_DdisAMode__PRETTY_FUNCTION__.4575dis_SSE_E_to_G_unary_lo32dis_SSE_E_to_G_lo32dis_SSEcmp_E_to_G__PRETTY_FUNCTION__.5989dis_SSE_E_to_G_unary_alldis_SSE_E_to_G_lo64dis_SSE_E_to_G_all_wrkdis_SSE_shiftG_byE__PRETTY_FUNCTION__.6018dis_MMXop_regmem_to_reg__PRETTY_FUNCTION__.5506dis_SSEint_E_to_Gdis_MMX_shiftG_byE__PRETTY_FUNCTION__.5535dis_imul_I_E_G__PRETTY_FUNCTION__.5047dis_mov_E_Gdis_movx_E_Gdis_bs_E_G__PRETTY_FUNCTION__.5718dis_mov_G_Edis_SHLRD_Gv_Ev__PRETTY_FUNCTION__.5662dis_xadd_G_Edis_op2_E_G__PRETTY_FUNCTION__.4645dis_op2_G_E__PRETTY_FUNCTION__.4664dis_Grp1CSWTCH.1587grp1_names.4413__PRETTY_FUNCTION__.4755dis_Grp2CSWTCH.1589grp2_names.4417__PRETTY_FUNCTION__.4776dis_bt_G_E__PRETTY_FUNCTION__.5697dis_cmpxchg_G_Edis_Grp3.constprop.0dis_MMX.constprop.0disInstr_X86_WRKguest_EIP_bbstart__PRETTY_FUNCTION__.6231grp4_names.4421__PRETTY_FUNCTION__.5728grp5_names.4425__PRETTY_FUNCTION__.4941__PRETTY_FUNCTION__.6049__PRETTY_FUNCTION__.4086__PRETTY_FUNCTION__.4175grp8_names.4429__PRETTY_FUNCTION__.4831__PRETTY_FUNCTION__.5359__PRETTY_FUNCTION__.5807__PRETTY_FUNCTION__.7191.LC0.LC2.LC1.LC3.LC5.LC9.LC7.LC8.LC4.LC6.LC10.LC11.LC27.LC12.LC13.LC28.LC14.LC15.LC16.LC17.LC18.LC19.LC20.LC21.LC22.LC23.LC24.LC25.LC26.LC29.LC30.LC31.LC32.LC33.LC34.LC35.LC36.LC37.LC38.LC42.LC39.LC41.LC45.LC43.LC44.LC40.LC46.LC47.LC48.LC49.LC50.LC51.LC52.LC53.LC54.LC55.LC56.LC58.LC57.LC59.LC60.LC61.LC62.LC63.LC64.LC65.LC66.LC67.LC68.LC73.LC75.LC70.LC74.LC69.LC72.LC71.LC77.LC76.LC78.LC79.LC80.LC82.LC81.LC83.LC84.LC85.LC86.LC87.LC88.LC89.LC90.LC93.LC91.LC92.LC94.LC95.LC96.LC97.LC100.LC103.LC99.LC98.LC101.LC102.LC106.LC104.LC105.LC108.LC107.LC109.LC110.LC113.LC112.LC111.LC114.LC120.LC119.LC115.LC118.LC116.LC117.LC121.LC123.LC122.LC135.LC125.LC124.LC126.LC131.LC129.LC130.LC128.LC127.LC132.LC133.LC134.LC137.LC136.LC138.LC139.LC141.LC140.LC143.LC142.LC144.LC145.LC148.LC146.LC147.LC149.LC154.LC155.LC156.LC150.LC151.LC152.LC153.LC157.LC158.LC160.LC159.LC161.LC166.LC163.LC164.LC165.LC162.LC170.LC173.LC179.LC193.LC184.LC180.LC185.LC171.LC174.LC172.LC175.LC197.LC186.LC187.LC181.LC183.LC191.LC196.LC177.LC195.LC194.LC169.LC167.LC168.LC182.LC189.LC198.LC192.LC176.LC188.LC190.LC178.LC202.LC277.LC241.LC238.LC233.LC243.LC242.LC640.LC418.LC232.LC419.LC284.LC261.LC251.LC262.LC255.LC559.LC570.LC569.LC553.LC554.LC223.LC561.LC427.LC428.LC607.LC235.LC246.LC248.LC298.LC352.LC295.LC292.LC297.LC293.LC200.LC280.LC286.LC276.LC203.LC274.LC296.LC336.LC313.LC264.LC301.LC282.LC199.LC260.LC305.LC571.LC309.LC249.LC568.LC567.LC290.LC259.LC254.LC273.LC272.LC271.LC268.LC267.LC300.LC288.LC278.LC253.LC252.LC340.LC250.LC343.LC350.LC329.LC327.LC257.LC285.LC322.LC270.LC287.LC311.LC310.LC314.LC319.LC318.LC320.LC321.LC312.LC339.LC432.LC218.LC217.LC617.LC611.LC615.LC616.LC614.LC610.LC613.LC560.LC230.LC592.LC594.LC591.L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I|ALDL׹xI|E1DLLL$ H|$XMljG JILH9D!Lcd$XM|ALDL׹I{E1LLDL$ H|$XMmʼn?GHH,ldLcd$XM{E1DLLL$ H|$XMljF IILH;CLcd$XM{ALDLA,IzALDL׹aIzE1LDLӆIzE1LDL腢IzLDLIszALDLA-ILzE1DH|$XLL$ LML\$ʼnLcd$XL\$AM"DL\$HHAL\$IcHt$H=H L1pH H5H=E1DH|$XLL$ LML\$Lcd$XL\$AMg$L\$DHHH8AL\$yHcD$Ht$LH=H1xE1LLDL$ H|$XMjʼnN Lcd$XMevPA{LDjLLjjnH I7vLE1LDL$ H|$XML\$谅H|$H=Lcd$XMIcHL\$H H5HHDLH=1BE1DH|$XLL$ LML\$Lcd$XL\$AM"L\$DHHHG=L\$&uHcD$Ht$LH=H1tQAvLDjLLjjHmH ItE1DLLL$ H|$XMKlj@f5ILH<Lcd$XMhtH %H5H=E1DLLL$ H|$XMǃlj?4ILH < !Lcd$XMsLLADL$ H|$XML\$ZH|$H;HcT$XL\$H DbMcLMD,˰HcD$HHcDH H=LL1雰E1LLDL$ H|$XLD$貂 H|$H:Lcd$XLD$MHIcLH HcH=H1ATAxLDjLLjjjH IzrLE1LDL$ H|$XML\$H|$H:Lcd$XMgIcHL\$H H5HHDLH=1)APAwLDjLLjj(jH IqE1LLDL$ H|$XM+ʼn<HHILcd$XMAqQAzLDjLLjjiH IqALDLL^IpE1LLDL$`H$LD$iAH|$HH=HHDILHHHH=HHDILHH|$HH=H HDILHHDHH=HLc$LD$MRHcHLHH=1.E1LLDH$ H|$XI~HHFqLcd$XMnHIcHct$H HH=1KE1LLDL$ H|$XLD$8~HHe6Lcd$XLD$MHIcLH HcT$H=H1銯E1LLDL$ H|$XM}HDH5Lcd$XM~HIcMcH HcJ4H=H1HIcIcH IcH4H=H1ŹHcT$HHH=H IcH1McHLJ4H=1^HIcIcH IcH4H=H1頾McHLJH=1E1DLLL$ H|$XML|Ab:DHHH4Lcd$XMglE1LLDL$`H$M{HDHH=HLc$MLALDL$ H|$XLD$l{HHcD$XLHDH3D$XLD$D`McMזHcD$HH=H L1鯖LE1LDH$`H$IzHHH=HLc$MJIcHHHH=1&E1LLDH$ H|$XI5zHH[Lcd$XMYjE1LLDL$ H|$XMyHDH2Lcd$XMAE1LLDL$ H|$XMxyHDH1&Lcd$XM1E1DLLL$ H|$XMyA/7DHHH]1Lcd$XM4iLLADL$ H$MxHHH=HHc$H DbLMcD,MHcHDH H=L1酫McHLJH=15E1LLDL$ H|$XLD$wHH 0Lcd$XLD$MZHIcLH HcT$H=H1-E1LLDH$ H|$XISwHH X4Lcd$XMwgE1DLLL$ H|$XMvA(DHHHE/Lcd$XMgMcHLJ4H=1XE1LLDL$ H|$XLD$tvHH.Lcd$XLD$MHIcLH HcT$H=H1aHIcHct$H HH=1H %H5H=HIcIcH HcH4H=H1E1DLLL$ H|$XMnuA&DHHH-iLcd$XMeHcHLH4H=1RHcD$H HcT$HH=L IcLL1LLHIcHcDHcL$LH=L LL1L`LE1LDL$ H|$XML\$ttH|$H,Lcd$XMgIcHL\$H H5HHELH=1|gE1LLDL$ H|$XLD$sH|$H,Lcd$XLD$MHHcLH HcT$H=H1oE1DLLL$ H|$XMLs1AKDILH+Lcd$XMecHcHLHH=1E1LLDH$ H|$XIrHH:Lcd$XMb1DIcH=HHH HcT$H1靷LLADL$ H|$XML\$rHDHI*HcT$XL\$H DbMcLMD,L{HcD$HHcDH H=LL1{HIcMcH HcT$H=J4H1$E1LLDH$ H|$XIGqLcd$XMHHHQcaHcHHHH=1?aLLADL$ H|$XML\$pHDH(HcT$XL\$H DbMcLMD,(HcD$HHcDH H=LL1HIcIcH IcH4H=H1黸1DH H=HHcD$H 1钋HcHLHH=1xHcHLHH=1̿LE1LDH$H$I_oHHH=HLc$M7HcD$HHH=H1HIcIcH HcH4H=H1 HcD$H HcT$HH=L IcLL1LLwE1LLDH$ H|$XIcnLcd$XMHHHO^HcHHHH=1[^HIcIcH IcH4H=H1钵E1LLDL$ H|$XMmH1HxJLcd$XM鐩LE1LDL$ H|$XML\$EmH|$Hp%Lcd$XMIcHL\$H H5HHDLH=1E1LLDL$ H|$XMlHDH$(Lcd$XM]E1LLDH$`H|$\IMlAHDHH=HHDILHH|$HH=H Lcd$\MҡLE1LDH$`H$IkH|$HH=HLc$M}HcHHHH=1|HHcHcLH4H=1Li1DIcH=HHH HcT$H1aHcHLH4H=1HcD$HHcL$DH=LHcLL 1LLHcD$H HcT$HH=L IcLL1LLHcHLHH=1阈E1LLDL$ H|$XLD$iH|$H!Lcd$XLD$MmHHcLH HcT$H=H1lE1DLLL$ H|$XM8i1A@DILHz!Lcd$XMQYH AgH5H=HcHH=H4L1jHcD$HHcL$H5H=LHcLL 1LLtHcHLH4H=16HHcHcHH4H=1ԝHcD$H HcT$HH=L IcLL1LLYYHcHLHH=11DHcH=HHH HcT$H1k1DH H=HHcH41HcHHHH=1)HcHLHH=1"L\$HH *H5H=IcHHcHHH=H41vHcHHHH=1HcHH HHcH=H41%xHcD$HcL$HHH=LH 1LHcD$HcL$HHH=LH 1LHcHHHH=1HcD$HcL$HH5H=LH 1L6HLD EIU2HLD EIUHcHLHH=1HcHLH4H=1'HHcHcHH4H=1Fl"W|$I"DHDD(H|EETW L\$HLDEIT HLDEITHcHLH4H=1$|$|HD$$H|$tIXXFl"|$I!DHDD<+HkDES HLDEISu'D$g'AHF| V1DI!|$HDDg!DH |$D&1HJDD&HpJERHcHLH4H=1 HLDEIRHcHLHH=1/L\$ HcHHHH=1%HcD$HcL$HHH=LH 1L H H5H=HcT$HHcH=H4H1鉊HcHHHH=1hHcHLH4H=1W1HLDx EI]QHMcHcDHcT$N H=H LL1HjHcD$HcL$HHH=LH 1L1D HcH=HHH HcT$H1Y1DX H H=HHcH41HcHHHH=1kHcHLHH=1HHcMcDH JH=1H eH5H=H H5H=HIcHcDHcL$LH=L 1LLLH 3eH5H=H H5H=5HLDTEI9OHcHLH4H=1sL\$HcHHHH=1H H5H=H H5H=H %H5H=H %H5H=HcHH HIcH=H41LDLINH mH5H=!D$!AHF| 1DI|$HDDHf|$D$1HDDD$HDE.MHHcDH HcT$H=H1HHcDH IcH=H1HHcDH HcT$H=H1|3HLDEILH H5H=H H5H= HLD@EI%LHHcDH IcH=H1fHAWAVAUATUSHhH=HD$@H D$H4$L$HD$HHD$PF=YIAMHJ40HMNLUH=g%wq@Aw@Hc4H>AERAt $ىމA ރރ @AAtH$~tH$كEɃ AA DDÀ3HH5Hc H>OuHL9t' (H4$HˀL9ufAE9H=HHH=HH|$@H|$DpH$D$@foD$@HD$PAIGHhL[]A\A]A^A_AE,uL(1DL(AH@@@A@@ AD܃ ˍN D@D1A@@Ɖ|$1A @1AL$1AL$D L$ D  \$ \$ރD4,@$ ރ DމރEމރ Eމރ@EπAEAف~*~ ~~H ~~~ ~H~ ~ ~ =~ H~ ~~3~H3AUH5H=1L$D\$ LLD$HT$D\$ LD$DT$HT$)@HHB|0 FL0FD0BL0BT0B40WB|0WB|0WB|0WBD0H=P1AA؉ىډAH0AA1AH=LAt)LAtALHLEىډH=1ى H=1@<tFH=1D\$,LD$ DT$HT$DL$DL$HT$DT$LD$ D\$,fDrAH<(D\$H|$@AUAQMS$Ht$ D\$(H I@LH)YHnI9D$D lM)HD$PDl$@foL$@IGAH }H5H=H }H5H=H H5H=@t:H$xOUwH5Hc H>@88tƃLHt$?H|$@IH$AD\$PD\$I H ~H5H=H ~H5H=H ~H5H=@6H $H5H=~F<)<<tH=1H=MnH=HhHH=HHpHH=HH=LHHH=HD$DD$L @tH=1MnhA{ DHpFH0HHڿHH&HH=LHHHHH|$@D $|$D\H }H5H=tH=1xMnHtH=1HMnH|$@Lj |$DH }H5H=AWIAVAUATUSHXH$$$HH5I$D$/H|$0DD$DsD5Ht$/HHH+$P$$L L$HLLD$0Ht$(H|$ H_kH H<$Ht$LD$A91=D$/A96HKMcAD)JM *H$HNt1fL A9 ADHL9u8*HD$@foD$0IELAEHX[]A\A]A^A_T$0H HH; YH=1H$H5H=1H$H51H=HH=fDH IH5H=fH [H5H=PD$$DL P$$L$H H=LT$DL%RD$$L P$$L$jLT$(Ll$ H Il*HL1HCJ<(IH=1I9umpriv/guest_amd64_toIR.creg < 16reg < 8irregular == FalseALWAYSobaeenebeasnspnplgelegnoname_AMD64CondcodenameIReg(amd64)mkSizedOp(amd64)%ax%al%eax%raxnameIRegRAX(amd64)nameISize(amd64)*preZeroP == False*preSwapP == False*opP == Iop_INVALID*postNotP == FalsefindSSECmpOp(amd64,guest)preSwap == FalsenameXMMReg(amd64)nameYMMReg(amd64)ymmGuestRegOffset(amd64)doScalarWidening(amd64)amd64g_calculate_condition src, dst tys are: , narrowTo(amd64)host_endness == VexEndnessLEty == Ity_I64ty == Ity_I32ty == Ity_I16ty == Ity_I8putIRegRAX(amd64)dres->len == 0dres->continueAt == 0amd64g_dirtyhelper_FINITepartIsReg(mod_reg_rm) szToITy(%d) szToITy(amd64)getIRegRAX(amd64)widenUto640setFlags_DEP1_DEP2(amd64)setFlags_DEP1(amd64)setFlags_MUL(amd64)isPlausibleIRType(ty)i < 256i < 0x100000000ULLszB >= 0szB == 128amd64 %fs segment overrideamd64 %gs segment overridelaneno >= 0 && laneno < 4fucomi%s %%st(0),%%st(%u) amd64g_calculate_rflags_cf%s%s st(%u), st(%u) laneno >= 0 && laneno < 2IS_VALID_PFX(pfx)laneno >= 0 && laneno < 8t0 && *t0 == IRTemp_INVALIDt1 && *t1 == IRTemp_INVALIDgetSDisp(amd64)lo3bits < 8f%s%c %s amd64g_calculate_mmx_psadbwamd64g_calculate_mmx_pmaddwdtyE == tyNi < 0x10000ULLmkU(amd64)amd64g_calculate_pclmult2 && *t2 == IRTemp_INVALIDt3 && *t3 == IRTemp_INVALIDguardvepartIsReg(modrm)%spmovmskb %s,%s amd64g_calc_mpsadbwrestart_point == 0mkSzMask(amd64)!carryingdis_op_imm_A(amd64,guest)%s%c $%lld, %s amd64g_calculate_rflags_all%smovmskpd %s,%s epartIsReg(rm)%s $%d,%s pfx == clearSegBits(pfx)%s%c %s $%d,%s,%s %smaskmovdqu %s,%s %smovmskps %s,%s %spextrw $%u,%s,%s imulmul%s%c %s codegen_div(amd64)%cs:%ds:%es:%fs:%gs:%ss:%s%lld(,%s)%s%lld(,%s,%d)%s(%s,%s)%s(%s,%s,%d)%s%lld(%s,%s)%s%lld(%s,%s,%d)%s %s,%s,%s %s(%s)%s%lld(%s)disAMode(amd64): not an addr!%s%lld(%%rip)%s%lld%spshufd $%d,%s,%s %spshuf%cw $%u,%s,%s %smovddup %s,%s %spmovsxbq %s,%s %spmovsxwq %s,%s %spmov%cxbw %s,%s %spmov%cxbd %s,%s %spmovzxbq %s,%s %spmov%cxwd %s,%s %spmovzxwq %s,%s %spmov%cxdq %s,%s vcvtph2ps %s,%s !epartIsReg(modrm)gregOfRexRM(pfx,modrm) == 3%sstmxcsr %s amd64g_create_mxcsr1==getRexW(pfx)%spextrq $%d, %s,%s imul%c $%lld, %s, %s keepflag == WithFlagNone%s%c %s,%s mov%c %s,%s mov%c%c%c %s,%s am_sz == 1sz == 2 || sz == 4 || sz == 8sh%cd%c %s, %s, %s sz == 8amd64g_calculate_RCRamd64g_calculate_RCLwidenSto64%s%c %s, %s topc == 0x2D || opc == 0x2C%scvt%sss2si %s,%s %scvt%ssd2si %s,%s 0==getRexW(pfx)%spextrw $%d, %s,%s %spextrd $%d, %s,%s %sextractps $%d, %s,%s cmpxchg%c %s,%s rcbt%s%c %s, %s sz == 8 || sz == 4 || sz == 2bs%c%c %s, %s %smovs%cdup %s,%s addswadddsubdaddwsubswsubw%sph%s %s,%s %sphminposuw %s,%s qdw 0x%x dis_MMXop_regmem_to_reghName == NULLhAddr == NULLhName != NULLhAddr != NULL%s%s %s, %s %s %s,%s uopc == 0x2F || opc == 0x2E%s%scomisd %s,%s %s%scomiss %s,%s sz == 4 || sz == 8%s $%u,%s,%s,%s opFn == NULLopFn != NULLvcvtps2ph $%u,%s,%s %s %s,%s,%s,%s %scvt%spd2dq %s,%s %scvt%spd2dqx %s,%s vmovs%cdup %s,%s vcvt%spd2dq %s,%s vcvt%spd2dqy %s,%s %scvtps2pd %s,%s %scvtdq2pd %s,%s %scvtpd2ps %s,%s gregOfRexRM(pfx,modrm) == 2%sldmxcsr %s amd64g_check_ldmxcsr%scvt%sps2dq %s,%s %scvtdq2ps %s,%s !preZero!preSwap%s $%u,%s,%s pspd%s%stest%s %s,%s v%stest%s %s,%s declastencdecenclast,imcamd64g_dirtyhelper_AES%saes%s %s,%s%s%s %spcmp%cstr%c $%x,%s,%s (opc & 0x03) == 0x03amd64g_dirtyhelper_PCMPxSTRx%saeskeygenassist $%x,%s,%s vcvt%sps2dq %s,%s vpshuf%cw $%u,%s,%s vph%s %s,%s vpmov%cxbw %s,%s vpmov%cxbd %s,%s vpmov%cxwd %s,%s vpmov%cxdq %s,%s !isLoad && !isYMM%spextrb $%d, %s,%s %spextrb $%d,%s,%s palignr $%lld,%s,%s palignr $%lld%s,%s subaddh%sps %s,%s h%spd %s,%s addsubpd %s,%s addsubps %s,%s lddqu %s,%s xadd%c %s, %s test%c $%lld, %s not%c %s neg%c %s div%c %s idiv%c %s popcnt%c %s, %s tzcnt%c %s, %s lzcnt%c %s, %s pshufb %s,%s ph%s %s,%s pmaddubsw %s,%s psign%s %s,%s pmulhrsw %s,%s pabs%s %s,%s blendvpdblendvpspblendvbpminsbpmaxsbpmaxsdpminsdpmaxuwpminuwpminudpmaxudamd64g_calc_crc32lamd64g_calc_crc32bamd64g_calc_crc32wamd64g_calc_crc32qnmpmuldq %s,%s pcmpeqqmovntdqa %s,%s packusdw %s,%s pcmpgtqpmulld %s,%s crc32b %s,%s nm && fnmovbe %s,%s adcxadoxmovd %s, %s movd{64} %s, %s movq %s, %s mov(nt)q %s, %s paddpaddspadduspsubpsubspsubuspmulhwpmullwsz == 4pmaddwdpcmpeqpcmpgtpackssdwpacksswbpackuswbpunpckhpunpcklpandpandnporpxorpsllwpslldpsllqpsrlwpsrldpsrlqpsrawpsradmaskmovq %s,%s roundps $%d,%s,%s roundpd $%d,%s,%s rounds%c $%d,%s,%s blendps $%d, %s,%s blendpd $%d, %s,%s pblendw $%d, %s,%s pinsrb $%d,%s,%s insertps $%u, %s,%s pinsrd $%d, %s,%s pinsrq $%d, %s,%s dpps $%d, %s,%s dppd $%d, %s,%s mpsadbw $%d, %s,%s pclmulqdq $%d, %s,%s fsinfcosfcoms %s fcomps %s subrdivdivrfcom %%st(0),%%st(%u) fcomp %%st(0),%%st(%u) flds %s fsts %s fstps %s amd64g_dirtyhelper_FLDENVfldenv %s fldcw %s amd64g_check_fldcwamd64g_dirtyhelper_FSTENVfnstenv %s fnstcw %s amd64g_create_fpucwunhandled opc_aux = 0x%2x first_opcode == 0xD9 fld %%st(%u) fxch %%st(%u) fchs fabs amd64g_calculate_FXAMfxam fld1 fldl2t fldl2e fldpi fldlg2 fldln2 fldz f2xm1 fyl2x fptan fpatan fxtract x86amd64g_calculate_FXTRACTfprem1 fincstp fprem fyl2xp1 fsqrt fsincos frndint fscale %s fiaddl %s fimull %s fisubl %s fisubrl %s fidivrl %s first_opcode == 0xDA fcmovb %%st(%u), %%st(0) fcmovz %%st(%u), %%st(0) fcmovbe %%st(%u), %%st(0) fcmovu %%st(%u), %%st(0) fucompp %%st(0),%%st(1) fildl %s fisttpl %s fistl %s fistpl %s amd64g_dirtyhelper_loadF80lefldt %s amd64g_dirtyhelper_storeF80lefstpt %sfirst_opcode == 0xDB fcmovnb %%st(%u), %%st(0) fcmovnz %%st(%u), %%st(0) fcmovnbe %%st(%u), %%st(0) fcmovnu %%st(%u), %%st(0) fnclex fninit fcoml %s fcompl %s fldl %s fistppll %s fstl %s fstpl %s amd64g_dirtyhelper_FRSTORSamd64g_dirtyhelper_FRSTORfrstors %s frstor %s amd64g_dirtyhelper_FNSAVESamd64g_dirtyhelper_FNSAVEfnsaves %s fnsave %s fnstsw %s first_opcode == 0xDD ffree %%st(%u) fst %%st(0),%%st(%u) fstp %%st(0),%%st(%u) fucom %%st(0),%%st(%u) fucomp %%st(0),%%st(%u) fiaddw %s fimulw %s fisubw %s fisubrw %s fidivrw %s first_opcode == 0xDE fcompp %%st(0),%%st(1) fildw %s fisttps %s fists %s fistps %s fildll %s fistpll %s first_opcode == 0xDF ffreep %%st(%d) fnstsw %%ax (assumed taken)(assumed not taken)%gs%es%ss%ds%fs%cscwd cltd cqo rep ; ret ret oradcsbbandxorcmppush%c %s pop%c %s movslq %s,%s push%c $%lld bnd ; j%s-8 0x%llx %s testxchg%c %s, %s nameSReg(amd64)mov %s,%s lea%c %s, %s popl %s rep nop (P4 pause) nop regLo3 < 8cltqcwtl cbw fwait pushf%c sz == 2 || sz == 4popf%c sahf lahf mov%c %s0x%llx, %s mov%c %s, %s0x%llx rep movsmovsrepe cmpsrep stosstoslodsrepne scasrepe scasscasmovb $%lld,%s movabsq $%lld,%s mov%c $%lld,%s ret $%lld mov%c $%lld, %s xbeginq 0x%llx xabort $%denter $%u, $0 leave int $0x3 int $0xD2 %clloop%s%s 0x%llx jecxz 0x%llx jrcxz 0x%llx in%c $%d,%s %dxin%c %s,%s sz == 1 || sz == 2 || sz == 4amd64g_dirtyhelper_INout%c %s,$%d out%c %s,%s amd64g_dirtyhelper_OUTcall 0x%llx jmp 0x%llx jmp-8 0x%llx cmc clc stc disInstr(x64)(cmc/clc/stc)cld std nameGrp4(amd64)%sb %s nameGrp5(amd64)ht1t2ntat0mrex64/movupd %s,%s movsd %s,%s movss %s,%s movups %s,%s movlpd %s, %s movhlps %s, %s movlps %s, %s unpck%sps %s,%s movhpd %s,%s movhps %s,%s prefetch%s %s movapd %s,%s movaps %s,%s cvtpi2ps %s,%s cvtsi2ss %s,%s cvtsi2ssq %s,%s cvtsi2sdl %s,%s cvtsi2sdq %s,%s cvtpi2pd %s,%s movntp%s %s,%s cvt%sps2pi %s,%s cvt%spd2pi %s,%s cvt%spf2pi %s,%s sqrtsssqrtpssqrtsdsqrtpdrsqrtssrsqrtpsrcpssrcppsandpsandpdandnpsandnpdorpsorpdxorpdxorpsaddpsaddssaddsdaddpdmulsdmulssmulpsmulpdcvtss2sd %s,%s cvtsd2ss %s,%s subsssubsdsubpssubpdminpsminssminsdminpddivsddivpsdivssdivpdmaxpsmaxssmaxsdmaxpdpunpcklbwpunpcklwdpunpckldqpcmpgtbpcmpgtwpcmpgtdpunpckhbwpunpckhwdpunpckhdqpunpcklqdqpunpckhqdqsz == 2 || sz == 8mov%c %s, %s movdqa %s,%s movdqu %s,%s pshufw $%d,%s,%s psrldq $%d,%s pslldq $%d,%s pcmpeqbpcmpeqwpcmpeqdmovdqu %s, %s movdqa %s, %s sfence %sfence clflush %s %sfxsave %s %sfxrstor %s %sxsave %s %sxrstor %s cmppscmpsscmpsdcmppdmovnti %s,%s pinsrw $%d,%s,%s pextrw $%d,%s,%s shufps $%d,%s,%s shufpd $%d,%s,%s paddqmovq2dq %s,%s movq %s,%s movdq2q %s,%s pmovmskb %s,%s psubusbpsubuswpminubpaddusbpadduswpmaxubpavgbpavgwpmuluhpmulhuwmovntq %s,%s movntdq %s,%s psubsbpsubswpminswpaddsbpaddswpmaxswpmuludq %s,%s pmaddwd %s,%s psadbwpsadbw %s,%s psubbpsubwpsubdpsubqpaddbpaddwpadddamd64g_dirtyhelper_CPUID_avx2sgdt %s sidt %s amd64g_dirtyhelper_SxDTxgetbv xend xtest amd64g_dirtyhelper_RDTSCPrdtscp syscall ud2 prefetch %s prefetchw %s nop%c nop%c %s amd64g_dirtyhelper_RDTSCrdtsc cmov%s %s,%s j%s-32 0x%llx %s set%s %s bndmk %s, %%bnd%d bndcl %s, %%bnd%d bndcu %s, %%bnd%d bndcn %s, %%bnd%d bndmov %s, %%bnd%d bndmov %%bnd%d, %s bndldx %s, %%bnd%d bndstx %%bnd%d, %s cpuid $%dimul%c %s, %s nameGrp8(amd64)%s%c $0x%llx, %s cmpxchg8b %s amd64g_dirtyhelper_RDRANDrdrand %sbswapl %s bswapq %s {f}emms vpermqvpermpdvpblendd $%u,%s,%s,%s vpermilps $%u,%s,%s vpermilpd $%u,%s,%s vperm2f128 $%u,%s,%s,%s vroundps $%d,%s,%s vroundpd $%d,%s,%s vrounds%c $%d,%s,%s,%s vblendps $%u,%s,%s,%s vblendpd $%u,%s,%s,%s vpblendw $%u,%s,%s,%s vpalignr $%u,%s,%s,%s vinsertf128 $%u,%s,%s,%s vextractf128 $%u,%s,%s vpinsrb $%d,%s,%s,%s vpinsrd $%d,%s,%s,%s vpinsrq $%d,%s,%s,%s vinserti128 $%u,%s,%s,%s vextracti128 $%u,%s,%s vdpps $%d,%s,%s,%s vdppd $%d,%s,%s,%s vmpsadbw $%d, %s,%s,%s vpclmulqdq $%d, %s,%s,%s vperm2i128 $%u,%s,%s,%s vblendvpsvblendvpdvpblendvbvfm%s%c %s,%s,%s,%srorx %d,%s,%s naddsubsubadd231213132sdssvpshufbvpmaddubswvpsign%c %s,%s,%s vpmulhrsw %s,%s,%s vpermilps %s,%s,%s vpermilpd %s,%s,%s vpermpsvbroadcastss %s,%s vbroadcastsd %s,%s vbroadcastf128 %s,%s vpabsbvpabswvpabsdvpmovsxbq %s,%s vpmovsxwq %s,%s vpmuldqvpcmpeqqvmovntdqa %s,%s vpackusdwvmaskmovpsvmaskmovpdvpmovzxbq %s,%s vpmovzxwq %s,%s vpermdvpcmpgtqvpminsbvpminsdvpminuwvpminudvpmaxsbvpmaxsdvpmaxuwvpmaxudvpmulldvpsrlvdvpsrlvqvpsravdvpsllvdvpsllvqvpbroadcastd %s,%s vpbroadcastq %s,%s vbroadcasti128 %s,%s vpbroadcastb %s,%s vpbroadcastw %s,%s vpmaskmovdvpmaskmovqvpgatherddvpgatherdqvpgatherqdvpgatherqqvgatherdpsvgatherdpdvgatherqpsvgatherqpddis_FMA(amd64)vf%sm%s%s%s %s,%s,%s andn %s,%s,%s blsi %s,%s blsmsk %s,%s blsr %s,%s bzhi %s,%s,%s pdep %s,%s,%s amd64g_calculate_pdeppext %s,%s,%s amd64g_calculate_pextmulx %s,%s,%s sarxshlxshrxbextr %s,%s,%s vmovsd %s,%s vmovsd %s,%s,%s vmovss %s,%s vmovss %s,%s,%s vmovupd %s,%s vmovups %s,%s vmovddup %s,%s vmovhlps %s,%s,%s vmovlpd %s,%s,%s vmovlpd %s,%s vunpck%sps %s,%s vunpck%spd %s,%s vmovlhps %s,%s,%s vmovhp%c %s,%s,%s vmovhp%c %s,%s vmovapd %s,%s vmovaps %s,%s vcvtsi2sdl %s,%s,%s vcvtsi2sdq %s,%s,%s vcvtsi2ssq %s,%s,%s vcvtsi2ssl %s,%s,%s vmovntp%c %s,%s vmovmskps %s,%s vsqrtssvsqrtpsvsqrtsdvsqrtpdvrsqrtssvrsqrtpsvrcpssvrcppsvandpdvandpsvorpdvorpsvxorpdvxorpsvaddsdvaddssvaddpsvaddpdvmulsdvmulssvmulpsvmulpdvcvtps2pd %s,%s vcvtpd2psy %s,%s vcvtsd2ss %s,%s,%s vcvtss2sd %s,%s,%s vcvtdq2ps %s,%s vsubsdvsubssvsubpsvsubpdvminsdvminssvminpsvminpdvdivsdvdivssvdivpsvdivpdvmaxsdvmaxssvmaxpsvmaxpdvpunpcklbwvpunpcklwdvpunpckldqvpacksswbvpcmpgtbvpcmpgtwvpcmpgtdvpackuswbvpunpckhbwvpunpckhwdvpunpckhdqvpackssdwvpunpcklqdqvpunpckhqdqsz == 2vmovd %s, %s vmovq %s, %s vmovdq%c %s,%s vpshufd $%d,%s,%s vpsrlwvpsrawvpsllwvpsrldvpsradvpslldvpsrldq $%d,%s,%s vpslldq $%d,%s,%s vpsrlqvpsllqvpcmpeqbvpcmpeqwvpcmpeqdvzeroupper vzeroall vh%spd %s,%s,%s vmovq %s,%s vmovd %s,%s vcmpsdvcmpssvcmppdvcmppsvpinsrw $%d,%s,%s vshufps $%d,%s,%s,%s vshufpd $%d,%s,%s,%s vaddsubpdvaddsubpsvpaddqvpmullwvpmovmskb %s,%s vpsubusbvpsubuswvpminubvpandvpaddusbvpadduswvpmaxubvpandnvpavgbvpavgwvpmulhuwvpmulhwvcvtdq2pd %s,%s vmovntdq %s,%s vpsubsbvpsubswvpminswvporvpaddsbvpaddswvpmaxswvpxorvlddqu %s,%s vpmuludqvpmaddwdvpsadbwvpsubbvpsubwvpsubdvpsubqvpaddbvpaddwvpadddNONE0F380F0F3Aguest_RIP_next_assumed == 0 0x%llx: dres.whatNext == Dis_StopHere%%rax = guest_NRADDR call-noredir *%%rax IR injection lock esc == ESC_NONEguest_arch == VexArchAMD64x2 >= x1assumed next %%rip = 0x%llx actual next %%rip = 0x%llx %ymm0%ymm1%ymm2%ymm3%ymm4%ymm5%ymm6%ymm7%ymm8%ymm9%ymm10%ymm11%ymm12%ymm13%ymm14%ymm15%xmm0%xmm1%xmm2%xmm3%xmm4%xmm5%xmm6%xmm7%xmm8%xmm9%xmm10%xmm11%xmm12%xmm13%xmm14%xmm15%mm0%mm1%mm2%mm3%mm4%mm5%mm6%mm7???btbtsbtrbtcinccall*jmp*pushrolrorrclrcrshlshrsar%dl%bl%spl%bpl%sil%dil%r8b%r9b%r10b%r11b%r12b%r13b%r14b%r15b%ah%ch%dh%bh%cx%bx%sp%bp%si%di%r8w%r9w%r10w%r11w%r12w%r13w%r14w%r15w%ecx%edx%ebx%esp%ebp%esi%edi%r8d%r9d%r10d%r11d%r12d%r13d%r14d%r15d%rcx%rdx%rbx%rsp%rbp%rsi%rdi%r8%r9%r10%r11%r12%r13%r14%r15bwdbwd @ @  @ @  $ CDEBCDEBDCBBDCBBCDEBCDEBDCBBDCBjmp_litputIRegVputYMMRegLane32Fdis_FMAdis_VMASKMOVputYMMRegLane32dis_AVX_var_shiftV_byEdis_PHADD_256dis_AVX256_shiftV_byEdis_AVX128_shiftV_byEputYMMRegdis_VEX_NDS_256_AnySimdPfx_0F_WIGdis_VEX_NDS_128_AnySimdPfx_0F_WIGdis_PMOVMSKB_256dis_AVX256_cmp_V_E_to_Gdis_AVX128_cmp_V_E_to_GbreakupV256toV128sdis_AVX256_shiftE_to_V_immdis_AVX128_shiftE_to_V_immputYMMRegLane64FymmGuestRegLane32offsetputYMMRegLane64ymmGuestRegLane64offsetbreakupV256to64sdis_ESC_0F__VEXdis_PCMPISTRI_3Adis_PEXTRQdis_PEXTRDdis_PEXTRWdis_AESxxmmGuestRegLane16offsetdis_ESC_0F38__SSE4math_PABS_MMXdis_PSIGN_helperdis_PHADD_128dis_ESC_0F38__SupSSE3putXMMRegbreakupV128to64sdis_SSE_shiftG_byEdis_PMOVMSKB_128breakup64to16sfindSSECmpOpdis_SSE_cmp_E_to_Gdis_XRSTORdis_XSAVEdis_FXRSTORdis_FXSAVEput_sse_roundingmodedis_LDMXCSRdis_STMXCSRputXMMRegLane64dis_SSE_shiftE_immputXMMRegLane32FxmmGuestRegLane64offsetputXMMRegLane64FymmGuestRegLane128offsetputYMMRegLane128dis_COMISSdis_COMISDdis_CVTxSD2SIdis_CVTxSS2SIbreakupV128to32sxmmGuestRegOffsetxmmGuestRegLane32offsetputXMMRegLane32dis_ESC_0F__SSE2dis_MMX_shiftE_immdis_MMX_shiftG_byEdis_MMXop_regmem_to_regputMMXRegdis_MMXmath_BSWAPdis_bs_E_Gdis_bt_G_Edis_Grp8_Immdis_SHLRD_Gv_Evdis_ESC_0Fdis_Grp5setFlags_INC_DECputIRegAHmake_redzone_AbiHintgetIRegRDXgetIReg32mkAnd1putIReg32mkU32put_ST_TAGput_C3210put_ST_UNCHECKEDput_emwarnput_ftopput_fprounddis_FPUsetFlags_DEP1_DEP2_shiftdis_Grp2getIRegCLmkU8getIReg64rexXnameIReg64rexXdisAModeputIRegEdis_retnameIRegRexBputIRegRexBdis_string_opdis_REP_opdis_op_imm_AputIRegRDXmkSizedOpputIReg16getIReg16codegen_xchg_rAX_RegnameIRegputIRegGmkU16casLEhelper_ADCX_ADOXdis_op2_E_Gdis_Grp1positiveIse_AMD64Condcodejcc_01dis_imul_I_E_GgetIRegRexBsetFlags_DEP1helper_SBBhelper_ADCeregOfRexRMoffsetIRegEoffsetIRegoffsetIRegGdis_op2_G_EsetFlags_DEP1_DEP2dis_ESC_NONEjmp_tregputIReg64newTempgetIRegRAXputIRegRAXdisInstr_AMD64_WRKdisInstr_AMD64op8 == Iop_Add8 || op8 == Iop_Sub8 || op8 == Iop_Mul8 || op8 == Iop_Or8 || op8 == Iop_And8 || op8 == Iop_Xor8 || op8 == Iop_Shl8 || op8 == Iop_Shr8 || op8 == Iop_Sar8 || op8 == Iop_CmpEQ8 || op8 == Iop_CmpNE8 || op8 == Iop_CasCmpNE8 || op8 == Iop_Not8integerGuestReg64Offset(amd64)typeOfIRExpr(irsb->tyenv,x) == Ity_I1typeOfIRExpr(irsb->tyenv,y) == Ity_I1dres->whatNext == Dis_Continuedres->jk_StopHere == Ijk_INVALIDcond >= AMD64CondO && cond <= AMD64CondNLEtypeOfIRExpr(irsb->tyenv,e) == Ity_I64typeOfIRExpr(irsb->tyenv, value) == Ity_I8typeOfIRExpr(irsb->tyenv,e) == Ity_I32typeOfIRTemp(irsb->tyenv, new_rsp) == Ity_I64typeOfIRTemp(irsb->tyenv, nia) == Ity_I64typeOfIRExpr(irsb->tyenv,e) == Ity_V256amd64toIR: unimplemented feature typeOfIRExpr(irsb->tyenv, e) == Ity_I32typeOfIRExpr(irsb->tyenv, value) == Ity_F64typeOfIRExpr(irsb->tyenv,e) == Ity_F64typeOfIRExpr(irsb->tyenv,e) == Ity_V128typeOfIRExpr(irsb->tyenv, e) == Ity_I64typeOfIRExpr(irsb->tyenv,e) == Ity_F32typeOfIRExpr(irsb->tyenv,e) == szToITy(sz)sz == 8 || sz == 4 || sz == 2 || sz == 1typeOfIRExpr(irsb->tyenv, e) == szToITy(sz)dres->whatNext == Dis_StopHeretyE == Ity_I64 || tyE == Ity_I32 || tyE == Ity_I16 || tyE == Ity_I8setFlags_DEP1_DEP2_shift(amd64)typeOfIRTemp(irsb->tyenv, tres) == tytypeOfIRTemp(irsb->tyenv, texpVal) == tyamd64g_dirtyhelper_XSAVE_COMPONENT_0amd64g_dirtyhelper_XSAVE_COMPONENT_1_EXCLUDING_XMMREGSgregLO3ofRM(rm) == 2 || gregLO3ofRM(rm) == 4 || gregLO3ofRM(rm) == 6amd64g_dirtyhelper_XRSTOR_COMPONENT_0amd64g_dirtyhelper_XRSTOR_COMPONENT_1_EXCLUDING_XMMREGStypeOfIRExpr(irsb->tyenv, e) == Ity_I8extra_bytes >= 0 && extra_bytes < 10size == 2 || size == 4 || size == 8flag == WithFlagNone || flag == WithFlagCarrysz == 1 || sz == 2 || sz == 4 || sz == 8dis_Grp2(Reg): unhandled case(amd64)vbi->guest_stack_redzone_size == 128amd64g_calculate_sse_phminposuw0==getVexL(pfx) && 0==getRexW(pfx)typeOfIRExpr(irsb->tyenv, sseround) == Ity_I32amd64g_dirtyhelper_AESKEYGENASSIST1==getVexL(pfx) && 0==getRexW(pfx)typeOfIRExpr(irsb->tyenv, sw) == Ity_I16typeOfIRExpr(irsb->tyenv,e) == Ity_I16amd64g_dirtyhelper_CPUID_avx_and_cx16amd64g_dirtyhelper_CPUID_sse42_and_cx16amd64g_dirtyhelper_CPUID_baselinecount == 1 || count == 2 || count == 4 || count == 8guest_RIP_next_mustcheck == False%%rdx = client_request ( %%rax ) delta - delta_at_primary_opcode >= 0delta - delta_at_primary_opcode < 16vex amd64->IR: unhandled instruction bytes: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x vex amd64->IR: REX=%d REX.W=%d REX.R=%d REX.X=%d REX.B=%d vex amd64->IR: VEX=%d VEX.L=%d VEX.nVVVV=0x%x ESC=%s vex amd64->IR: PFX.66=%d PFX.F2=%d PFX.F3=%d disInstr_AMD64: disInstr miscalculated next %ripdisInstr_AMD64: inconsistency in LOCK prefix handling?GNUzRx i0D\ H d D P5)0hDw E Z F Q G _ I O A (Jv H O I _ A F A UISG8BBA A(D0: (A ABBF 4%YH%Y\#Wp)](BGG ` FEE 4uBEE A(H0I(I EBBDBEE E(A0C8GP8I0D(B BBBHEB{8dBGB A(A0(A BBBh?IEA n EGG D BBH A EGK A EGK A EGK A EGE ( [ADF [ ADE 8DPP'D[hDM O ,BBA  EBH $AAG AD4BEB A(F0{(A EBBDZ R 0%AA^L"AAHhLGSDX L [D[ Q Cd(Ds I S M N J X P  WDf N 0(Hy O D D I O I G I E (\BGD  AEJ G H (BDF  AEL ?AU J ?DR J  ?IN I ((gADF p ADH ,TIED V EBI (wADF } ADK ,/BBA  EBE (gADF p ADH ( {EDF w ADE L8BED D(F0^ (I DBBL D (D ABBC (BAD h AEK (BFD c AEK H] [ H] [ (BCD  AEJ 8DBBB B(N0(E BBBHBBA C(F0 (A ABBA D(A ABB[H] K 8BQA A(D0 (A ABBG <$ FBB A(C0F (D BBBJ ,d IBD s BEG H BBE D(C0| (A BBBE A(A BBBH BBE D(C0| (A BBBE A(A BBB4, BBB N(D0w(C EBB,d MGD G DBK , MGD G DBK 8 BGB B(D0(K BBB8 BEB B(D0(K BBB< {D] O X {D] O (t EDF C ADI  Kl H] [  H] [ , FEA g BBI 4 BEA K(G0b(I DBB,T BBK  EBE , MGD G DBK , MGD G DBK , BDH  DBK  _DN N 80 FJB A(F0 (D BBBC (l EDF  ADI 8 BHD C(F0 (A DBBK ( BDI i AEJ (BAD M AEF ,PP@DFBB B(A0F@ 0D(B BBBD (IDF  DBH ,?BAA  DBL </FBE J(A0 (E BBBC 0$OFBA F0  DBBF 8XBBA A(D0 (A DBBJ <BBB B(I0 (K BBBG 8BBE I(F@ (D BBBJ $8L`t8BBD C(G0z (C DBBI 8<BBD C(G0z (C DBBI (xIDD y DBH <_BBE E(I0 (E BBBI 8BBB I(D0b (D BBBA H BDB B(I0H8F@' 8D0A(B BBBK lQDQ S \ H 8OFBB F(D@ (D BBBB 0OFBA F0  DBBF @LBE J(D0DP/ 0D(B BBBH H@BEB J(A0A8G@~ 8A0A(B BBBD H/BJE E(D0A8F@ 8D0A(B BBBF HBBB E(I0A8DP 8D0A(B BBBH 8$FJE A(D@ (D BBBG 0`OFBA F0  DBBF <BBJ D(A0 (D BBBE 8BBB A(F@V (D BBBC ,MGD G DBK (@IGD } DBI (lIGD } DBI ,MGD G DBK H?BBB B(D0H8DP 8D0A(B BBBH HBBE J(A0A8FP 8D0A(B BBBA X`BEB B(D0D8DPXJ`SXAPO 8A0D(B BBBI ( Fp J T L R N S M HBBE B(I0A8DP9 8C0D(B BBBO H4FBB B(D0H8D`X 8D0A(B BBBG <FEB A(C0T (D BBBI ~A_ P f J HBBB B(A0H8FP~ 8D0A(B BBBF <0gBBB B(I0& (E BBBF p8oFBB A(K0+ (D BBBE 8oFBB A(K0+ (D BBBE 8$oFBB A(K0+ (D BBBE H`BBJ E(A0A8F@E 8D0A(B BBBC HBBB J(A0C8F@ 8D0A(B BBBA HFFEB B(A0C8DP 8A0D(B BBBL HDBBB J(A0C8F@ 8D0A(B BBBF H0BBB B(A0A8F` 8I0D(B BBBI DL H j F 0Gr G T D O I ] C O A <4BBB A(A0w (D BBBG HtFBB B(D0H8Dp 8D0A(B BBBF 0AQ N  Q HwLBJ E(A0A8F`" 8D0A(B BBBD $0 F~ D X H g A HXOBHB B(A0A8D@ 8A0D(B BBBF <FBE A(A0 (D BBBL HFBB B(A0C8DPb 8A0D(B BBBM H0_BBB B(A0A8DPu 8E0A(B BBBG L|/LBE B(A0A8F 8D0A(B BBBH H7BBB B(A0A8D` 8I0D(B BBBI ${DY C X H w I @?D[ A j F 8dBHD C(F0Q (A DBBO LEBBB E(A0C8D 8A0D(B BBBH LEBBB E(A0C8D 8A0D(B BBBH H@>BBB E(D0A8D@ 8A0A(B BBBB HBBE B(D0H8GP; 8A0D(B BBBJ HBBE B(D0H8GP; 8A0D(B BBBJ H$ BBB B(F0A8F`( 8D0A(B BBBF Hp _BBB B(F0A8F` 8D0A(B BBBK 0 WFBB I@  EBBF 0 OFBA H0  DBBD H$!BBE J(A0A8Fp 8D0A(B BBBI Hp!FBB B(D0H8Dp] 8D0A(B BBBJ 0!WFBB G@  EBBH 0!OFBA H0  DBBD H$"BBB B(A0C8FPH 8D0A(B BBBI Lp"BEB B(A0A8K 8D0A(B BBBJ H"OBBB E(A0H8Gp 8A0A(B BBBF H #BBB B(A0A8FPF 8D0A(B BBBE TX#/FBB B(D0H8DE}8D0A(B BBBJ #An Q q O h#BBB B(D0C8Gp 8D0A(B BBBH xNRxApWxNRxApH@$eBBB B(A0C8Dp 8A0D(B BBBI H$BBB B(A0A8D`2 8E0A(B BBBB H$BBB B(A0C8GP 8E0A(B BBBA d$%BBB B(D0I8Fp 8A0A(B BBBC  8J0A(B BBBK H%-BBB E(A0D8KP 8D0A(B BBBH H%BBB B(D0A8GP 8D0A(B BBBJ H$&BBB E(A0D8KP 8D0A(B BBBG Hp&ZBBB J(D0A8F@ 8D0A(B BBBG H&& BBB B(D0C8K` 8A0A(B BBBH H'?BBB B(A0I8F` 8D0A(B BBBK HT'BBB B(A0A8D` 8E0A(B BBBJ H'BBB B(A0H8FP6 8D0A(B BBBF H'BBB B(A0H8FP6 8D0A(B BBBF H8(OBBE B(D0A8K` 8D0A(B BBBG d(d BBB B(D0C8FPf 8C0A(B BBBI  8A0A(B BBBK d(BEE B(A0A8DP 8A0D(B BBBH  8A0A(B BBBK HT)BBJ E(A0A8FP 8A0D(B BBBI H)'BBB B(A0E8F` 8D0A(B BBBA H)<BBB B(D0H8FP  8D0A(B BBBD \8*BBB E(A0C8J 8D0A(B BBBE !EWAd*BBB B(D0A8G`e 8D0A(B BBBJ  hRpMhA`hRpMhA`L+BJB E(D0A8I 8D0A(B BBBF LP+BBJ B(D0A8Jt 8D0A(B BBBH L+BBE B(D0A8G 8D0A(B BBBK L+BJE B(D0A8GI 8D0A(B BBBK L@,BJE B(D0A8GI 8D0A(B BBBK L,?BBE E(D0A8GO 8D0A(B BBBJ L,wBBE E(D0A8G 8D0A(B BBBH L0-BJB E(D0A8G 8D0A(B BBBG L-BBE E(D0A8GO 8D0A(B BBBJ L-BJB E(D0A8G 8D0A(B BBBB L .BBE E(D0A8G 8D0A(B BBBA Lp.BBB E(D0A8F 8D0A(B BBBK D.BBB A(A0GC 0D(A BBBC L/oBBE B(D0A8G 8D0A(B BBBG LX/BBB B(D0A8J, 8D0A(B BBBH / BEE E(A0D8GPmA` 8A0A(B BBBD  P` GMoAm P_ X00BBB D(C0G 0D(A BBBK  0E(A BBBE d0'BFE E(D0D8G 8D0A(B BBBG  8E0A(B BBBC L0RBDE H(A0A8G 8D0A(B BBBF D1 BEB E(A0D8GUFWAa 8A0A(B BBBH FWA]MlB M\ t HL , HE 1yBEB B(A0A8I0 8D0A(B BBBE FXAMSB@FXANSBM HL D HL L2 BBE E(A0D8Gx 8A0A(B BBBD L2VBEB E(D0A8I 8A0A(B BBBK L43BFB B(A0A8D 8D0A(B BBBE L3BFB B(A0A8D 8D0A(B BBBJ L3_BBB E(D0A8Jg 8D0A(B BBBB L$4BJB E(D0A8G 8D0A(B BBBB Lt4BBB B(I0D8F 8D0A(B BBBE \4WBBB E(A0C8JGA] 8A0A(B BBBC L$5t BEE E(D0C8J 8A0A(B BBBG Lt5BBB E(A0C8J 8D0A(B BBBA L5/BEB E(D0A8G 8D0A(B BBBK L6BFB B(D0A8JK 8D0A(B BBBE Ld6BBB B(A0D8F 8D0A(B BBBE L6? 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|$$DD\$sD\$A?{AgAVAA0AAD˺hDD\$H${SD\$A<H=1D\$AD\$<$DH=1A?H=1L$L$8A DDILH/HOA]Au0WDDILHA!s [DDILH/HH=1AD\$pH=1A;R|$$SDD\$5D\$A;"|$HHH ^1H{L$=|$$DD\$G;D\$A;CuS|$$DD\$"D\$A;ZH=1L$L$1%tȃ  HHcH>EDDD\$!ID\$A<|$(DDD\$~D\$A<DEݿ D\$BA A ÉD A 7 A݉D$%DAHH|$HH=HHHDHH=HDD\$=H=1D\$A<D\$H=1KDHLHHLDH=1YH=1DH=1LDHwBH=1AAEt0AADDHH5HEH=1D|$IL⿭HHADHDHE |$|$ ILDHHH=HHDHH=HH\$$HƉH=HDDILHDHH=HDDILTHDIDILTHLH腴HILHƿ|$HH=H|$|$H>kD/HA  D`DHH=Ho = HH8AƉHDHH=H DDD+?u|$|$ IL@HHH=HHDHH=HH\$$HƉH=HDDILHDHH=H?HDIL HHHILH\$(HƉAXAA)  H=1f DDILH*=|$$DD\$pD8D\$A?Ȼ=DA%=韻*DDILH/HH=1D\$AD\$:AJAHH8AHH8H$EDp(pDD~DHH=H=DAHHDILE1HHH=HPJ<IHILH1IHLHGE9w=ANAnzDDD1 H==X=AlAQA?FAADH=1cP|$|$ IL@HHH=HHDHH=HH|$$HH=HDDILHEH H5H==F#=vwA=A6 DDH=1DFA鉷=A=m|$ DD\$řD\$A==3vA%A=t=A=tH=14DDD1 H=t$H=1|$0TDD\$D\$A;_|$4DD\$D\$A;/DD\$zD\$A; A;|$,DD\$D\$AϵDDH=1 H=1t$H=1:H=1dH=1H H5H=DD$DDH=1AGD\$H=1AD\$D\$9|$HDIL0HDHH=HDDDH=1A?[|$$\DD\$C)D\$A?+|$$,DD\$"kD\$A?Cuz|$$DD\$~6D\$A?ƳDD\$ɩD\$A顳DD$DDH=1AA?whH=1 DH=1銿H=1D\$AD\$DH=1>HH8Aƅ DD1H=DLDILHA|$mLIHDILHLH}HIHHH8=J=L@t.H=HHHHH`PHHH=1HH!H{H H鎽H5HHDH=1Z DH= H=1bDDH=1D=HHD\HDILH=HtZHA|$u\PHH8Aƅ H뤿H= 0t0 && *t0 == IRTemp_INVALIDt1 && *t1 == IRTemp_INVALIDt2 && *t2 == IRTemp_INVALIDt3 && *t3 == IRTemp_INVALIDfmrgew fr%u,fr%u,fr%u fmrgow fr%u,fr%u,fr%u dis_fp_merge(ppc)(opc2) .dscliq%s fr%u,fr%u,%u dscriq%s fr%u,fr%u,%u dscli%s fr%u,fr%u,%u dscri%s fr%u,fr%u,%u drintxq/drintnq%s fr%u,fr%u dis_dfp_roundq(ppc)(opc2) drintx/drintn%s fr%u,fr%u dis_dfp_round(ppc)(opc2) daddq%s fr%u,fr%u,fr%u dsubq%s fr%u,fr%u,fr%u dmulq%s fr%u,fr%u,fr%u ddivq%s fr%u,fr%u,fr%u dadd%s fr%u,fr%u,fr%u dsub%s fr%u,fr%u,fr%u dmul%s fr%u,fr%u,fr%u ddiv%s fr%u,fr%u,fr%u dxex%s fr%u,fr%u,fr%u diex%s fr%u,fr%u,fr%u generate_store_C_FPCC_helperxsrqpi %d,v%d,v%d,%d xsrqpix %d,v%d,v%d,%d xsrqpxp %d,v%d,v%d,%d dxexq%s fr%u,fr%u diexq%s fr%u,fr%u,fr%u vextublx %d,%d,v%dvextuhlx %d,%d,v%dvextuwlx %d,%d,v%dvextubrx %d,%d,v%dvextuhrx %d,%d,v%dvextuwrx %d,%d,v%ddis_abs_diff(ppc)(instr) vabsdub v%d,v%d,v%d vabsduh v%d,v%d,v%d vabsduw v%d,v%d,v%d dquai%s fr%u,fr%u,fr%u dqua%s fr%u,fr%u,fr%u drrnd%s fr%u,fr%u,fr%u dquaiq%s fr%u,fr%u,fr%u drrndq%s fr%u,fr%u,fr%u mode64dctqpq%s fr%u,fr%u dctfixq%s fr%u,fr%u drdpq%s fr%u,fr%u dcffixq%s fr%u,fr%u dis_av_fp_cmp(ppc)(instr) vcmpeqfp%s v%d,v%d,v%d vcmpgefp%s v%d,v%d,v%d vcmpgtfp%s v%d,v%d,v%d vcmpbfp%s v%d,v%d,v%d dis_av_fp_cmp(ppc)(opc2) dctdp%s fr%u,fr%u drsp%s fr%u,fr%u dctfix%s fr%u,fr%u dcffix%s fr%u,fr%u dis_vx_move(ppc)(instr) mfvsrld %u,r%u mfvsrdd %u,r%u mfvsrws %u,r%u dis_vx_move(ppc)(opc2) dis_av_mult10(ppc)(instr) vmul10cuq v%d,v%d vmul10ecuq v%d,v%d,v%d vmul10uq v%d,v%d vmul10euq v%d,v%d,v%d dis_av_mult10(ppc)(opc2) vpmsumb v%d,v%d,v%d vpmsumd v%d,v%d,v%d vpmsumw v%d,v%d,v%d vpmsumh v%d,v%d,v%d vcfux v%d,v%d,%d vcfsx v%d,v%d,%d vctuxs v%d,v%d,%d vctsxs v%d,v%d,%d vrfin v%d,v%d vrfiz v%d,v%d vrfip v%d,v%d vrfim v%d,v%d dis_av_fp_convert(ppc)(opc2) vand v%d,v%d,v%d vandc v%d,v%d,v%d vor v%d,v%d,v%d vxor v%d,v%d,v%d vnor v%d,v%d,v%d vorc v%d,v%d,v%d vnand v%d,v%d,v%d veqv v%d,v%d,v%d dis_av_logic(ppc)(opc2=0x%x) dis_av_fp_arith(ppc)(instr) vmaddfp v%d,v%d,v%d,v%d vnmsubfp v%d,v%d,v%d,v%d vaddfp v%d,v%d,v%d vsubfp v%d,v%d,v%d vmaxfp v%d,v%d,v%d vminfp v%d,v%d,v%d vrefp v%d,v%d vrsqrtefp v%d,v%d vexptefp v%d,v%d => not implemented vlogefp v%d,v%d dis_av_cipher(ppc)(instr) vcipher v%d,v%d,v%d vcipherlast v%d,v%d,v%d vncipher v%d,v%d,v%d vncipherlast v%d,v%d,v%d vsbox v%d,v%d dis_av_cipher(ppc)(opc2) vaddcuw v%d,v%d,v%d vaddubm v%d,v%d,v%d vadduhm v%d,v%d,v%d vadduwm v%d,v%d,v%d vaddudm v%d,v%d,v%d vaddubs v%d,v%d,v%d vadduhs v%d,v%d,v%d vadduws v%d,v%d,v%d vaddsbs v%d,v%d,v%d vaddshs v%d,v%d,v%d vaddsws v%d,v%d,v%d vsubcuw v%d,v%d,v%d vsububm v%d,v%d,v%d vsubuhm v%d,v%d,v%d vsubuwm v%d,v%d,v%d vsubudm v%d,v%d,v%d vsububs v%d,v%d,v%d vsubuhs v%d,v%d,v%d vsubuws v%d,v%d,v%d vsubsbs v%d,v%d,v%d vsubshs v%d,v%d,v%d vsubsws v%d,v%d,v%d vmaxub v%d,v%d,v%d vmaxuh v%d,v%d,v%d vmaxuw v%d,v%d,v%d vmaxud v%d,v%d,v%d vmaxsb v%d,v%d,v%d vmaxsh v%d,v%d,v%d vmaxsw v%d,v%d,v%d vmaxsd v%d,v%d,v%d vminub v%d,v%d,v%d vminuh v%d,v%d,v%d vminuw v%d,v%d,v%d vminud v%d,v%d,v%d vminsb v%d,v%d,v%d vminsh v%d,v%d,v%d vminsw v%d,v%d,v%d vminsd v%d,v%d,v%d vavgub v%d,v%d,v%d vavguh v%d,v%d,v%d vavguw v%d,v%d,v%d vavgsb v%d,v%d,v%d vavgsh v%d,v%d,v%d vavgsw v%d,v%d,v%d vmuloub v%d,v%d,v%d vmulouh v%d,v%d,v%d vmulouw v%d,v%d,v%d vmuluwm v%d,v%d,v%d vmulosb v%d,v%d,v%d vmulosh v%d,v%d,v%d vmulosw v%d,v%d,v%d vmuleub v%d,v%d,v%d vmuleuh v%d,v%d,v%d vmuleuw v%d,v%d,v%d vmulesb v%d,v%d,v%d vmulesh v%d,v%d,v%d vmulesw v%d,v%d,v%d vsum4ubs v%d,v%d,v%d vsum4sbs v%d,v%d,v%d vsum4shs v%d,v%d,v%d vsum2sws v%d,v%d,v%d vsumsws v%d,v%d,v%d dis_av_arith(ppc)(opc2=0x%x) calculate_XER_OV_32: op = %u calculate_XER_OV_32(ppc)dis_av_load(ppc)(instr) ppc32g_dirtyhelper_LVSppc64g_dirtyhelper_LVSlvsl v%d,r%u,r%u lvsr v%d,r%u,r%u lvebx v%d,r%u,r%u lvehx v%d,r%u,r%u lvewx v%d,r%u,r%u lvx v%d,r%u,r%u lvxl v%d,r%u,r%u dis_av_load(ppc)(opc2) calculate_XER_OV_64: op = %u calculate_XER_OV_64(ppc64)lhbrx r%u,r%u,r%u lwbrx r%u,r%u,r%u ldbrx r%u,r%u,r%u sthbrx r%u,r%u,r%u stwbrx r%u,r%u,r%u stdbrx r%u,r%u,r%u dis_int_ldst_rev(ppc)(opc2) dis_av_store(ppc)(instr) stvebx v%d,r%u,r%u stvehx v%d,r%u,r%u stvewx v%d,r%u,r%u stvx v%d,r%u,r%u stvxl v%d,r%u,r%u dis_av_store(ppc)(opc2) prtyd r%u,r%u dis_int_parity(ppc)(opc2) dis_av_rotate(ppc)(instr) dis_av_rotate(ppc)(opc2) vrlwmi %d,%d,v%dvrldmi %d,%d,v%dvrlwnm %d,%d,v%dvrldnm %d,%d,v%dddedpd %llu,r%u,r%u denbcd %llu,r%u,r%u dis_fp_move(ppc)(instr) fcpsgn%s fr%u,fr%u,fr%u fneg%s fr%u,fr%u fmr%s fr%u,fr%u fnabs%s fr%u,fr%u fabs%s fr%u,fr%u dis_fp_move(ppc)(opc2) fmsubs%s fr%u,fr%u,fr%u,fr%u fmadds%s fr%u,fr%u,fr%u,fr%u fmsub%s fr%u,fr%u,fr%u,fr%u fmadd%s fr%u,fr%u,fr%u,fr%u fnmsub%s fr%u,fr%u,fr%u,fr%u fnmadd%s fr%u,fr%u,fr%u,fr%u dis_fp_multadd(ppc)(opc1) ddedpdq %llu,r%u,r%u stfs fr%u,%d(r%u) stfsu fr%u,%d(r%u) stfd fr%u,%d(r%u) stfdu fr%u,%d(r%u) dis_fp_store(ppc)(instr,b0) stfsx fr%u,r%u,r%u stfsux fr%u,r%u,r%u stfdx fr%u,r%u,r%u stfdux fr%u,r%u,r%u stfiwx fr%u,r%u,r%u dis_fp_store(ppc)(opc2) dis_fp_store(ppc)(opc1) dis_vx_logic(ppc)(instr) xxlxor v%d,v%d,v%d xxlor v%d,v%d,v%d xxlnor v%d,v%d,v%d xxland v%d,v%d,v%d xxlandc v%d,v%d,v%d xxlorc v%d,v%d,v%d xxlnand v%d,v%d,v%d xxleqv v%d,v%d,v%d dis_vx_logic(ppc)(opc2) getGST(ppc): reg = %ugetGST(ppc)dis_av_quad(ppc)(instr) vaddcuq v%d,v%d,v%d vadduqm v%d,v%d,v%d vsubcuq v%d,v%d,v%d vsubuqm v%d,v%d,v%d vbpermq v%d,v%d,v%d vaddecuq v%d,v%d,v%d,v%d vaddeuqm v%d,v%d,v%d,v%d vsubecuq v%d,v%d,v%d,v%d vsubeuqm v%d,v%d,v%d,v%d dis_av_quad(ppc)(opc2.2) slw%s r%u,r%u,r%u sraw%s r%u,r%u,r%u srawi%s r%u,r%u,%d srw%s r%u,r%u,r%u sld%s r%u,r%u,r%u srad%s r%u,r%u,r%u sradi%s r%u,r%u,%u srd%s r%u,r%u,r%u dis_int_shift(ppc)(opc2) dis_int_shift(ppc)(opc1) modud r%u,r%u,r%u moduw r%u,r%u,r%u cnttzw%s r%u,r%u cnttzd%s r%u,r%u modsd r%u,r%u,r%u modsw r%u,r%u,r%u dis_modulo_int(ppc)(opc2) dis_modulo_int(ppc)(opc1) dis_int_cmp(ppc)(flag_L) dis_int_cmp(ppc)(b22) cmpi cr%u,%u,r%u,%d cmpli cr%u,%u,r%u,0x%x dis_int_cmp(ppc)(0x1F,b0) cmp cr%u,%u,r%u,r%u cmpl cr%u,%u,r%u,r%u setb r%u,%d dis_int_cmp(ppc)(opc2) dis_int_cmp(ppc)(opc1) fdivs%s fr%u,fr%u,fr%u fsubs%s fr%u,fr%u,fr%u fadds%s fr%u,fr%u,fr%u fsqrts%s fr%u,fr%u fres%s fr%u,fr%u fmuls%s fr%u,fr%u,fr%u frsqrtes%s fr%u,fr%u dis_fp_arith(ppc)(3B: opc2) fdiv%s fr%u,fr%u,fr%u fsub%s fr%u,fr%u,fr%u fadd%s fr%u,fr%u,fr%u fsqrt%s fr%u,fr%u fsel%s fr%u,fr%u,fr%u,fr%u fre%s fr%u,fr%u fmul%s fr%u,fr%u,fr%u frsqrte%s fr%u,fr%u dis_fp_arith(ppc)(3F: opc2) dis_fp_arith(ppc)(opc1) dis_av_permute(ppc)(instr) vsel v%d,v%d,v%d,v%d vperm v%d,v%d,v%d,v%d dis_av_permute(ppc)(vsldoi) vsldoi v%d,v%d,v%d,%d vpermxor v%d,v%d,v%d,v%d vpermr v%d,v%d,v%d,v%d vmrghb v%d,v%d,v%d vmrghh v%d,v%d,v%d vmrghw v%d,v%d,v%d vmrglb v%d,v%d,v%d vmrglh v%d,v%d,v%d vmrglw v%d,v%d,v%d vextractub v%d,v%d,%d vextractuh v%d,v%d,%d vextractuw v%d,v%d,%d vextractd v%d,v%d,%d vinsertb v%d,v%d,%d vinserth v%d,v%d,%d vinsertw v%d,v%d,%d vinsertd v%d,v%d,%d vspltb v%d,v%d,%d vsplth v%d,v%d,%d vspltw v%d,v%d,%d vspltisb v%d,%d vspltish v%d,%d vspltisw v%d,%d vmrgow v%d,v%d,v%d vmrgew v%d,v%d,v%d dis_av_permute(ppc)(opc2) ty_src == tyty_src == Ity_I32ty_src == Ity_I64putGST(ppc): reg = %uputGST(ppc)tweqi r%u,%d tw%di r%u,%d tdeqi r%u,%d td%di r%u,%d tweq r%u,r%u tw%d r%u,r%u tdeq r%u,r%u td%d r%u,r%u dis_av_procctl(ppc)(instr) mfvscr v%d mtvscr v%d dis_av_procctl(ppc)(opc2) putGST_masked(ppc): reg = %uputGST_masked(ppc)dis_vvec_cmp(ppc)(instr) xvcmpeqdp%s crf%d,fr%u,fr%u xvcmpgedp%s crf%d,fr%u,fr%u xvcmpgtdp%s crf%d,fr%u,fr%u xvcmpeqsp%s crf%d,fr%u,fr%u xvcmpgesp%s crf%d,fr%u,fr%u xvcmpgtsp%s crf%d,fr%u,fr%u dis_vvec_cmp(ppc)(opc2) dcmpo %u,fr%u,fr%u dcmpoq %u,fr%u,fr%u dis_dfp_compare(ppc)(opc2) dtstsf %u,r%u,r%u dtstsfi %u,%u,r%u dtstsfq %u,r%u,r%u dtstsfiq %u,%u,r%u dis_fp_cmp(ppc)(instr) fcmpu crf%d,fr%u,fr%u fcmpo crf%d,fr%u,fr%u dis_fp_cmp(ppc)(opc2) cgdtstd%s %u,r%u,%u dtstd%sq %u,r%u,%u dtstex %u,r%u,r%d dtstexq %u,r%u,r%d dis_byte_cmp(ppc)(opc1) cmprb %u,%u,r%u,r%u cmpeqb %u,r%u,r%u dis_byte_cmp(ppc)(opc2) dis_av_bcd_misc(ppc)(instr) bcdcpsgn. v%d,v%d,v%d dis_av_bcd_misc(ppc)(opc2) xxsldwi v%d,v%d,v%d,%d xxpermdi v%d,v%d,v%d,0x%x xxmrg%cw v%d,v%d,v%d xxsel v%d,v%d,v%d,v%d xxperm v%u,v%u,v%u xxpermr v%u,v%u,v%u xxspltw v%d,v%d,%d dis_av_shift(ppc)(instr) vrlb v%d,v%d,v%d vrlh v%d,v%d,v%d vrlw v%d,v%d,v%d vrld v%d,v%d,v%d vslb v%d,v%d,v%d vslh v%d,v%d,v%d vslw v%d,v%d,v%d vsld v%d,v%d,v%d vsl v%d,v%d,v%d vslo v%d,v%d,v%d vsrb v%d,v%d,v%d vsrh v%d,v%d,v%d vsrw v%d,v%d,v%d vsr v%d,v%d,v%d vsrab v%d,v%d,v%d vsrah v%d,v%d,v%d vsraw v%d,v%d,v%d vsrad v%d,v%d,v%d vsro v%d,v%d,v%d vsrd v%d,v%d,v%d dis_av_shift(ppc)(opc2) dis_av_cmp(ppc)(instr) vcmpequb%s v%d,v%d,v%d vcmpneb%s v%d,v%d,v%d vcmpequh%s v%d,v%d,v%d vcmpneh%s v%d,v%d,v%d vcmpequw%s v%d,v%d,v%d vcmpnew%s v%d,v%d,v%d vcmpnezb%s v%d,v%d,v%d vcmpnezh%s v%d,v%d,v%d vcmpnezw%s v%d,v%d,v%d vcmpequd%s v%d,v%d,v%d vcmpgtub%s v%d,v%d,v%d vcmpgtuh%s v%d,v%d,v%d vcmpgtuw%s v%d,v%d,v%d vcmpgtud%s v%d,v%d,v%d vcmpgtsb%s v%d,v%d,v%d vcmpgtsh%s v%d,v%d,v%d vcmpgtsw%s v%d,v%d,v%d vcmpgtsd%s v%d,v%d,v%d dis_av_cmp(ppc)(opc2) lfs fr%u,%d(r%u) lfsu fr%u,%d(r%u) lfd fr%u,%d(r%u) lfdu fr%u,%d(r%u) dis_fp_load(ppc)(instr,b0) lfsx fr%u,r%u,r%u lfsux fr%u,r%u,r%u lfdx fr%u,r%u,r%u lfdux fr%u,r%u,r%u lfiwax fr%u,r%u,r%u lfiwzx fr%u,r%u,r%u dis_fp_load(ppc)(opc2) dis_fp_load(ppc)(opc1) rlwimi%s r%u,r%u,%d,%d,%d rlwinm%s r%u,r%u,%d,%d,%d slwi%s r%u,r%u,%d srwi%s r%u,r%u,%d rlwnm%s r%u,r%u,r%u,%d,%d rldcl%s r%u,r%u,r%u,%u rldcr%s r%u,r%u,r%u,%u rldic%s r%u,r%u,%u,%u srdi%s r%u,r%u,%u rldicl%s r%u,r%u,%u,%u sldi%s r%u,r%u,%u rldicr%s r%u,r%u,%u,%u rldimi%s r%u,r%u,%u,%u dis_int_rot(ppc)(opc2) dis_int_rot(ppc)(opc1) vclzb v%d,v%d vclzh v%d,v%d vclzw v%d,v%d vclzd v%d,v%d vpopcntb v%d,v%d vpopcnth v%d,v%d vpopcntw v%d,v%d vpopcntd v%d,v%d vgbbd v%d,v%d vbpermd v%d,v%d,v%d lbz r%u,%d(r%u) lbzu r%u,%d(r%u) lha r%u,%d(r%u) lhau r%u,%d(r%u) lhz r%u,%d(r%u) lhzu r%u,%d(r%u) lwz r%u,%d(r%u) lwzu r%u,%d(r%u) dis_int_load(ppc)(Ox1F,b0) lbzux r%u,r%u,r%u lbzx r%u,r%u,r%u lhaux r%u,r%u,r%u lhax r%u,r%u,r%u lhzux r%u,r%u,r%u lhzx r%u,r%u,r%u lwzux r%u,r%u,r%u lwzx r%u,r%u,r%u ldux r%u,r%u,r%u ldx r%u,r%u,r%u lwaux r%u,r%u,r%u lwax r%u,r%u,r%u dis_int_load(ppc)(opc2) ld r%u,%d(r%u) ldu r%u,%d(r%u) lwa r%u,%d(r%u) lq r%u,%d(r%u) dis_int_load(ppc)(opc1) ,1dis_fp_scr(ppc)(instr) mtfsb1%s crb%d dis_fp_scr(ppc)(instr,mcrfs) mcrfs crf%d,crf%d mtfsb0%s crb%d mtfsfi%s crf%u,%d%s mffs%s fr%u mffsce fr%u mffscdrn fr%u,fr%u mffscdrni fr%u,%u mffscrn fr%u,fr%u mffscrni fr%u,%u mffsl fr%u mtfsf%s %d,fr%u (L=1) mtfsf%s %d,fr%u dis_fp_scr(ppc)(opc2) dis_av_multarith(ppc)(instr) vmhaddshs v%d,v%d,v%d,v%d vmhraddshs v%d,v%d,v%d,v%d vmladduhm v%d,v%d,v%d,v%d vmsumudm v%d,v%d,v%d,v%d vmsumubm v%d,v%d,v%d,v%d vmsummbm v%d,v%d,v%d,v%d vmsumuhm v%d,v%d,v%d,v%d vmsumuhs v%d,v%d,v%d,v%d vmsumshm v%d,v%d,v%d,v%d vmsumshs v%d,v%d,v%d,v%d dis_av_multarith(ppc)(opc2) stb r%u,%d(r%u) stbu r%u,%d(r%u) sth r%u,%d(r%u) sthu r%u,%d(r%u) stw r%u,%d(r%u) stwu r%u,%d(r%u) dis_int_store(ppc)(0x1F,b0) stbux r%u,r%u,r%u stbx r%u,r%u,r%u sthux r%u,r%u,r%u sthx r%u,r%u,r%u stwux r%u,r%u,r%u stwx r%u,r%u,r%u stdux r%u,r%u,r%u stdx r%u,r%u,r%u dis_int_store(ppc)(opc2) std r%u,%d(r%u) stdu r%u,%d(r%u) stq r%u,%d(r%u) dis_int_store(ppc)(opc1) vclzlsbb %d,v%d vctzlsbb %d,v%d vnegw v%d,%d,v%dvnegd v%d,%d,v%dvprtybw v%d,v%dvprtybd v%d,v%dvprtybq v%d,v%dvextsb2w v%d,%d,v%dvextsh2w v%d,%d,v%dvextsb2d v%d,%d,v%dvextsh2d v%d,%d,v%dvextsw2d v%d,%d,v%dvctzb v%d,v%dvctzh v%d,v%dvctzw v%d,v%dvctzd v%d,v%dalb%s%s 0x%llx b%s%s 0x%x bc%s%s 0x%x, 0x%x, 0x%x bcctr%s 0x%x, 0x%x blr bclr%s 0x%x, 0x%x dis_int_branch(ppc)(opc2) dis_int_branch(ppc)(opc1) dis_av_pack(ppc)(instr) vpkuhum v%d,v%d,v%d vpkuwum v%d,v%d,v%d vpkuhus v%d,v%d,v%d vpkuwus v%d,v%d,v%d vpkshus v%d,v%d,v%d vpkswus v%d,v%d,v%d vpkshss v%d,v%d,v%d vpkswss v%d,v%d,v%d vpkpx v%d,v%d,v%d vpkudum v%d,v%d,v%d vpkudus v%d,v%d,v%d vpksdus v%d,v%d,v%d vpksdss v%d,v%d,v%d dis_av_pack(ppc)(vA_addr) vupkhsb v%d,v%d vupkhsh v%d,v%d vupklsb v%d,v%d vupklsh v%d,v%d vupkhpx v%d,v%d vupklpx v%d,v%d vupkhsw v%d,v%d vupklsw v%d,v%d dis_av_pack(ppc)(opc2) zdis_fp_round(ppc)(instr) fcfids%s fr%u,fr%u fcfidus%s fr%u,fr%u frsp%s fr%u,fr%u fctiw%s fr%u,fr%u fctiwz%s fr%u,fr%u fctiwu%s%s fr%u,fr%u fctid%s fr%u,fr%u fctidz%s fr%u,fr%u fctidu%s%s fr%u,fr%u fcfid%s fr%u,fr%u fcfidu%s fr%u,fr%u frin%s fr%u,fr%u friz%s fr%u,fr%u frip%s fr%u,fr%u frim%s fr%u,fr%u dis_fp_round(ppc)(opc2) andi. r%u,r%u,0x%x andis r%u,r%u,0x%x ori r%u,r%u,0x%x oris r%u,r%u,0x%x xori r%u,r%u,0x%x xoris r%u,r%u,0x%x extswsli%s r%u,r%u,%u and%s r%u,r%u,r%u andc%s r%u,r%u,r%u cntlzw%s r%u,r%u eqv%s r%u,r%u,r%u extsb%s r%u,r%u extsh%s r%u,r%u nand%s r%u,r%u,r%u nor%s r%u,r%u,r%u mr r%u,r%u or%s r%u,r%u,r%u orc%s r%u,r%u,r%u xor%s r%u,r%u,r%u extsw%s r%u,r%u cntlzd%s r%u,r%u cmpb r%u,r%u,r%u mftgpr r%u,fr%u mffgpr fr%u,r%u popcntd r%u,r%u popcntw r%u,r%u popcntb r%u,r%u bpermd r%u,r%u,r%u dis_int_logic(ppc)(opc2) dis_int_logic(ppc)(opc1) xsaddqp v%d,v%d,v%d xsaddqpo v%d,v%d,v%d xsmulqp v%d,v%d,v%d xsmulqpo v%d,v%d,v%d xsmaddqp v%d,v%d,v%d xsmaddqpo v%d,v%d,v%d xsmsubqp v%d,v%d,v%d xsmsubqpo v%d,v%d,v%d xsnmaddqp v%d,v%d,v%d xsnmaddqpo v%d,v%d,v%d xsnmsubqp v%d,v%d,v%d xsnmsubqpo v%d,v%d,v%d xssubqp v%d,v%d,v%d xssubqpo v%d,v%d,v%d xsdivqp v%d,v%d,v%d xsdivqpo v%d,v%d,v%d xssqrtqp v%d,v%d xssqrtqpo v%d,v%d xscvqpuwz v%d,v%d xscvudqp v%d,v%d xscvqpswz v%d,v%d xscvsdqp v%d,v%d xscvqpudz v%d,v%d xscvqpdp v%d,v%d xscvqpdpo v%d,v%d xscvdpqp v%d,v%d xscvqpsdz v%d,v%d dis_av_bcd(ppc)(instr) bcdadd. v%d,v%d,v%d,%u bcdsub. v%d,v%d,v%d,%u bcds. v%d,v%d,v%d,%d bcdsr. v%d,v%d,v%d,%d bcdus. v%d,v%d,v%d,%d increment_BCDstring32_helperbcdctsq v%d, v%d bcdcfsq v%d, v%d, %d bcdctz. v%d,v%d,%d convert_to_zoned_helperbcdctn. v%d,v%d convert_to_national_helperbcdcfz. v%d,v%d,%d convert_from_zoned_helperbcdcfn. v%d,v%d,%d convert_from_national_helperbcdsetsgn. v%d,v%d,%d dis_av_bcd(ppc)(opc2) mtcrfmtocrfdis_proc_ctl(ppc)(opc1|b%d) mcrxr crf%d mfcr r%u mfocrf r%u,%u mfxer r%u mfspr r%u (DSCR) mflr r%u mfctr r%u mfspr r%u (TFHAR) mfspr r%u (TFIAR) mfspr r%u (TEXASR) mfspr r%u (TEXASRU) mfspr r%u (PSPB) mfspr r%u (PPR) mfspr r%u (PPR)32 mfvrsave r%u mfspr r%u, SPRG3(readonly) ppcg_dirtyhelper_MFTBmfspr r%u,%uppc32g_dirtyhelper_MFSPR_287mftbu r%umftb r%umftbl r%u%s 0x%x,r%u mtxer r%u mtspr r%u (DSCR) mtlr r%u mtctr r%u mtvrsave r%u mtspr r%u (TFHAR) mtspr r%u (TFIAR) mtspr r%u (TEXASR) mtspr r%u (PSPB) mtspr r%u (PPR) mtspr r%u (PPR32) mfvsrd r%u,vsr%d mfvsrwz r%u,vsr%d mtvsrd vsr%d,r%u mtvsrwa vsr%d,r%u mtvsrwz vsr%d,r%u dis_proc_ctl(ppc)(opc2) ldpx fr%u,r%u,r%u stdpx fr%u,r%u,r%u dis_fp_pair(ppc)(0x1F,b0) lfdp fr%u,%d(r%u) lxsd v%u,%u(r%u) lxssp v%u,%u(r%u) stfdp fr%u,%d(r%u) lxv v%u,%u(r%u) stxv v%u,%u(r%u) stxsd v%u,%u(r%u) stxssp v%u,%u(r%u) dis_fp_pair(ppc)(instr) dis_vx_store(ppc)(instr) stxsiwx %d,r%u,r%u stxvx %u,r%u,r%u stxvl %u,r%u,r%u stxvll %u,r%u,r%u stxsspx %u,r%u,r%u stxsdx %u,r%u,r%u stxsibx %u,r%u,r%u stxsihx %u,r%u,r%u stxvd2x %u,r%u,r%u stxvw4x %u,r%u,r%u stxvb8x %u,r%u,r%u stxvb16x %u,r%u,r%u dis_vx_store(ppc)(opc2) lwdis_memsync(ppc)(0x13,opc2) isync eieio mbar %u lwarx r%u,r%u,r%u,EH=%u lbarx r%u,r%u,r%u,EH=%u lharx r%u,r%u,r%u,EH=%u dis_memsync(ppc)(stwcx.,b0) stwcx. r%u,r%u,r%u dis_memsync(ppc)(stbcx.,b0) stbcx. r%u,r%u,r%u sthcx. r%u,r%u,r%u %ssync ldarx r%u,r%u,r%u,EH=%u dis_memsync(ppc)(stdcx.,b0) stdcx. r%u,r%u,r%u lqarx r%u,r%u,r%u,EH=%u dis_memsync(ppc)(stqcx.,b0) stqcx. r%u,r%u,r%u dis_memsync(ppc)(opc2) dis_memsync(ppc)(opc1) oaddic r%u,r%u,%d addic. r%u,r%u,%d li r%u,%d addi r%u,r%u,%d lis r%u,%d addis r%u,r%u,0x%x mulli r%u,r%u,%d subfic r%u,r%u,%d add%s%s r%u,r%u,r%u addc%s%s r%u,r%u,r%u adde%s%s r%u,r%u,r%u addex r%u,r%u,r%u,%d addex instruction addme%s%s r%u,r%u,r%u addze%s%s r%u,r%u,r%u divw%s%s r%u,r%u,r%u divwu%s%s r%u,r%u,r%u mulhw%s r%u,r%u,r%u mulhwu%s r%u,r%u,r%u mullw%s%s r%u,r%u,r%u neg%s%s r%u,r%u subf%s%s r%u,r%u,r%u subfc%s%s r%u,r%u,r%u subfe%s%s r%u,r%u,r%u subfme%s%s r%u,r%u subfze%s%s r%u,r%u mulhd%s r%u,r%u,r%u mulhdu%s r%u,r%u,r%u mulld%s%s r%u,r%u,r%u divd%s%s r%u,r%u,r%u divdu%s%s r%u,r%u,r%u divweu%s%s r%u,r%u,r%u divwe%s%s r%u,r%u,r%u divde%s%s r%u,r%u,r%u divdeu%s%s r%u,r%u,r%u dis_int_arith(ppc)(opc2) dis_int_arith(ppc)(opc1) dis_vx_load(ppc)(instr) lxsiwzx %d,r%u,r%u lxsiwax %d,r%u,r%u lxvx %u,r%u,r%u lxvl %u,r%u,r%u lxvll %u,r%u,r%u lxvwsx %u,r%u,r%u lxsspx %d,r%u,r%u lxsdx %d,r%u,r%u lxsibzx %u,r%u,r%u lxsihzx %u,r%u,r%u lxvd2x %d,r%u,r%u lxvdsx %d,r%u,r%u lxvw4x %u,r%u,r%u lxvh8x %u,r%u,r%u lxvb16x %u,r%u,r%u dis_vx_load(ppc)(opc2) Unrecognized opcode %x sudis_vx_conv(ppc)(instr) dis_vx_conv(ppc)(opc2) xscvdpsxds v%u,v%u xscvdpsxws v%u,v%u xscvdpuxds v%u,v%u xscvsxdsp v%u,v%u xscvsxddp v%u,v%u xscvuxdsp v%u,v%u xscvuxddp v%u,v%u xvcvdpsxws v%u,v%u xvcvdpuxws v%u,v%uxvcvsp%sxws v%u,v%u xscvdpsp v%u,v%u xscvdpspn v%u,v%u xscvdpuxws v%u,v%u xscvspdp v%u,v%u xscvspdpn v%u,v%u xvcvdpsp v%u,v%u xvcvdpuxds v%u,v%u xvcvspdp v%u,v%u xvcvspsxds v%u,v%u xvcvspuxds v%u,v%u xvcvdpsxds v%u,v%u xvcvsxddp v%u,v%u xvcvuxddp v%u,v%u xvcvsxdsp v%u,v%u xvcvuxdsp v%u,v%u xvcvsxwdp v%u,v%u xvcvuxwdp v%u,v%u xvcvsxwsp v%u,v%u xvcvuxwsp v%u,v%u xscmpeqdp v%d,v%d,v%d xscmpgtdp v%d,v%d,v%d xsmaxcdp v%d,v%d,v%d xsmincdp v%d,v%d,v%d dis_vx_misc(ppc)(opc2) xvredpxvrsqrtedpxvrespxvrsqrtespxvmaxspxvminspxvmaxdpxvmindpnpmdis_vxv_misc(ppc)(instr) %s v%d,v%d %s v%d,v%d v%d xvcpsgndp v%d,v%d,v%d xvcpsgnsp v%d,v%d v%d xv%sabsdp v%d,v%d xvnegsp v%d,v%d xvnegdp v%d,v%d xvrdpi%s v%d,v%d xvrspi%s v%d,v%d xvrspic v%d,v%d dis_vxv_misc(ppc)(opc2) xsmindpxsmaxdpxsrsqrtespxsrespxsrsqrtedpxsredpdis_vxs_misc(ppc)(instr) xxspltib v%u,%u xscmpexpdp %u,v%u,v%u xxextractuw v%u,v%u,%u xxinsertw v%u,v%u,%u xsabsdp v%u,v%u xsxexpd %u,v%u xsxsigdp v%u,v%u xscvhpdp v%u, v%u xscvdphp v%u, v%u inst_select = %u xststdcsp %u,v%u,%u xststdcdp %u,v%u,%u xscpsgndp v%d,v%d v%d xsnabsdp v%d,v%d xsrdpi%s v%d,v%d xsrsp v%d, v%d xvtstdcsp v%u,v%u,%u xviexpsp v%d,v%d xsiexpdp v%u,%u,%u xvxexpdp v%d,v%d xvxsigdp v%d,v%d xxbrh v%u, v%u xvxexpsp v%d,v%d xvxsigsp v%d,v%d xxbrw v%u, v%u xxbrd v%u, v%u xvcvhpsp v%d,v%d xvcvsphp v%d,v%d xxbrq v%u, v%u xvtstdcdp v%u,v%u,%u xviexpdp v%d,v%d dis_vxs_misc(ppc)(opc2) dis_vxs_arith(ppc)(instr) xsaddsp v%d,v%d,v%d xssubsp v%d,v%d,v%d xsadddp v%d,v%d,v%d xsdivsp v%d,v%d,v%d xsdivdp v%d,v%d,v%d xsmadd%ssp v%d,v%d,v%d xsmadd%sdp v%d,v%d,v%d xsmsub%ssp v%d,v%d,v%d xsmsub%sdp v%d,v%d,v%d xsnmadd%sdp v%d,v%d,v%d xsnmadd%ssp v%d,v%d,v%d xsnmsub%ssp v%d,v%d,v%d xsnmsub%sdp v%d,v%d,v%d xsmulsp v%d,v%d,v%d xsmuldp v%d,v%d,v%d xssubdp v%d,v%d,v%d xssqrtsp v%d,v%d xssqrtdp v%d,v%d xstdivdp crf%d,v%d,v%d xstsqrtdp v%d,v%d dis_vxs_arith(ppc)(opc2) dis_fp_tests(ppc)(ftdiv) ftdiv crf%d,fr%u,fr%u dis_fp_tests(ppc)(ftsqrt) ftsqrt crf%d,fr%u dis_fp_tests(ppc)(opc2) addsubmuldivmdpadpdis_vxv_dp_arith(ppc)(instr) xv%sdp v%d,v%d,v%d xvsqrtdp v%d,v%d xv%sm%s%s v%d,v%d,v%d xvtsqrtdp cr%d,v%d xvtdivdp cr%d,v%d,v%d dis_vxv_dp_arith(ppc)(opc2) maddmspaspdis_vxv_sp_arith(ppc)(instr) xvaddsp v%d,v%d,v%d xvmulsp v%d,v%d,v%d xvsubsp v%d,v%d,v%d xvdivsp v%d,v%d,v%d xvsqrtsp v%d,v%d xvtsqrtsp cr%d,v%d xvtdivsp cr%d,v%d,v%d dis_vxv_sp_arith(ppc)(opc2) xscpsgnqp v%d,v%d,v%d xscmpoqp %u,v%d,v%u xscmpuqp %u,v%d,v%u xscmpexpqp %u,v%d,v%u xststdcqp %u,v%d,%u xsabsqp v%d,v%d xsxexpqp v%d,v%d xsnabsqp v%d,v%d xsnegqp v%d,v%d xsxsigqp v%d,v%d xsiexpqp v%d,v%d,v%d t(hwcaps_guest & mask32) == 0(hwcaps_guest & mask64) == 0 0x%llx: r3 = client_request ( %%r4 ) r3 = guest_NRADDR r3 = guest_NRADDR_GPR2 IR injection lmw r%u,%d(r%u) stmw r%u,%d(r%u) dis_syslink(ppc)(theInstr) sc ERROR: get_VSX60_opc2() xscmp%sdp crf%d,fr%u,fr%u dis_vx_cmp(ppc)(opc2) addpcis %u,%llu dis_cond_logic(ppc)(opc1) mcrf cr%u,cr%u crand crb%d,crb%d,crb%d crandc crb%d,crb%d,crb%d creqv crb%d,crb%d,crb%d crnand crb%d,crb%d,crb%d crnor crb%d,crb%d,crb%d cror crb%d,crb%d,crb%d crorc crb%d,crb%d,crb%d crxor crb%d,crb%d,crb%d dis_cond_logic(ppc)(opc2) wait %d tbegin. %u tend. %u tsr. %u tcheck. %u tabortwc. %u,%u,%u tabortdc. %u,%u,%u tabortwci. %u,%u,%u tabortdci. %u,%u,%u tabort. %u treclaim. %u trechkpt. dis_int_ldst_str(ppc)(opc1) lswi r%u,r%u,%d lswx r%u,r%u,r%u stswi r%u,r%u,%d stswx r%u,r%u,r%u dis_int_ldst_str(ppc)(opc2) dcbf r%u,r%u dcbst r%u,r%u dcbt r%u,r%u dcbtst r%u,r%u dcbzl r%u,r%u dcbz r%u,r%u icbi r%u,r%u dis_cache_manage(ppc)(opc2) dst%s r%u,r%u,%d dstst%s r%u,r%u,%d dss %d dssall dis_av_datastream(ppc)(opc2) isel r%u,r%u,r%u,crb%u maddhd r%u,r%u,r%u,r%u maddhdu r%u,r%u,r%u,r%u maddld r%u,r%u,r%u,r%u vshasigmaw v%d,v%d,%u,%u vshasigmad v%d,v%d,%u,%u dis_av_hash(ppc)(opc2) !allow_VX0 dres.len == 20xsaddspxsmaddaspxsmaddmspxscmpeqdpxssubspxscmpgtdpxxpermrxsmulspxsmsubaspxxmrghwxscmpgedpxsdivspxsmsubmspxxpermxsadddpxsmaddadpxscmpudpxssubdpxsmaddmdpxscmpodpxsmuldpxsmsubadpxxmrglwxstsqrtdpxsdivdpxsmsubmdpxscmpexpdpxstdivdpxvaddspxvmaddaspxvcmpeqspxvcvspuxwsxvsubspxvmaddmspxvcvspsxwsxvmulspxvmsubaspxvcmpgespxvdivspxvmsubmspxvtdivspxvadddpxvmaddadpxvcmpeqdpxvsubdpxvmaddmdpxvcmpgtdpxvmuldpxvmsubadpxvcmpgedpxvdivdpxvmsubmdpxvtdivdpxsmaxcdpxsnmaddaspxxlandxsmincdpxsnmaddmspxxlandcxsnmsubaspxxlorxsnmsubmspxxlxorxsnmaddadpxxlnorxsnmaddmdpxxlorcxscpsgndpxsnmsubadpxxlnandxsnmsubmdpxxleqvxvnmaddaspxvnmaddmspxvcpsgnspxvnmsubaspxviexpspxvnmsubmspxvnmaddadpxvnmaddmdpxvcpsgndpxvnmsubadpxviexpdpxvnmsubmdpxvcvsxddpxssqrtspxxselxscvdpuxwsxsrdpixssqrtdpxscvdpsxwsxsrdpizxsrdpipxsrdpicxsrdpimxvrspixvsqrtspxvrspizxxspltwxxextractuwxvcvuxwspxvrspipxvtsqrtspxvrspicxxinsertwxvcvsxwspxvrspimxvcvdpuxwsxvrdpixvsqrtdpxvcvdpsxwsxvrdpizxvcvuxwdpxvrdpipxvtsqrtdpxvrdpicxvcvsxwdpxvrdpimxscvdpspxscvdpspnxxrspxscvuxdspxststdcspxscvsxdspxscvdpuxdsxscvspdpxscvspdpnxscvdpsxdsxsabsdpxsxexpdp_xsxigdpxscvuxddpxsnabsdpxststdcdpxscvsxddpxsnegdpxvcvspuxdsxvcvdpspxvcvspsxdsxvabsspxvcvuxdspxvnabsspxvcvsxdspxvnegspxvcvdpuxdsxvcvspdpxvcvdpsxdsxvabsdpxvcvuxddpxvnabsdpxvnegdpop8 == Iop_Add8 || op8 == Iop_Sub8 || op8 == Iop_Mul8 || op8 == Iop_Or8 || op8 == Iop_And8 || op8 == Iop_Xor8 || op8 == Iop_Shl8 || op8 == Iop_Shr8 || op8 == Iop_Sar8 || op8 == Iop_CmpEQ8 || op8 == Iop_CmpNE8 || op8 == Iop_Not8typeOfIRExpr(irsb->tyenv,rot_amt) == Ity_I8typeOfIRExpr(irsb->tyenv, arg1) == Ity_I1typeOfIRExpr(irsb->tyenv, arg2) == Ity_I1typeOfIRExpr( irsb->tyenv, e ) == Ity_I32align == 2 || align == 4 || align == 8 || align == 16typeOfIRTemp(irsb->tyenv, addr) == Ity_I64typeOfIRTemp(irsb->tyenv, addr) == Ity_I32typeOfIRTemp(irsb->tyenv, t) == Ity_I32typeOfIRExpr(irsb->tyenv, src) == Ity_I64typeOfIRExpr(irsb->tyenv, e) == Ity_I8typeOfIRExpr(irsb->tyenv, e) == Ity_V128tyA == Ity_I32 || tyA == Ity_I64typeOfIRExpr(irsb->tyenv,res) == Ity_I32typeOfIRExpr(irsb->tyenv,argL) == Ity_I32typeOfIRExpr(irsb->tyenv,argR) == Ity_I32typeOfIRExpr(irsb->tyenv,oldca) == Ity_I32typeOfIRExpr(irsb->tyenv,res) == Ity_I64typeOfIRExpr(irsb->tyenv,argL) == Ity_I64typeOfIRExpr(irsb->tyenv,argR) == Ity_I64typeOfIRExpr(irsb->tyenv,oldca) == Ity_I64shift == 0 || shift == 8 || shift == 16 || shift == 24typeOfIRExpr(irsb->tyenv, t64) == Ity_I64typeOfIRExpr(irsb->tyenv, t3) == Ity_I64typeOfIRExpr(irsb->tyenv, t2) == Ity_I64typeOfIRExpr(irsb->tyenv, t1) == Ity_I64typeOfIRExpr(irsb->tyenv, t0) == Ity_I64typeOfIRExpr(irsb->tyenv, e) == Ity_D128typeOfIRExpr(irsb->tyenv,addr) == tytypeOfIRExpr(irsb->tyenv, vIn) == Ity_V128vEvn && *vEvn == IRTemp_INVALIDvOdd && *vOdd == IRTemp_INVALIDtypeOfIRExpr(irsb->tyenv,result) == Ity_I32 || typeOfIRExpr(irsb->tyenv,result) == Ity_I64typeOfIRTemp(irsb->tyenv, nia) == Ity_I64typeOfIRTemp(irsb->tyenv, nia) == Ity_I32typeOfIRExpr(irsb->tyenv, t128) == Ity_V128typeOfIRExpr(irsb->tyenv, e) == Ity_F64typeOfIRExpr(irsb->tyenv, e) == Ity_D64dis_dfp_extract_insert(ppc)(opc2) ( size == Ity_I16 ) || ( size == Ity_I32 ) || ( size == Ity_I64 ) || ( size == Ity_F128 )( typeOfIRExpr(irsb->tyenv, mkexpr( src ) ) == Ity_I32 ) || ( typeOfIRExpr(irsb->tyenv, mkexpr( src ) ) == Ity_I64 ) || ( typeOfIRExpr(irsb->tyenv, mkexpr( src ) ) == Ity_F128 )typeOfIRExpr(irsb->tyenv, e) == Ity_I32dis_vx_Scalar_Round_to_quad_integer(ppc)(instr) dis_vx_Scalar_Round_to_quad_integer(ppc)(opc2) typeOfIRExpr(irsb->tyenv, e) == Ity_F128dis_dfp_extract_insertq(ppc)(opc2) typeOfIRExpr(irsb->tyenv, e) == tydis_av_extract_element(ppc)(instr) dis_av_extract_element(ppc)(opc2) typeOfIRExpr(irsb->tyenv,result) == Ity_V128dis_dfp_quantize_sig_rrnd(ppc)(opc2) dis_dfp_quantize_sig_rrndq(ppc)(opc2) typeOfIRExpr(irsb->tyenv, argL0) == Ity_I32typeOfIRExpr(irsb->tyenv, argR0) == Ity_I32typeOfIRExpr(irsb->tyenv, argL0) == Ity_I64typeOfIRExpr(irsb->tyenv, argR0) == Ity_I64typeOfIRExpr(irsb->tyenv, e) == Ity_D32dis_av_polymultarith(ppc)(instr) dis_av_polymultarith(ppc)(opc2=0x%x) dis_av_fp_convert(ppc)(instr) dis_av_fp_convert(ppc)(UIMM_5) dis_av_logic(ppc)(opc1 != 0x4) dis_av_fp_arith(ppc)(vA_addr) dis_av_fp_arith(ppc)(opc2=0x%x) dis_av_arith(ppc)(opc1 != 0x4) dis_int_ldst_rev(ppc)(opc1|b0) dis_int_parity(ppc)(0x1F,opc1:rB|b0) ERROR: dis_dfp_bcd(ppc), undefined opc2 case fnmsubs%s fr%u,fr%u,fr%u,fr%u fnmadds%s fr%u,fr%u,fr%u,fr%u dis_fp_multadd(ppc)(3B: opc2) dis_fp_multadd(ppc)(3F: opc2) ERROR: dis_dfp_bcdq(ppc), undefined opc2 case dis_fp_arith(ppc)(instr,fmul) ( ty_src == Ity_I64 ) || ( ty_src == Ity_I32 )dis_av_procctl(ppc)(opc2,dst) typeOfIRExpr( irsb->tyenv,src ) == Ity_I64typeOfIRExpr(irsb->tyenv,src ) == Ity_I32dis_dfp_significant_digits(ppc)(opc2) wrong dis_dfp_class_test(ppc)(opc2) dis_dfp_exponent_test(ppc)(opc2) dis_vx_permute_misc(ppc)(instr) dis_vx_permute_misc(ppc)(opc2) dis_av_count_bitTranspose(ppc)(instr) dis_av_count_bitTranspose(ppc)(opc2) dis_int_load(ppc)(lbzu,rA_addr|rD_addr) dis_int_load(ppc)(lhau,rA_addr|rD_addr) dis_int_load(ppc)(lhzu,rA_addr|rD_addr) dis_int_load(ppc)(lwzu,rA_addr|rD_addr) dis_int_load(ppc)(lwzux,rA_addr|rD_addr) dis_int_load(ppc)(lhaux,rA_addr|rD_addr) dis_int_load(ppc)(lhzux,rA_addr|rD_addr) dis_int_load(ppc)(ldux,rA_addr|rD_addr) dis_int_load(ppc)(lwaux,rA_addr|rD_addr) dis_int_load(ppc)(ldu,rA_addr|rD_addr) dis_int_load(ppc)(0x3A, opc2) dis_fp_scr(ppc)(instr,mtfsb1) dis_fp_scr(ppc)(instr,mtfsb0) dis_fp_scr(ppc)(instr,mtfsfi) dis_fp_scr(ppc)(mff**) Unrecognized instruction. dis_int_store(ppc)(stbu,rA_addr) dis_int_store(ppc)(sthu,rA_addr) dis_int_store(ppc)(stwu,rA_addr) dis_int_store(ppc)(stbux,rA_addr) dis_int_store(ppc)(sthux,rA_addr) dis_int_store(ppc)(stwux,rA_addr) dis_int_store(ppc)(stdux,rA_addr) dis_av_extend_sign(ppc)(instr) vctzb instruction not supported on non ISA 3.0 platform vctzh instruction not supported on non ISA 3.0 platform vctzw instruction not supported on non ISA 3.0 platform vctzd instruction not supported on non ISA 3.0 platform dis_av_extend_sign(ppc)(Unsupported vector extend sign instruction) bcl 0x%x, 0x%x (a.k.a mr lr,cia+4) dres->jk_StopHere == Ijk_INVALIDdis_int_branch(ppc)(0x13,b11to15)(%d) dis_int_branch(ppc)(bcctr,BO) dis_int_logic(ppc)(cntlzw,rB_addr) dis_int_logic(ppc)(extsb,rB_addr) dis_int_logic(ppc)(extsh,rB_addr) dis_int_logic(ppc)(extsw,rB_addr) dis_int_logic(ppc)(cntlzd,rB_addr) Erorr, dis_vx_Floating_Point_Arithmetic_quad_precision(ppc)(instr) dis_vx_Floating_Point_Arithmetic_quad_precision(0x324 unknown inst_select) dis_vx_Floating_Point_Arithmetic_quad_precision invalid inst_select (ppc)(opc2) dis_vx_Floating_Point_Arithmetic_quad_precision(ppc)(opc2) dis_av_bcd(ppc)(invalid inst_select) dis_proc_ctl(ppc)(mcrxr,b21to22|b11to20) dis_proc_ctl(ppc)(mfspr,SPR)(0x%x) dis_proc_ctl(ppc)(mtspr,SPR)(%u) dis_fp_pair(ppc) ldpx or stdpx: odd frT register dis_fp_pair(ppc) : X-form wrong opc2 dis_fp_pair(ppc) lfdp : odd frT register dis_fp_pair(ppc) : DS-form wrong opc2 dis_fp_pair(ppc) stfdp : odd frT register dis_fp_pair vector load/store (ppc) : DS-form wrong opc2 dis_memsync(ppc)(0x13,b11to25|b0) dis_memsync(ppc)(eieio,b11to20|b0) dis_memsync(ppc)(mbar,b11to20|b0) dis_memsync(ppc)(sync/lwsync,b11to20|b0) dis_memsync(ppc)(sync/lwsync,flag_L) addex instruction, CY = %d is reserved. dis_int_arith(ppc)(addme,rB_addr) dis_int_arith(ppc)(addze,rB_addr) dis_int_arith(ppc)(mulhw,flag_OE) dis_int_arith(ppc)(mulhwu,flag_OE) dis_int_arith(ppc)(neg,rB_addr) dis_int_arith(ppc)(subfme,rB_addr) dis_int_arith(ppc)(subfze,rB_addr) dis_int_arith(ppc)(mulhd,flagOE) dis_int_arith(ppc)(mulhdu,flagOE) ( size == Ity_I16 ) || ( size == Ity_I32 ) || ( size == Ity_I64 ) || ( size == Ity_V128 )_do_vsx_fp_roundToInt(ppc)(opc2)typeOfIRExpr(irsb->tyenv, src ) == Ity_I32_get_vsx_rdpi_suffix(ppc)(opc2)dis_vxv_misc(ppc)(vrspi)(opc2) dis_vxv_scalar_extract_exp_sig invalid inst_select (ppc)(opc2) dis_vxs_misc(ppc) Invalid instruction selection The impossible happened: dis_vxv_dp_arith(ppc)The impossible happened: dis_vxv_sp_arith(ppc)dis_vx_scalar_quad_precision(ppc)(instr) dis_vx_scalar_quad_precision invalid inst_select (ppc)(opc2) dis_vx_scalar_quad_precision(ppc)(opc2) guest_arch == VexArchPPC32 || guest_arch == VexArchPPC64disInstr(ppc): Little Endian 32-bit mode is not supported disInstr(ppc): old ppc32 instruction magic detected. Code might clobber r0. disInstr(ppc): source needs to be recompiled against latest valgrind.h. branch-and-link-to-noredir r12 branch-and-link-to-noredir r11 dis_int_ldst_mult(ppc)(lmw,rA_addr) Error: undefined opcode 0x %x, the instruction = 0x %x dis_cond_logic(ppc)(crbD|crbA|crbB != 0) typeOfIRExpr(irsb->tyenv,bit) == Ity_I32dis_transactional_memory(ppc): unrecognized instruction dis_cache_manage(ppc)(dcbzl not supported by host) dis_cache_manage(ppc)(opc1|b0) lineszB == 16 || lineszB == 32 || lineszB == 64 || lineszB == 128dis_av_datastream(ppc)(instr) dis_av_datastream(ppc)(opc2,dst) dis_int_mult(ppc): unrecognized instruction disInstr(ppc): found the Floating Point instruction 0x%x that can't be handled by Valgrind on this host. This instruction requires a host that supports Floating Point instructions. disInstr(ppc): found an AltiVec or an e500 instruction 0x%x that can't be handled by Valgrind. If this instruction is an Altivec instruction, Valgrind must be run on a host that supportsAltiVec instructions. If the application was compiled for e500, then unfortunately Valgrind does not yet support e500 instructions. disInstr(ppc): found the instruction 0x%x that is defined in the Power ISA 2.06 ABI but can't be handled by Valgrind on this host. This instruction requires a host that supports the ISA 2.06 ABI. disInstr(ppc): found the General Purpose-Optional instruction 0x%x that can't be handled by Valgrind on this host. This instruction requires a host that supports the General Purpose-Optional instructions. disInstr(ppc): found the Graphics-Optional instruction 0x%x that can't be handled by Valgrind on this host. This instruction requires a host that supports the Graphic-Optional instructions. disInstr(ppc): found the decimal floating point (DFP) instruction 0x%x that can't be handled by Valgrind on this host. This instruction requires a host that supports DFP instructions. disInstr(ppc): found the Power 8 instruction 0x%x that can't be handled by Valgrind on this host. This instruction requires a host that supports Power 8 instructions. disInstr(ppc): found the Power 9 instruction 0x%x that can't be handled by Valgrind on this host. This instruction requires a host that supports Power 9 instructions. disInstr(ppc): unhandled instruction: 0x%x primary %d(0x%x), secondary %u(0x%x) xxbr[h|w|d|q]|xvxexpdp|xvxexpsp|xvxsigdp|xvxsigsp|xvcvhpsp|xvcvsphp|xscvdphp|xscvhpdpputXER_BCputXER_CA32putGSTgen_vpopcntd_mode32expand16Sx8mkQNarrow64Sto32mkV128from4x64SbreakV128to4x64SmkQNarrow64Uto32mkV128from4x64Uexpand8Ux16expand8Sx16expand16Ux8gen_POPCOUNTdis_int_logicputIRegintegerGuestRegOffsetgetIRegputVRegdis_cache_managegenerate_stsw_sequencegenerate_lsw_sequencegen_byterev32gen_byterev16gen_SIGBUS_if_misalignedputXER_SOset_XER_OV_64set_XER_OV_OV32_32set_XER_CA_64putXER_CAset_XER_CA_32mk64lo32Uto64mk64lo32Sto64putXER_OV32putXER_OVmake_redzone_AbiHintaddr_aligndis_branchputCRbitputDReg_pairputF128RegputFReggetFRegbreakV128to4x64Uset_AV_CR6handle_SNaN_to_QNaN_32breakV128to4x32breakV128to4xF64mkNOT1mkOR1putFPCCputGST_maskedputGST_fieldputCgenerate_store_FPRFmkAND1putVSRegvsxGuestRegOffsetputDReg32putDRegfloatGuestRegOffsetgetDRegdo_trapgetCR321getCR0storemkSzOpputCR0putCR321set_CR0ROTLdisInstr_PPC_WRKdisInstr_PPCnewTempsetup_value_check_args $,:@DHL`dh  $0@DL`dt $(DHdh $@D`d4024HJPRTVjpr2PTp02PRpr?89CGNUzRx Cd0DPH+L_`Fldx,Ud_,IBD  HEL $`BFD AIE$BAL `IE($BBA JE(PBGG ` FEE \|BBB E(D0F (E EGBH  (E EBBF J(E EGBlBBE D(F0G (I EBBL  (D EBBH Z (I EBBL e(I EBB,LIED  EBH (|BGG ` FEE (BFD Y IEM 4BBB G(L0(I EBBL BBB A(D0~ (I BBBH  (J BBBJ L\:BBB B(A0} (E GBBJ  (E BBBI HBEB B(A0C8F@ 8A0D(B BBBM 8BDB A(F0 (I EBBL 44BBB D(O0(D EBB(lBEA GE?AU J 9GU L I4gHu K _Hh P ( AAF a ADJ (LAAF a ADJ xDN(BAD | AEG *(BGG E AEE HZ N Hc M A G @HZ N <`OIKH D(D0 (A EBBJ HZ N YIH8 BBA C(Q0T (L ABBJ HHBHB E(D0C8F`5 8A0A(B BBBA (oAAF q IDJ 8BBE A(D0K (G EBBG ,BEA  BBE 4,BGB A(D0](I BBB<dBBJ A(D0 (D BBBI ,?BGA  JEN 8oBBB A(L0 (J BBBG 8 oBEE G(G0 (I EBBF 8L oBBA D(K0  (A DBBH $ XHS M Q O H8 _BBB I(D0  (I EBBO L BBB A(F0s (D BBBF @ (G EBBH L< oBBB D(A0o (D BBBD  (D EGBO H BBB B(I0A8F@ 8C0A(B BBBM H BBB A(H0b (E BBBL T(G EBB<$ BBB B(A0o (E BBBM 8d oBEE G(G0 (I EBBF 8 BIA  DJN  CBJ , BGA  JEH , BAD h ABN << BBB J(A0 (E BBBF L| BEE B(A0D8O 8A0A(B BBBG H BBB B(D0I8D@F 8F0D(B BBBO 8 7BBB I(D0x (G BBBH 8T BBD I(G0e (A DBBJ 8 BBD I(G0e (A DBBJ 8 BBD I(G0e (A DBBJ 8BBD I(G0e (A DBBJ DH L HdBBB B(I0D8D` 8A0A(E BBBK HBBB E(D0L8Dp 8A0A(E BBBF LBBB B(D0I8DI 8A0D(B BBBI 8LBBA H(F0- (D ABBG LBBB A(D0 (A EBBE l (A BBBE HBBB B(A0D8Dp 8A0D(B BBBM H$OBBB E(D0I8GPP 8A0D(B BBBL HpBBB E(D0I8GP 8A0D(B BBBH HBBB E(D0I8GP 8A0D(B BBBH `BBB B(A0A8KP 8F0A(B BBBB r 8C0A(B BBBB HlBBB E(D0I8GP 8A0D(B BBBL HBEF H(K0K8ZP 8F0A(B BBBD HoBEI I(K0G8ZP 8F0A(B BBBJ `PBBB B(A0A8K@j 8C0A(B BBBE  8A0A(B BBBD `BBB B(A0A8K@j 8C0A(B BBBE  8F0A(B BBBG H7 BBB B(I0D8DP 8F0D(B BBBH HdBBB B(A0D8Gp6 8G0D(B BBBK HBBB B(A0A8KP 8F0A(B BBBI HBBB B(A0A8KPe 8F0A(B BBBG LH BBB B(I0C8D 8D0D(B BBBI zD_H%BBB B(A0A8KP' 8D0A(B BBBG <BBE D(A0 (A EBBI x<9BEI B(D0E8OP 8C0A(B BBBJ R 8C0A(B BBBB  8F0A(B BBBE HnBBB B(A0A8KP  8D0A(B BBBD ,KBKE K DBM H4BBH E(A0C8J` 8A0A(B BBBA d-BBB B(A0A8KP 8F0A(B BBBG  8A0A(B BBBB HBBB B(A0D8DP$ 8A0D(B BBBN |4BBB B(A0A8KP 8A0A(B BBBD z 8C0A(B BBBB v 8F0A(B BBBK H.BBB B(A0A8KP 8D0A(B BBBG HBBB B(A0A8KP 8D0A(B BBBJ dL9BBE E(A0D8Fp' 8C0A(B BBBD  8F0A(B BBBK LBBB E(A0C8Ds 8D0A(B BBBE HBBB B(A0A8FP7 8F0A(B BBBJ HP'BBB B(A0A8KP 8D0A(B BBBF HoBBB E(H0K8UP 8F0A(B BBBH BBB B(A0C8N@~ 8C0A(B BBBD R 8C0A(B BBBJ b 8F0A(B BBBG E 8F0A(B BBBD |BBB E(H0E8O@ 8F0A(B BBBJ R 8C0A(B BBBB B 8C0A(B BBBB dBBB B(A0A8K@ 8F0A(B BBBF t 8A0A(B BBBB (|vADF ~ ADJ dBBB B(A0A8KP 8A0A(B BBBB v 8F0A(B BBBK |BEF E(H0I8O@ 8F0A(B BBBG  8A0A(B BBBJ k 8F0A(B BBBF d'BBB B(A0A8KP? 8A0A(B BBBB  8F0A(B BBBH `DBEF E(H0I8O@ 8A0A(B BBBB ~ 8F0A(B BBBC L\q(BBB B(A0A8N 8A0A(B BBBG `BBB B(A0 (E BBBH  (J EBBH  (E GBBH 8BEE D(G0 (A EBBI |L8 BBB E(H0A8Fp( 8F0A(B BBBG  8F0A(B BBBJ L 8A0A(B BBBJ <oIBE E(D0 (B EBBE 8 BEH G(I0 (A EBBI |HBBB B(A0C8FP 8A0A(B BBBB  8F0A(B BBBF  8F0A(B BBBE |BBB B(A0C8FP 8F0A(B BBBJ  8A0A(B BBBB  8F0A(B BBBA LH (BBB B(A0C8F" 8A0A(B BBBB L CBBB B(A0H8G 8A0A(B BBBH L kBBB B(A0A8K 8F0A(B BBBH H8!BBB B(A0A8KP 8D0A(B BBBA H! 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@ B( @Ch E F  H I@ J K N pQX S U W YH[h]c0iPnp r(0xt{ p0@TP`hL@@p@088``P`T P@ `p0 $*`@.VZP[0ejLkPsL  { P `3L304440$5T555086px6p6,7%\7 &7&7' 8/\80W8p8 H9x99@,::;X;`.symtab.strtab.shstrtab.rela.text.data.bss.rodata.str1.1.rodata.str1.8.rela.rodata.rela.data.rel.ro.local.rodata.cst4.rodata.cst8.note.GNU-stack.note.gnu.property.rela.eh_frame @t@xkp &^t,`t,12`tV[@2(TVO@uaO \@` t@ZHZPZPZ pZ;@p8h4 x0:/571 0 0 0 644 27136 ` ELF>f@@HHHcHfDHfD2HDH)@΍tH H5H=@uH))H H5H=A1щH=H=ff.HLIcL>1H@ux)փ19H1 H@H1H@19H@u81Hf.H H5H=H H5H=A1щH=H=ff.HnHHc@19H@ʅ19u19ЩtH CH5H=oH JH5H=?H QH5H=H1H@19@H <H5H=H 2H5H=A1щH=H=ff.H~LIcL>@ȃ:HDȃtH H5H=H H11!DH)11!fDH11!uPH)1)1!ȩ)H H5H=@H H5H=H H5H=H H5H=A1щH=H=ff.HLIc@ʁ@@Ѓ% H ׁ ։@@tH QH5H=H% 1111H! ȉ ȉ fA1A)9191D1H! D ȉ D< E1A1AAD ȅ1911H! ȉ )׃AA)9D 19@1D1H!  @@@ H H5H=D19@tH H5H=H H5H=H CH5H=H JH5H=A1щH=H=ff.99 ff.AWAVAUATUSHt1AAAσ oH HcDHD>H[]A\A]A^A_@|$ |$ DDDH1[1]A\A]A^A_|$ w|$ DDD|$ DDADND1H [1]A\A]A^A_+H1[]A\A]A^A_f.H1[]A\A]A^A_f.H1[]A\A]A^A_f.H1[]A\A]A^A_f.|$ |$ DDDH![1]A\A]A^A_AAЉH=1H=D@uH H DH H fDHH 1H5H=D@uH H DH H fDHH =H5H=D@uH H DH H fDHH IH5H=D@uH H DH H fDHH UH5H=DAVADDAUATUSDt$0DD$8\$@DL$Hl$PD\$XDd$`@uLI II DI M I I I H L\$0L H I I L[]A\A]A^DH hH5H=fAVADDAUATUSDt$0DD$8\$@DL$Hl$PD\$XDd$`@uLI II DI M I I I H L\$0L H I I L[]A\A]A^DH {H5H=fAVADDAUATUSDt$0DD$8\$@DL$Hl$PD\$XDd$`@uLI II DI M I I I H L\$0L H I I L[]A\A]A^DH H5H=fAVADDAUATUSDt$0DD$8\$@DL$Hl$PD\$XDd$`@uLI II DI M I I I H L\$0L H I I L[]A\A]A^DH H5H=fAVADDAUATUSDt$0DD$8\$@DL$Hl$PD\$XDd$`@uLI II DI M I I I H L\$0L H I I L[]A\A]A^DH H5H=fAVADDAUATUSDt$0DD$8\$@DL$Hl$PD\$XDd$`@uLI II DI M I I I H L\$0L H I I L[]A\A]A^DH H5H=fAVADDAUATUSDt$0DD$8\$@DL$Hl$PD\$XDd$`@uLI II DI M I I I H L\$0L H I I L[]A\A]A^DH H5H=fHDD\$DD$DT$ @u.I H HI M H H H M LfDH H5H=HDD\$DD$DT$ @u.I H HI M H H H M LfDH H5H=@uH H DH H fDHH H5H=D@uH H DH H fDHH H5H=DAWAVAUATIUSHH>HIAθHH|uH5LH DpHAF9H@H9IT:u9ruHR:uցzuHR: uHR:uzuHX[]A\A]A^A_H@HkLc8E1HL[]A\A]A^A_H5LDH8 uH@Lc8uxtxL{DxuLLSLsHLILUH1HHL+HHLH[H]A\A]A^A_@H5LH8 H@Lc8xxHkLk xHIHLHLHILHHHLHILHLHxxxxxxx"Sx2^xax\x$xx7xULxEPxx@!xPx)xHHHIHHHIHHH1HHIHLLIHHLHLHH[]A\A]A^A_LH'H[H]A\A]A^A_LH+H5tYH MH5H=HLOLHQLHOwHLQgH5Lt\H 9H5H=HLU%LLHSLHHLSH5LH kH5H=HLSLsHHIZ1HH'HwHLHIHHLHILHLH1HH+H1HIHHHL'H뷿HIHHHLH@HIHIHHHLHLHHIHHHHIHHHIHHHHHIHIfDHwHWTOPDWLqL Ic4L>DE1сEADAA A D DOXAA EtAw\tAO`tAWdtAGhtADA0GDAEHÉ1D щMAA A D ZfDD%Bf.AE1DEA1AED1D1!A D%D EE1DA)D9A1AD9D1D1!A D%D fD<4 1DE1AAAAE ȅt1A9D11D !\@D։E1)΃AA)9ADA%A 1D9DD1D1D !DE1%EAA D H H5H=f1D9wH H5H=H H5H=H CH5H=H QH5H=H JH5H=AH=D1H=HHGHGHGHG HG(HG0HG8HG@HGHHGPHGXHG`HGhHGpHGxHLJHLJHLJHLJHLJHLJHLJHLJHLJHLJHLJHLJHLJHLJHLJHLJHLJHLJHLJHLJHLJ HLJ(HLJ0HLJ8HLJ@HLJHHLJPHLJXHLJ`HLJhHLJpHLJxHLJHLJfD;~?@1tC~ G~3~ 7~Ӄ#' Ѓ<D DHTlptx|priv/guest_arm_helpers.c(oldC & ~1) == 0armg_calculate_flags_narmg_calculate_flags_z(shco & ~1) == 0(cc_dep3 & ~3) == 0armg_calculate_flag_c(oldV & ~1) == 0armg_calculate_flag_varmg_calculate_condition(ARM)0 == (((HWord)res) & (8-1))armg_calculate_conditionarity == 4armg_calculate_flag_n( op=%u, dep1=0x%x, dep2=0x%x, dep3=0x%x ) armg_calculate_flags_z( op=%u, dep1=0x%x, dep2=0x%x, dep3=0x%x ) armg_calculate_flag_c( op=%u, dep1=0x%x, dep2=0x%x, dep3=0x%x ) armg_calculate_flag_v( op=%u, dep1=0x%x, dep2=0x%x, dep3=0x%x ) armg_calculate_condition(ARM)( %u, %u, 0x%x, 0x%x, 0x%x ) guest_arm_spechelperarmg_dirtyhelper_VMULLP64armg_dirtyhelper_SHA1Harmg_dirtyhelper_SHA256SU0armg_dirtyhelper_SHA1SU1armg_dirtyhelper_SHA256SU1armg_dirtyhelper_SHA256H2armg_dirtyhelper_SHA256Harmg_dirtyhelper_SHA1SU0armg_dirtyhelper_SHA1Marmg_dirtyhelper_SHA1Parmg_dirtyhelper_SHA1Carmg_dirtyhelper_AESIMCarmg_dirtyhelper_AESMCarmg_dirtyhelper_AESDarmg_dirtyhelper_AESEarmg_calculate_flag_zarmg_calculate_flag_narmg_calculate_flag_varmg_calculate_flag_cGNUzRx 0De G F J G I F J A O <PDg E X H K E G I K E K E U K $Hk E  I K E 4Hr F v J I O F R S U S U 8"H] K I W [ e ` ` I W M S ,@FBB B(A0F8GPz 8F0A(B BBBE a 8C0C(B DBED y 8C0C(B DBED I 8C0A(B BBBK I 8C0A(B BBBK I 8C0A(B BBBK I 8C0A(B BBBK a 8E0C(B EBBA 4KlHKl\KlpKl<FKB A(A0b (A BBBJ <FKB A(A0b (A BBBJ <FKB A(A0b (A BBBJ <DFKB A(A0b (A BBBJ <FKB A(A0b (A BBBJ <FKB A(A0b (A BBBJ <FKB A(A0b (A BBBJ DoHf b `oHf b |KlKlFBB B(D0A8D@ 8A0A(B BBBL _ 8D0A(B BBBD  8G0D(B BBBI  8A0A(B BBBE T 8F0D(B BBBE TH A pR 0F_`x@`@' @Yr`@ !&+0*5H:A?XDiIN}SY_e kqw}     "1 KG_ KuP K K  6OP f`8Uon0oKK %@:DP]jv  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HH8DAMQDH$AQDD$PH $DH¾X^DDH}pHDIPH-LT$PDH3pA+|$EADDHH=17|$0]AS|$PH锤oػD$"݁ ]   r$x|$PI<$|$PHƿDLHH=H3ڃ AăAƒE9c݉ؾ HH8DA:ODH$.ODD$PH $DH¾E\DDHjnHDINH+LT$PDH nsA+|$tCADDHH=1DDHIHHH8=LDE1AH=Hڃ AăA׃ ݃9#TDAMDH$MDD$PH $DH¾ZDDHlMDIvMH(LT$PDHl A+|$ BADDHH=1铧HD$p|$(DDHDD$D$HD$8MD$DD$I ڃ AăA׃݃9RDA{LDH$oLDD$PH $DH¾YDDHk4LDI)LH'LT$PDHikA+|$@ADDHH=1FfD|$lr"{T$0t$hDDD$PADH yAIH|$pE-H51DT$D$鼸H=HߤH=1鄥|$E1A?1H=H1A%cD$ D!بE3D$HH8DADL%IDD$PLDH¾uWD|$0HiD$.H @H5H=sH=1E1AA%b AܾT$PDHhR|$Y>DH=H1DT$PHhDT$ |$h|$0ILHDHH=HD$= AAA܉A AAA|$@A@YPؿ $NAND$N|$UHDD$HD5>D=HDH">DD$$DǍ4[H@H#yDHHڿHH=T$PDH%gx|$DN@1HD$ HHD$HT$HLD$ T$PHLxIAFljD$0?HD$ HH-HD$HT$HLD$ T$PHLI$ $-u7L|$S4LD$8DHHH=1ڙH FH5H=f.AĉAAAA„A HH>DI>L?HHڿHHT$PDH]=L|$=3AEDHLH=1ØHD$pt$(DHHD$8?HHH8D$(ԜHH8B<D$ |$(HH=HAFD$0AAF<|$ HH=H;HH8D$HH8|$(D$H1HD$@HHD$(HT$(HDD$PHL$@|$HI|$DH[|$ HD$ HH-HD$HT$HDL$HDD$PHL$ HDDL$VIDL$DA~Hu[WH XH5H=HD$| xHHHHH8=JHDE1H=AHA%D\$H+HH8D$0HH8AؙHH8D$(HH8AHH8D$[HH8\$8|$ ۉ$4:|$0HƁ?H=H|$:DHH=HD9HD$@9HT$@H|$(HH=HD|$0ILH|$(ILHDHH=HDH|$HH=HDH<$HH=HD\$HA|$\$PHƉ9X<$DHXr|$y- HD$|$8AEH=PD$(sP1ۑxHHHH8=HE1H=AHA%錒D$t$0H==HpHH=HHtHH=HxHHHHH8=ҲHDE1 H=AHA%yHH8D$HH8$eHH8=HH8AHH8AHH8D$(HH8|$ D$05|$HH=H5<$HH=H|$c5HH=HDB5DHH=HD{HI{H<$H|$H$H$CHHڿHLHDHH=HDH\$(HƉH=HDHDD$0HDD$H=H\$P|$HƉSD$DDHcS|$(DD$ ADL$HH=1@A}|$uE9dD9d$0:ET$PDHR|$0a3HDL%IT$PLHyA-O%A1DHH=H|$ I\$0LH‰H=H=IHDLHH=HDDH=0x|$7H5HjD\$P|$(HƉ=T$lADDkw|$H H5H H H5H=LDH#A]DHDD$PDDT$l9kH5H=H ?H5H=H BH5H=DL=HHHT$PDH;Mv|$TD $EDHLH=1vDL=H}HHt_"S"D$HDHD$HT$HHDHD$HT$HDD$HDDD$vlDD$IDH}HLHIHHD$H}HHT$HLL=HH*H ~EH5H=DL=HyHHmH ?H5H=H FH5H=H FH5H=DL=HwHH>HDL=HHڿHH o oT$PDH8)s|$0 aՊarmg_calculate_flag_varmg_calculate_flag_c{nv}{eq}{hs}{lo}{mi}{pl}{vs}{vc}{hi}{ls}{ge}{lt}{gt}{le}{ne}priv/guest_arm_toIR.carmg_calculate_condition__curr_is_ThumbguardT != IRTemp_INVALIDt != IRTemp_INVALID0! __curr_is_Thumbi32i16ff00i64i8%s.%s %c%u, #0x%x0x%x000x%x00000x%x0000000x%xff0x%xffff0x%s f32iregNo < 16dregNo < 32[r%u, #%c%u][r%u, %c r%u]i < 256qregNo < 16fregNo < 64isPlausibleIRType(ty)fregNo < 32armg_calculate_flag_qcloaded != NULLrot >= 0 && rot < 32iregNo >= 0 && iregNo <= 14r15written == Falser15guard == IRTemp_INVALIDr15kind == Ijk_Boringarmg_calculate_flags_nzcvmath_INTERLEAVE_2math_DEINTERLEAVE_2t0 && *t0 == IRTemp_INVALIDt1 && *t1 == IRTemp_INVALIDt2 && *t2 == IRTemp_INVALIDt3 && *t3 == IRTemp_INVALIDr%u, LSR #0(a.k.a. 32)r%u, LSR #%ur%u, ASR #0(a.k.a. 32)r%u, ASR #%ur%u, ROR r#%ur%ur%u, LSL #%uwrite_nzcvq || write_ger%u, LSR r%ur%u, LSL r%ur%u, ASR r%udesc[2 * si + 0] <= 2desc[2 * si + 1] <= 7math_INTERLEAVE_3math_DEINTERLEAVE_3vtb%c.8 d%u, {d%u-d%ud%u}, d%u u0 && u1 && u2 && u3math_DEINTERLEAVE_4r != rNm == nRegsnX <= 16nX > 0i < nXm == nXshift_amt < 32how < 4r%u, RRXr%u, ROR #%u[r%u, %c r%u LSL #%u][r%u, %cr%u, LSR #%u][r%u, %cr%u, ASR #%u][r%u, %cr%u, RRX][r%u, %cr%u, ROR #%u]index*shco == IRTemp_INVALID#0x%xsubaddrv%s%c.%c%d q%u, %c%u, d%u v%saddhn.i%d d%u, q%u, q%u vabal.%c%d q%u, d%u, d%u v%ssubhn.i%d d%u, q%u, q%u vabdl.%c%d q%u, d%u, d%u vml%cl.%c%d q%u, d%u, d%u vqdml%cl.s%d q%u, d%u, d%u vmull.%c%d q%u, d%u, d%u vqdmull.s%d q%u, d%u, d%u stld!condT != IRTemp_INVALIDcondT == IRTemp_INVALIDv%s%u.%d {, d%u[%u]}, [r%u], r%u %s vld%u.%d {d%u[]vrsra.%c%d %c%u, %c%u, #%u vrshr.%c%d %c%u, %c%u, #%u vsra.%c%d %c%u, %c%u, #%u vshr.%c%d %c%u, %c%u, #%u vsri.%d %c%u, %c%u, #%u vsli.%d %c%u, %c%u, #%u vshl.i%d %c%u, %c%u, #%u vqshl.u%d %c%u, %c%u, #%u vqshlu.s%d %c%u, %c%u, #%u vqshl.s%d %c%u, %c%u, #%u vshrn.i%d d%u, q%u, #%u vrshrn.i%d d%u, q%u, #%u vq%sshrn.%c%d d%u, q%u, #%u Uvq%sshrun.s%d d%u, q%u, #%u vmovl.%c%d q%u, d%u vshll.%c%d q%u, d%u, #%u sha1su1armg_dirtyhelper_SHA1SU1sha256su0armg_dirtyhelper_SHA256SU0dbhf64s32u32minmaxold_itstate != IRTemp_INVALIDnew_itstate != IRTemp_INVALIDold_itstate == IRTemp_INVALIDnew_itstate == IRTemp_INVALIDarmg_dirtyhelper_AESEarmg_dirtyhelper_AESDarmg_dirtyhelper_AESMCarmg_dirtyhelper_AESIMCaeseaesdaesmcaesimc%s.8 q%u, q%u ix >= 0 && ix < 7sha1csha1psha1msha1su0sha256hsha256h2sha256su1armg_dirtyhelper_SHA1Carmg_dirtyhelper_SHA1Parmg_dirtyhelper_SHA1Marmg_dirtyhelper_SHA1SU0armg_dirtyhelper_SHA256Harmg_dirtyhelper_SHA256H2armg_dirtyhelper_SHA256SU1%s.8 q%u, q%u, q%u armg_dirtyhelper_SHA1Hsha1harmg_dirtyhelper_VMULLP64vmull%s.p64 q%u, q%u, w%u ldabldahldastlbstlhstl%s r%u, [r%u]tt2 == 16tt2 <= 14dd == 16dd <= 14(tt) <= 14(tt2) <= 14ldrex%s%s r%u, r%u, [r%u] ldrex%s%s r%u, [r%u] strex%s%s r%u, r%u, [r%u] vsel%s.%s %c%u, %c%u, %c%u vrint%c.%s.%s %c%u, %c%u vcvt%c.%s.%s %c%u, %c%u v%snm.%s %c%u, %c%u, %c%u v%snm.f32 %c%u, %c%u, %c%u vcvt%c.%c32.f32 %c%u, %c%u vrint%c.f32.f32 %c%u, %c%u vmull.%c%d q%u, d%u, d%u[%u] vhadd.%c%d %c%u, %c%u, %c%u vqadd.%c%d %c%u %c%u, %c%u vrhadd.%c%d %c%u, %c%u, %c%u vand %c%u, %c%u, %c%u vbic %c%u, %c%u, %c%u vorr %c%u, %c%u, %c%u vmov %c%u, %c%u vorn %c%u, %c%u, %c%u veor %c%u, %c%u, %c%u vbsl %c%u, %c%u, %c%u vbit %c%u, %c%u, %c%u vbif %c%u, %c%u, %c%u vhsub.%c%d %c%u, %c%u, %c%u vqsub.%c%d %c%u, %c%u, %c%u vcgt.%c%d %c%u, %c%u, %c%u vcge.%c%d %c%u, %c%u, %c%u vshl.%c%d %c%u, %c%u, %c%u vqshl.%c%d %c%u, %c%u, %c%u vrshl.%c%d %c%u, %c%u, %c%u vqrshl.%c%d %c%u, %c%u, %c%u vmax.%c%d %c%u, %c%u, %c%u vmin.%c%d %c%u, %c%u, %c%u vabd.%c%d %c%u, %c%u, %c%u vaba.%c%d %c%u, %c%u, %c%u vadd.i%d %c%u, %c%u, %c%u vsub.i%d %c%u, %c%u, %c%u vtst.%d %c%u, %c%u, %c%u vceq.i%d %c%u, %c%u, %c%u vml%c.i%d %c%u, %c%u, %c%u vmul.%c%d %c%u, %c%u, %c%u vp%s.%c%d %c%u, %c%u, %c%u vqdmulh.s%d %c%u, %c%u, %c%u vpadd.i%d %c%u, %c%u, %c%u vadd.f32 %c%u, %c%u, %c%u vsub.f32 %c%u, %c%u, %c%u vpadd.f32 d%u, d%u, d%u vabd.f32 %c%u, %c%u, %c%u vml%c.f32 %c%u, %c%u, %c%u vmul.f32 %c%u, %c%u, %c%u vceq.f32 %c%u, %c%u, %c%u vcge.f32 %c%u, %c%u, %c%u vcgt.f32 %c%u, %c%u, %c%u vacg%c.f32 %c%u, %c%u, %c%u vmin.f32 %c%u, %c%u, %c%u vmax.f32 %c%u, %c%u, %c%u vpmin.f32 d%u, d%u, d%u vpmax.f32 d%u, d%u, d%u vrecps.f32 %c%u, %c%u, %c%u vrsqrts.f32 %c%u, %c%u, %c%u vmovvmvnvorrvbicvext.8 %c%u, %c%u, %c%u, #%u vrev64.%d %c%u, %c%u vrev32.%d %c%u, %c%u vrev16.%d %c%u, %c%u vpaddl.%c%d %c%u, %c%u vcls.s%d %c%u, %c%u vclz.i%d %c%u, %c%u vcnt.8 %c%u, %c%u vmvn %c%u, %c%u vpadal.%c%d %c%u, %c%u vqabs.s%d %c%u, %c%u vqneg.s%d %c%u, %c%u vcgt.%c%d %c%u, %c%u, #0 vcge.%c%d %c%u, %c%u, #0 vceq.%c%d %c%u, %c%u, #0 vcle.%c%d %c%u, %c%u, #0 vclt.%c%d %c%u, %c%u, #0 vabs.%c%d %c%u, %c%u vneg.%c%d %c%u, %c%u vswp %c%u, %c%u vtrn.%d %c%u, %c%u vuzp.%d %c%u, %c%u vzip.%d %c%u, %c%u vmovn.i%d d%u, q%u vqmovun.s%d d%u, q%u vqmovn.s%d d%u, q%u vqmovn.u%d d%u, q%u vshll.i%d q%u, d%u, #%d vrecpe.%c32 q%u, q%u vrecpe.%c32 d%u, d%u vrsqrte.%c32 q%u, q%u vrsqrte.%c32 d%u, d%u vcvt.f32.s32 %c%u, %c%u vcvt.f32.u32 %c%u, %c%u vcvt.s32.f32 %c%u, %c%u vcvt.u32.f32 %c%u, %c%u vdup.%u %c%u, d%u[%u] ezconq == ARMCondALf%smx%s r%u, {d%u-d%u} f%smiax%s r%u!, {d%u-d%u} f%smdbx%s r%u!, {d%u-d%u} f%smd%s r%u, {d%u-d%u} f%smiad%s r%u!, {d%u-d%u} f%smdbd%s r%u!, {d%u-d%u} fmstat%s fmrx%s r%u, fpscr fmxr%s fpscr, r%u vmov%s d%u, r%u, r%u vmov%s r%u, r%u, d%u vmov%s, s%u, s%u, r%u, r%u vmov%s, r%u, r%u, s%u, s%u vmov%s.8 d%u[%u], r%u vmov%s.16 d%u[%u], r%u vmov%s.32 d%u[%u], r%u vmov%s.%c8 r%u, d%u[%u] vmov%s.%c16 r%u, d%u[%u] vmov%s.32 r%u, d%u[%u] fconsts%s s%u #%ufconstd%s d%u #%uvdup.%d q%u, r%u vdup.%d d%u, r%u f%sd%s d%u, [r%u, %c#%u] fmacd%s d%u, d%u, d%u fnmacd%s d%u, d%u, d%u fmscd%s d%u, d%u, d%u fnmscd%s d%u, d%u, d%u fmuld%s d%u, d%u, d%u fnmuld%s d%u, d%u, d%u faddd%s d%u, d%u, d%u fsubd%s d%u, d%u, d%u fdivd%s d%u, d%u, d%u vfnmsd%s d%u, d%u, d%u vfnmad%s d%u, d%u, d%u vfmad%s d%u, d%u, d%u vfmsd%s d%u, d%u, d%u fcmpz%sd%s d%u fcmp%sd%s d%u, d%u fcpyd%s d%u, d%u fabsd%s d%u, d%u fnegd%s d%u, d%u fsqrtd%s d%u, d%u fsitod%s d%u, s%u fuitod%s d%u, s%u ftosi%sd%s s%u, d%u ftoui%sd%s s%u, d%u f%sms%s r%u, {s%u-s%u} f%smias%s r%u!, {s%u-s%u} f%smdbs%s r%u!, {s%u-s%u} fmrs%s r%u, s%u fmsr%s s%u, r%u f%ss%s s%u, [r%u, %c#%u] fmacs%s s%u, s%u, s%u fnmacs%s s%u, s%u, s%u fmscs%s s%u, s%u, s%u fnmscs%s s%u, s%u, s%u fmuls%s s%u, s%u, s%u fnmuls%s s%u, s%u, s%u fadds%s s%u, s%u, s%u fsubs%s s%u, s%u, s%u fdivs%s s%u, s%u, s%u vfnmss%s s%u, s%u, s%u vfnmas%s s%u, s%u, s%u vfmas%s s%u, s%u, s%u vfmss%s s%u, s%u, s%u fcmpz%ss%s s%u fcmp%ss%s s%u, s%u fcpys%s s%u, s%u fabss%s s%u, s%u fnegs%s s%u, s%u fsqrts%s s%u, s%u fsitos%s s%u, s%u fuitos%s s%u, s%u ftosi%ss%s s%u, d%u ftoui%ss%s s%u, d%u fcvtds%s d%u, s%u fcvtsd%s s%u, d%u vcvt.f32.%c32, s%u, s%u, #%d vcvt.f64.%c32, d%u, d%u, #%d vcvt.%c32.f64, d%u, d%u, #%d vcvt.%c32.f32, d%u, d%u, #%d INSN(11,9) == BITS3(1,0,1)tbbtxsmul%c%c%s r%u, r%u, r%u smulw%c%s r%u, r%u, r%u pkh%s%s r%u, r%u, r%u %s usat%s r%u, #0x%04x, %s ssat%s r%u, #0x%04x, %s ssat16%s r%u, #0x%04x, r%u usat16%s r%u, #0x%04x, r%u uadd16%s r%u, r%u, r%u sadd16%s r%u, r%u, r%u usub16%s r%u, r%u, r%u ssub16%s r%u, r%u, r%u uadd8%s r%u, r%u, r%u sadd8%s r%u, r%u, r%u usub8%s r%u, r%u, r%u ssub8%s r%u, r%u, r%u qadd8%s r%u, r%u, r%u qsub8%s r%u, r%u, r%u uqadd8%s r%u, r%u, r%u uqsub8%s r%u, r%u, r%u uhadd8%s r%u, r%u, r%u uhadd16%s r%u, r%u, r%u shadd8%s r%u, r%u, r%u qadd16%s r%u, r%u, r%u qsub16%s r%u, r%u, r%u qsax%s r%u, r%u, r%u qasx%s r%u, r%u, r%u sasx%s r%u, r%u, r%u smu%cd%s%s r%u, r%u, r%u smlaw%c%s r%u, r%u, r%u, r%u sel%s r%u, r%u, r%u usad8%s r%u, r%u, r%u usada8%s r%u, r%u, r%u, r%u qadd%s r%u, r%u, r%u qdadd%s r%u, r%u, r%u qsub%s r%u, r%u, r%u qdsub%s r%u, r%u, r%u uqsub16%s r%u, r%u, r%u shadd16%s r%u, r%u, r%u uhsub8%s r%u, r%u, r%u uhsub16%s r%u, r%u, r%u uqadd16%s r%u, r%u, r%u uqsax%s r%u, r%u, r%u uqasx%s r%u, r%u, r%u usax%s r%u, r%u, r%u uasx%s r%u, r%u, r%u ssax%s r%u, r%u, r%u shsub8%s r%u, r%u, r%u shasx%s r%u, r%u, r%u uhasx%s r%u, r%u, r%u shsax%s r%u, r%u, r%u uhsax%s r%u, r%u, r%u shsub16%s r%u, r%u, r%u smmls%s%s r%u, r%u, r%u, r%u cmncmpmulorreorandlsllsrasrror16nzlr,addssubsldrstrwfe yield ststteqrsbornbicmvnmovldrbstrbldrdstrd, LSL #1ubfxsbfxuxtbuxthsxtbsxthuxtb16sxtb16mlamlsgfwadcsbc???ldrshldrhldrsbstrh (thumb) 0x%x: r3 = client_request ( %%r4 ) r3 = guest_NRADDR IR injection %s r%u, r%u tst r%u, r%u negs r%u, r%u mvns r%u, r%u bics r%u, r%u adcs r%u, r%u sbcs r%u, r%u uxtb r%u, r%u sxtb r%u, r%u uxth r%u, r%u sxth r%u, r%u %ss r%u, r%u rev%s r%u, r%u revsh r%u, r%u add sp, #%u sub sp, #%u svc #0x%08x add(hi) r%u, r%u cmphi r%u, r%u mov r%u, r%u it%c%c%c %s cb%s r%u, 0x%x nRegs >= 1 && nRegs <= 9push {%s0x%04x} nRegs >= 0 && nRegs <= 8pc,pop {%s0x%04x} %s r%u, r%u, #%u %s r%u, r%u, r%u %s r%u, [r%u, r%u] %sh r%u, [r%u, r%u] ldrsh r%u, [r%u, r%u] ldrsb r%u, [r%u, r%u] %sb r%u, [r%u, r%u] %s r%u, #%u add r%u, pc, #%u add r%u, r13, #%u cmp r%u, #%u movs r%u, #%u ldr r%u, [pc, #%u] %s r%u, [r%u, #%u] %sh r%u, [r%u, #%u] %sb r%u, [r%u, #%u] %s r%u, [sp, #%u] ldmia r%u!, {0x%04x} stmia r%u!, {0x%04x} %ss r%u, r%u, #%u b 0x%x b%s 0x%x nop sev bl 0x%x (stay in Thumb mode) %sm%c%c r%u%s, {0x%04x} add%s.w r%u, r%u, #%u addw r%u, r%u, #%u %s.w r%u, #%u %s%s.w r%u, r%u, #%u subw r%u, r%u, #%u %s%s.w r%u, r%u, %s %s%s.w r%u, r%u, r%u %s%s.w r%u, %s %s.w r%u, %s %s%s.w r%u, #%u movw r%u, #%u movt r%u, #%u rN != rTloadsPC!loadsPCrN != 15%s.w r%u, [r%u, #%c%u] %s.w r%u, [r%u, #%c%u]! bP == 0 && bW == 1%s.w r%u, [r%u], #%c%u %s.w r%u, [r%u, +#%u] %s.w r%u, r%u, [r%u, #%c%u] %s.w r%u, r%u, [r%u, #%c%u]! %s.w r%u, r%u, [r%u], #%c%u b%s.w 0x%x b.w 0x%x tb%c [r%u, r%u%s] mask != 0%s r%u, r%u, #%u, #%u %s r%u, r%u, ror #%u mul.w r%u, r%u, r%u sdiv.w r%u, r%u, r%u udiv.w r%u, r%u, r%u %cmull r%u, r%u, r%u, r%u %s r%u, r%u, r%u, r%u %cmlal r%u, r%u, r%u, r%u umaal r%u, r%u, r%u, r%u smmul%s r%u, r%u, r%u smmla%s r%u, r%u, r%u, r%u sub r%u, pc, #%u bfc r%u, #%u, #%u bfi r%u, r%u, #%u, #%u clz r%u, r%u rbit r%u, r%u msr cpsr_%s%s, r%u mrs r%u, cpsr ldrex r%u, [r%u, #+%u] ldrex%c r%u, [r%u] ldrexd r%u, r%u, [r%u] strex r%u, r%u, [r%u, #+%u] strex%c r%u, r%u, [r%u] strexd r%u, r%u, r%u, [r%u] DSB DMB ISB pld%s [r%u, #%u] pld%s [r%u, #-%u] pld%s [r%u, r%u, lsl %u] mrc p15,0, r%u, c13, c0, 3 mcr p15,0, r%u, c13, c0, 2 mrc p15,0, r%u, c13, c0, 2 mrc p15,0, r%u, c9, c14, 0 clrex ldrt r%u, [r%u, #%u] strt r%u, [r%u, #%u] strbt r%u, [r%u, #%u] ldrht r%u, [r%u, #%u] ldrsht r%u, [r%u, #%u] strht r%u, [r%u, #%u] ldrbt r%u, [r%u, #%u] ldrsbt r%u, [r%u, #%u] pli [r%u, #%u] pli [r%u, #-%u] pli [pc, #%c%u] rscl(assumed not taken)(assumed taken)guest_arch == VexArchARM (arm) 0x%x: pld%c [r%u, #%c%u] eaEpld%c %s pli [r%u, #%c%u] op == Iop_Sub32op == Iop_And32shco == IRTemp_INVALIDshco != IRTemp_INVALID%s%s%s r%u, r%u, %s %s%s%s r%u, %s %s%s r%u, %s taT != IRTemp_INVALIDrD != rN%sr%s%s r%u, %s %sm%c%c%s r%u%s, {0x%04x} b%s%s 0x%x %s b%sx r%u b%sx%s r%u clz%s r%u, r%u mul%c%s r%u, r%u, r%u sdiv r%u, r%u, r%u udiv r%u, r%u, r%u ml%c%c%s r%u, r%u, r%u, r%u umaal %s r%u, r%u, r%u, r%u msr%s cpsr%s%sf, #0x%08x msr%s cpsr_%s%s, r%u mrs%s r%u, cpsr svc%s #0x%08x swp%s%s r%u, r%u, [r%u] movt%s r%u, #0x%04x movw%s r%u, #0x%04x %s%s r%u, r%u, ROR #%d bfc%s r%u, #%u, #%u bfi%s r%u, r%u, #%u, #%u %s%s r%u, r%u, #%u, #%u rD+0 != rNrD+1 != rNrev%s%s r%u, r%u revsh%s r%u, r%u smmul%s%s r%u, r%u, r%u smmla%s%s r%u, r%u, r%u, r%u ldrt%s r%u, [r%u], #%c%u ldrt%s r%u, %s ldrbt%s r%u, [r%u], #%c%u ldrbt%s r%u, %s ldrht%s r%u, [r%u], #%c%u ldrht%s r%u, [r%u], %cr%u ldrsht%s r%u, [r%u], #%c%u ldrsht%s r%u, [r%u], %cr%u ldrsbt%s r%u, [r%u], #%c%u ldrsbt%s r%u, [r%u], %cr%u strbt%s r%u, [r%u], #%c%u strbt%s r%u, %s strht%s r%u, [r%u], #%c%u strht%s r%u, [r%u], %cr%u strt%s r%u, [r%u], %c%u strt%s r%u, %s mrc%s p15,0, r%u, c13, c0, 3 mcr%s p15,0, r%u, c13, c0, 2 mrc%s p15,0, r%u, c13, c0, 2 mrc%s p15,0, r%u, c9, c14, 0 nop%s yield%s dres.whatNext == Dis_Continueirsb->next == NULLirsb->jumpkind == Ijk_Boringnpmwymk_EA_reg_plusminus_shifted_regmk_shifter_operanddecode_NV_instruction_ARMv7_and_belowdisInstr_ARM_WRKllPutIRegput_ITSTATEllPutFReg_up_to_64llGetFReg_up_to_64breakupV128to32sdecode_V8_instructiondecode_V6MEDIA_instructionmath_INTERLEAVE_4math_PERM_8x8x3dis_neon_load_or_storedis_neon_data_2reg_miscdis_neon_data_2reg_and_shiftppNeonImmTypebinop_w_fake_RMdecode_NEON_instruction_ARMv7_and_belowllPutFRegfloatGuestRegOffsetllGetFRegllPutDRegI64llPutDRegllGetDRegdoubleGuestRegOffsetllGetDRegI64mk_skip_over_A32_if_cond_is_falsellPutQRegquadGuestRegOffsetllGetQRegdecode_CP10_CP11_instructionputIRegTloadGuardedLEllGetIRegnewTempgetIRegTisBadRegTmk_skip_over_T32_if_cond_is_falseputMiscReg32put_GEFLAG32desynthesise_APSRmkU8genROR32gen_SIGILL_T_if_in_but_NLI_ITBlockgen_SIGILL_T_if_nonzerosetFlags_D1_D2_NDcompute_result_and_C_after_shift_by_imm5putIRegAintegerGuestRegOffsetgetIRegAmk_ldm_stmmk_skip_over_T16_if_cond_is_falsecompute_result_and_C_after_ASR_by_imm5compute_result_and_C_after_LSR_by_imm5compute_result_and_C_after_LSL_by_imm5mk_armg_calculate_condition_dynget_ITSTATEdisInstr_THUMB_WRKdisInstr_ARMtypeOfIRExpr(irsb->tyenv, cond) == Ity_I320 == (guest_R15_curr_instr_notENC & 1)typeOfIRExpr(irsb->tyenv, e) == Ity_I320 == (guest_R15_curr_instr_notENC & 3)typeOfIRExpr(irsb->tyenv, e) == Ity_V128typeOfIRExpr(irsb->tyenv, e) == Ity_F64typeOfIRExpr(irsb->tyenv, e) == Ity_I64typeOfIRExpr(irsb->tyenv, e) == Ity_F32lowbits_to_ignore == 0 || lowbits_to_ignore == 8 || lowbits_to_ignore == 16 || lowbits_to_ignore == 31shift_amt >= 1 && shift_amt <= 31typeOfIRTemp(irsb->tyenv, t_dep1 == Ity_I32)typeOfIRTemp(irsb->tyenv, t_dep2 == Ity_I32)typeOfIRTemp(irsb->tyenv, t_ndep == Ity_I32)cc_op >= ARMG_CC_OP_COPY && cc_op < ARMG_CC_OP_NUMBERshop && *shop == IRTemp_INVALIDmk_shifter_operand(0x%x,0x%x) VABA should not be in dis_neon_data_3diff VABL should not be in dis_neon_data_3diff (regs == 1 && (inc == 1 || inc == 2)) || (regs == 2 && inc == 2)regs == 1 && (inc == 1 || inc == 2)vcvt.%c32.f32 %c%u, %c%u, #%u vcvt.f32.%c32 %c%u, %c%u, #%u szBlg2 <= 2 && nn <= 14 && tt <= 14strex%s%s r%u, r%u, r%u, [r%u] vml%c.%c%d %c%u, %c%u, d%u[%u] vml%cl.%c%d q%u, d%u, d%u[%u] vqdml%cl.s%d q%u, d%u, d%u[%u] vmul.%c%d %c%u, %c%u, d%u[%u] vqdmull.s%d q%u, d%u, d%u[%u] vqdmulh.s%d %c%u, %c%u, d%u[%u] vqrdmulh.s%d %c%u, %c%u, d%u[%u] VABDL should not be in dis_neon_data_3same VABAL should not be in dis_neon_data_3samevqrdmulh.s%d %c%u, %c%u, %c%u conq >= ARMCondEQ && conq <= ARMCondALINSNA(31,28) == BITS4(0,0,0,0)sml%cd%s%s r%u, r%u, r%u, r%u smla%c%c%s r%u, r%u, r%u, r%u smlal%c%c%s r%u, r%u, r%u, r%u uxtab16%s r%u, r%u, r%u, ROR #%u sxtab16%s r%u, r%u, r%u, ROR #%u smlald%c%s r%u, r%u, r%u, r%u smlsld%c%s r%u, r%u, r%u, r%u branch-and-link-to-noredir r4 disInstr(thumb): unhandled instruction: 0x%04x 0x%04x n_guarded >= 1 && n_guarded <= 4bx r%u (possibly switch to ARM mode) blx r%u (possibly switch to ARM mode) blx 0x%x (switch to ARM mode) op == Iop_And32 || op == Iop_Or32%s.w r%u, [r%u, r%u, LSL #%u] %cxtah r%u, r%u, r%u, ror #%u %cxtab r%u, r%u, r%u, ror #%u blx 0x%x (and switch to Thumb mode) %sr%s%s r%u, %s! (at-EA-then-Rn=EA) %sr%s%s r%u, %s! (at-Rn-then-Rn=EA) %s%s r%u, %s! (at-EA-then-Rn=EA) %s%s r%u, %s! (at-Rn-then-Rn=EA) %cmull%c%s r%u, r%u, r%u, r%u %cmlal%c%s r%u, r%u, r%u, r%u %cxtab%s r%u, r%u, r%u, ror #%u %cxtah%s r%u, r%u, r%u, ror #%u mcr 15, 0, r%u, c7, c10, 5 (data memory barrier) mcr 15, 0, r0, c7, c10, 4 (data synch barrier) mcr 15, 0, r0, c7, c5, 4 (insn synch barrier) disInstr(arm): unhandled instruction: 0x%x cond=%d(0x%x) 27:20=%d(0x%02x) 4:4=%d 3:0=%d(0x%x) 1HAHD$X1HAHD$X1GNUzRx r(0BLA uBB(\BLA uBBDP8BEB D(D0 (A BBBD $ABAG dIE(BAD s AEH ,DIBA r EBK <tBBB E(D0 (E BBBO (BAD s AEH (BAD p AEK  %AA^(;\<%AA^X%AA^t%AA^<EHB D(C0I (H DBBI CdCdCd D` L X H 4,BDI r IEI b IEH 8dBBD C(F0k (D ABBK D` L X H ?DQ K (AAD | ADI (EAD z ADG (4AAD z ADK (`AAD U ADH (AAD z ADK  DT?AU J WDf N 4BED j BBG BB@dHp H \dDp L (xEAD U ADL 8BBE D(D0N (D BBBG CdHBBB E(D0I8FP 8I0D(B BBBG H@BBE E(A0C8D@} 8D0A(B BBBE <FBB E(A0a (B BBBG <BBB E(A0` (B BBBL < BBB E(A0a (B BBBK 8LBJE A(D0 (I EBBK <BBJ E(A0 (E EGBM 8BJE D(D0 (I EBBI LBBA A(D0o (I DBBF D (A ABBF 8TOBBB A(D0 (A EBBH <IBB B(A0j (B BBBN dHp H </BBB B(A0 (E BBBA <, BGB B(A0i (E BBBF pl _GFB A(A0 (D EGBK F (D EGBH F (D EGBH F (D EGBH < BBJ B(D0+ (G EGBL < BBB B(A0 (E BBBF <` FBB E(A0 (B BBBK ` BBB B(A0A8D@ 8A0A(B BBBE L 8A0A(B BBBJ H oBBB B(D0H8DP 8F0D(G BBBF `P BBB E(A0A8D`0 8A0D(B BBBJ l8A0A(B BBB` BBB J(A0A8Dp? 8A0D(B BBBN d8A0A(B BBBH OBBB B(I0A8D` 8D0A(B BBBG Hd /BGB B(A0A8D@ 8D0A(B BBBD H BBB B(D0C8L`z 8I0D(B BBBF < zBBE D(C0 (D BBBE << zBBE D(C0 (D BBBE H| OBBB J(A0A8D`  8C0A(B BBBC H BBE B(D0H8GP; 8A0D(B BBBJ x%BEE E(A0D8GP 8I0H(B BBBE  8A0A(B BBBD d8J0H(D BBBxEBEE E(A0C8GP 8I0H(B BBBJ  8A0A(B BBBF d8J0H(D BBB` _BEB E(A0C8Gp 8A0A(B BBBE Z 8A0A(B BBBL xp_BEE E(A0C8GP 8A0A(B BBBI  8J0H(D BBBL D 8I0H(B BBBK HBEE E(D0C8DP+ 8A0D(B BBBL <8BEE A(H0R (I BBBJ 8xBEA H(F0M (G KBBG PDEB A(A0 (D EDGG f (A BBBC `/BBE E(D0A8Gp 8A0A(B BBBF Z 8A0A(B BBBL `l/BBE E(D0A8Gp 8A0A(B BBBF Z 8A0A(B BBBL `?BBE E(D0A8Gp 8A0A(B BBBJ M 8D0H(D BBBM 4EHHUBEE E(D0C8G`q 8A0D(B BBBK H5BEE E(D0C8G`m 8A0D(B BBBG d.BBB B(A0F8Td 8A0A(B BBBG Q 8F0A(B BBBH LH, BBB B(A0A8D: 8A0D(B BBBK LBBB B(D0D8D 8A0D(B BBBG |fBBB B(A0C8I 8A0A(B BBBH  8M0A(B BBBE k 8C0A(B BBBE h#BBB B(A0A8DPE 8A0A(B BBBK D 8G0A(B BBBL D 8A0A(B BBBJ  8A0A(B BBBG  8H0H(B BBBJ D 8I0H(D BBBE H0BBE E(D0D8F` 8D0H(E BBBK ||BBB B(A0A8DPXXU`RXFP^ 8A0A(B BBBE  8F0A(B BBBB XH`TXFPDGK K(J0I8cNGBAPjDLF_ 8A0A(B BBBH r 8F0A(B BBBG $zRx ,)BBB B(A0C8Ig 8A0A(B BBBJ AHH`AAAHH`uAoB$h3+BJM K(K0J8Sp 8A0A(B BBBH xAWxApxMOxBp!x\UxFpOx\VxGp 8F0A(B BBBD HxAXxBpWxMOxApKxDKxApxIWxGp<xLZxFpx\VxGpCxIWxGpxMPxBpwx\VxGpBBHE B(A0A8I 8A0A(B BBBD JMGDDDFQ JJGX5 GQBMOALJEK HF OAEKCWAoRRBJNPB\%RDG E(A0A8DM 8A0A(B BBBA IWFwMGEI REDI5CNGXVFYTG,IWA|vBFH H(D0E8K- 8A0A(B BBBE IWAyJSB#DEEIGEEIDEEIJHBIDEEIkIXB"DEEIIKQANVHIDEEIDEEIQDEEI[QBJHBIDEEIIXBJ`BJSBKDEPIYBNGEEIJHBIKQAIWAJSAtIXAKJSBAKQAuNNBMDEEIJRAIWANNBoJSAKQAKDEPGDEPJSBCJRAqKQAJRAJSBKQAJSBt<HBIL K(E0A8DS 8A0A(B BBBG _ 8G0A(B BBBI  8D0A(B BBBG $ 8G0A(B BBBL D 8G0A(B BBBE OXBNLA JTF 8G0A(B BBBE DVADWBDVBDVADVADWANLBdcBHE B(A0A8D 8C0A(B BBBG  8F0A(B BBBH  LIB4LHAhX iBEB B(A0C8I D`B 8D0A(B BBBJ $DZAKELBEKB`JKAuD`A|KSADfB=JLB0D^AQKHAQLBP `QB +]IAvQPATQB! BBB B(A0A8J 8A0A(B BBBH 9LGBLFBvLFAULFABDOAJUAmBMA3K\AGaBZG[AKNXAxB]AHUAAdAD^B_AdA% AO ARA/DLBDbABSI$zRx ,2#FEB B(A0A8G; 8A0A(B BBBC L`B{NrJ DgA DW o ES KOASKPQ RU  KP = KH  RT  KL  HU r)BSZ_` A`"7D ]" "%   ; ,` %F _ %{  %@    C  C 8p CB [ d8 }p @ ?B x 4Ah Zm z0 `  ?PW ( AdKX ddwP p( 0C0 8 %0p@p\pxp H 0!O`#"p P#d#/ $"&_/ H(e)m`+u0,~ -o@03p7O :/>.Cz@`EzTFO_0L|p @O%'pQE' S_;  X_b  '{ Z  ^ ^ @_ 0 b/! @f/G pj?m nE oU   0      `u5 `  P  @  {. Ё, )  B V Гfa H z @# ) p     ! 5  N )e p ~ 3+   B p    `    T  H ( T 4 H @ T L H X `Z\%v v H   `>  ( @?c2PKir `|   2 ) B &[`esk6p;u@zEJOTY^chmr,1x0XS  Q# )/K5;ANG M'S0Y;_BeWkcqow|}(P#7Rh /<%S+`1r7n=CI@OpU[agmsy+'3H\dox % '+.C5M<ICSJQX+_fQmt{nfI~FLNH #*s18@?'F4MTY[bipIw~          1 H a z      ; Q g &~ - 4 ; B I PW^ elsczk  3    $ ) . 2  }    O " ) 0] 7@ >J ET Lf Sq Za hok v}@`   7   %Q,3:SA~H OV ]6di kry#Jk/cp> R  *   rA Y 0` !(/:6=RDK$RY|`ggnu||fL2Lb $3+x29/@GNU?\c#jqx%Ag\tr[E - ]'.v5_<GC0JQX_fmt{] !o~7HKOj #`*{18&?/FMT8[bJi3pw~!px{97O g&- 4;!BiI!PQW^el8sz~ &X  ! 1  D z c `! J ")0G!70!>E L SYZ!a!he"ovu#}""!!" #""!"!H#*#9##!e#%#! !@$#!%#,~!3W#:#A@H!O#V#]v"d$k$r!y!$$t$!P$b$!"h#"#!%!#$ &$ +0+v+!+(+/G+6+=*D+K*R*Y*`*g^+n+u+|A"s*e(){(5"(.":(""""'""(9"P(("#( h)v)="$?"+)2(9(@"G&N!U'\V'c'j'q!x'N*&)))"*) *)`*'+)D*?*I*(@ "P) O" i' =) ( ='' %'. '5 '< 'C  'J Q 'X U"_ `"f Z"m !t !{ K" W% l% C% /% $ %  % % % % % # $ % ! $ ! `&!!!!!!!!!!#!Q&*!v&1!=&8!C"?!G"F!&&M!&T![!!b!!i!&p!&w!&~!&!%!<$!%!!,!T,!W.!1,!,!%-!@,!b,!-!,!,!,!+! "a1 "-"."".&">.-" 4"/;"/B"-I"/P"N0W"i0^"z0e"0l"P s" z"0"."."h "."e-"( "4/"-"l."1"R/"+"1"u-""-"0" "0#+ #31#@-# /"# )#00#/7#/>#20E#/.L#`S#0Z# a#1h#|/o#v#X,}#Q1#/#H #-#,# -#,#t,#l/#,#X1#,#O-#.#Y-#.#.#.   #$$*$,8$E$S$`$m$}$$$$$$$$$$$%% %*%1%>%L%Y%p%}%%%%%%%%%&,&E&_&z&&&&&&&& '!'9'P'k'y''''p['thumbExpandImmmk_armg_calculate_flag_vmk_armg_calculate_flag_cname_ARMCondcodeassignirsbmk_armg_calculate_condition_dyn__PRETTY_FUNCTION__.4350mkU128mk_skip_over_T16_if_cond_is_false__curr_is_Thumbguest_R15_curr_instr_notENC__PRETTY_FUNCTION__.4424gen_SIGILL_T_if_nonzero__PRETTY_FUNCTION__.4432putMiscReg32__PRETTY_FUNCTION__.4258mk_skip_over_T32_if_cond_is_false__PRETTY_FUNCTION__.4428mk_skip_over_A32_if_cond_is_false__PRETTY_FUNCTION__.4420integerGuestRegOffset.part.0__PRETTY_FUNCTION__.4067isBadRegT__PRETTY_FUNCTION__.4103quadGuestRegOffset.part.0__PRETTY_FUNCTION__.4195doubleGuestRegOffset.part.0__PRETTY_FUNCTION__.4140floatGuestRegOffset.part.0__PRETTY_FUNCTION__.4217DIPimm.part.0__PRETTY_FUNCTION__.6102llGetIReg__PRETTY_FUNCTION__.4071llGetDRegI64__PRETTY_FUNCTION__.4161llGetDReg__PRETTY_FUNCTION__.4144getIRegA__PRETTY_FUNCTION__.4076mk_EA_reg_plusminus_imm8mk_EA_reg_plusminus_reggetIRegT__PRETTY_FUNCTION__.4081mkU8__PRETTY_FUNCTION__.3973llPutQReg__PRETTY_FUNCTION__.4207llPutDReg__PRETTY_FUNCTION__.4152llPutDRegI64__PRETTY_FUNCTION__.4169llPutFReg_up_to_64host_endness__PRETTY_FUNCTION__.4238llPutIReg__PRETTY_FUNCTION__.4086mk_armg_calculate_conditionnewTemp__PRETTY_FUNCTION__.4031put_ITSTATE__PRETTY_FUNCTION__.4267binop_w_fake_RM__PRETTY_FUNCTION__.4796llGetFReg__PRETTY_FUNCTION__.4221llGetFReg_up_to_64__PRETTY_FUNCTION__.4225llPutFReg__PRETTY_FUNCTION__.4233storeGuardedLEgetDRegsetFlag_QCloadGuardedLE__PRETTY_FUNCTION__.4027putDRegputQReg__PRETTY_FUNCTION__.4199putDRegI64or_into_QFLAG32signed_overflow_after_Sub32signed_overflow_after_Add32genROR32__PRETTY_FUNCTION__.4039gen_SIGILL_T_if_in_but_NLI_ITBlock__PRETTY_FUNCTION__.4437putIRegT__PRETTY_FUNCTION__.4099getFReggen_REV16mk_get_IR_rounding_modeput_GEFLAG32__PRETTY_FUNCTION__.4288set_GE_32_10_from_bits_31_15gen_REVputFRegputIRegAr15writtenr15guardr15kind__PRETTY_FUNCTION__.4093set_GE_3_2_1_0_from_bits_31_23_15_7armUnsignedSatQarmSignedSatQmk_convert_IRCmpF64Result_to_NZCVmath_PERM_8x8x3.part.0math_INTERLEAVE_2math_DEINTERLEAVE_2gen_BITREVbreakupV128to32s.constprop.0__PRETTY_FUNCTION__.7010compute_result_and_C_after_LSR_by_imm5__PRETTY_FUNCTION__.4535compute_result_and_C_after_ASR_by_imm5__PRETTY_FUNCTION__.4555compute_result_and_C_after_ROR_by_regcompute_result_and_C_after_LSL_by_imm5__PRETTY_FUNCTION__.4515setFlags_D1_D2_ND__PRETTY_FUNCTION__.4395setFlags_D1_D2setFlags_D1_ND.constprop.0desynthesise_APSR__PRETTY_FUNCTION__.4459compute_result_and_C_after_LSR_by_regcompute_result_and_C_after_LSL_by_regcompute_result_and_C_after_ASR_by_regcompute_result_and_C_after_shift_by_regmath_INTERLEAVE_3in0.6270__PRETTY_FUNCTION__.6236in1.6271in2.6272math_DEINTERLEAVE_3de0.6257de1.6258de2.6259dis_neon_vtbmath_INTERLEAVE_4__PRETTY_FUNCTION__.6308math_DEINTERLEAVE_4mk_ldm_stm__PRETTY_FUNCTION__.7430compute_result_and_C_after_shift_by_imm5__PRETTY_FUNCTION__.4588mk_EA_reg_plusminus_shifted_reg__PRETTY_FUNCTION__.4650mk_shifter_operand__PRETTY_FUNCTION__.4622dis_neon_data_3diffdis_neon_data_3diff.colddis_neon_load_or_store__PRETTY_FUNCTION__.6338dis_neon_data_2reg_and_shift__PRETTY_FUNCTION__.5618decode_V8_instruction.constprop.0CSWTCH.2463__PRETTY_FUNCTION__.7019CSWTCH.2464cvt.7178CSWTCH.2465CSWTCH.2466CSWTCH.2469CSWTCH.2470CSWTCH.2467CSWTCH.2468dis_neon_data_2reg_and_scalardis_neon_data_3samedis_neon_data_processing__PRETTY_FUNCTION__.5764decode_NEON_instruction_ARMv7_and_below.constprop.0__PRETTY_FUNCTION__.6442decode_CP10_CP11_instruction.constprop.0__PRETTY_FUNCTION__.7463decode_V6MEDIA_instruction.constprop.0__PRETTY_FUNCTION__.6453disInstr_THUMB_WRK.constprop.0it_length_table__PRETTY_FUNCTION__.8432__PRETTY_FUNCTION__.4262disInstr_THUMB_WRK.constprop.0.cold__PRETTY_FUNCTION__.7823__PRETTY_FUNCTION__.9477__PRETTY_FUNCTION__.7767.LC0.LC1.LC17.LC4.LC5.LC6.LC7.LC8.LC9.LC10.LC11.LC12.LC13.LC14.LC15.LC16.LC2.LC3.LC20.LC18.LC19.LC21.LC22.LC23.LC24.LC25.LC26.LC27.LC28.LC45.LC35.LC36.LC44.LC29.LC30.LC34.LC33.LC42.LC31.LC32.LC43.LC37.LC38.LC39.LC40.LC41.LC46.LC47.LC48.LC49.LC50.LC51.LC52.LC53.LC54.LC55.LC56.LC57.LC58.LC59.LC60.LC61.LC62.LC63.LC64.LC65.LC66.LC67.LC68.LC69.LC72.LC70.LC71.LC73.LC74.LC75.LC76.LC77.LC78.LC79.LC81.LC80.LC82.LC83.LC84.LC85.LC86.LC87.LC88.LC89.LC90.LC91.LC92.LC93.LC94.LC95.LC97.LC96.LC98.LC99.LC100.LC101.LC102.LC104.LC103.LC105.LC108.LC106.LC107.LC109.LC111.LC113.LC112.LC114.LC115.LC110.LC119.LC116.LC117.LC118.LC121.LC120.LC123.LC130.LC132.LC133.LC126.LC122.LC127.LC129.LC131.LC124.LC128.LC125.LC139.LC136.LC140.LC142.LC135.LC137.LC145.LC138.LC141.LC147.LC143.LC144.LC146.LC149.LC148.LC168.LC159.LC153.LC150.LC164.LC167.LC157.LC162.LC155.LC154.LC165.LC151.LC156.LC158.LC152.LC161.LC166.LC163.LC160.LC174.LC230.LC195.LC196.LC197.LC198.LC199.LC200.LC201.LC202.LC203.LC204.LC205.LC206.LC207.LC208.LC209.LC212.LC213.LC214.LC185.LC186.LC187.LC188.LC189.LC190.LC191.LC192.LC193.LC181.LC183.LC210.LC171.LC172.LC169.LC170.LC184.LC182.LC175.LC232.LC179.LC180.LC237.LC216.LC217.LC218.LC219.LC220.LC221.LC222.LC215.LC173.LC234.LC229.LC176.LC233.LC2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<$|$HH$0HH$8$D0|$|$ILDHH/DH-N|$H4$D觺IB|$艿|$Ix|$HgATLHAVHMIH=1Y^<$|$L|$I@4$|$LHAA=DHCDH-b|$H|$HHD4$D諹IF|$荾|$I||$HkATIMAVHH=LH1_AXHH$0HH$8$D0|$|$ILDHH:DH-Y|$H\$ͻDILHHH$0HH$8$0H迵DH-޿Ht|$HHDy1HLL濢HHHHH$0HH$8$0HHDH-7|$H˻nAu <$c@|$H H$0HH$8$D0|$M|$IALDHHiDH-舾|$H4$DI||$û|$I費|$H衻ATMIAVHLHH=1AYAZ"|$H-HHDH  H$0H  H$8$D0|$7|$I+LDHHSDH-r|$H|$HH$0HH$8$D0m|$袸|$I薸LDHH農DH-ݼ|$HqPHdeH$0HfgH$8$D0M|$HhiH$0HjkH$8$D0HH$0HH$8$D0p|$襷|$I虷LDHHDH-|$HtSHlmH$0HnoH$8$D0PfHشH &H5H=HxyH$0Hz{H$8$D0聺|$趶|$I誶LDHHҰDH-|$H腷8H H5H=AAT$ADt$DDDAԹ|$DA西HH=H|$!|$1HHDH=HDIL⿮+|$HDHH=HDUAHILHDHH=HD舿|$L%|$D轶@LH5HHH=HD19H$H$0HH$8D0һ|$tsH$H$0HH$8D0HH$0HH$8D0闻<$DIH$H$0HH$8D01H<$DUH|$H-HHD逼J $A1DH=ޥJ $A1DH=麥|$0|$HH=H|$(dbm_RepTo64priv/guest_arm64_toIR.cM == 32 || M == 64x == 0len <= 6M >= (1 << len)esize >= (S+1)esize >= (d+1)elem_s < (1ULL << esize)elem_d < (1ULL << esize)rot >= 0 && rot < widthnveqcsccmiplvsvchilsgeltgtlealne0bitQ <= 1 && size <= 38b4h2s1d16b8h4s2dsize < 4sizeNarrow < 4n >= 2 && n <= 64size < 3widenUto64(arm64)isPlausibleIRType(ty)i < 256arm64g_calculate_conditionsphost_endness == VexEndnessLElaneSzB > 0maxOff < 16wspt1 && *t1 == IRTemp_INVALIDt2 && *t2 == IRTemp_INVALIDt3 && *t3 == IRTemp_INVALIDt4 && *t4 == IRTemp_INVALIDsize <= 3ix <= 15is64 == True || is64 == Falseres && *res == IRTemp_INVALIDsize <= 2vecD == IRTemp_INVALIDbitQ == 1ty == Ity_I32imm < wmkSHRt6 && *t6 == IRTemp_INVALIDt7 && *t7 == IRTemp_INVALIDsh_amt < (is64 ? 64 : 32)imm <= 0xFFFFULLimm <= 0xFFFFFFFFULLsize == X01 || size == X10shift < laneBitsuqshlsqshlsqshlufmaddfmsubfnmaddfnmsub%s %s, %s, %s, %s bicorr%s %s.1d, %016llx %s %s.2d, #0x%016llx'%016llx mov %s, #0x%016llx'%016llx imm4 >= 1 && imm4 <= 7[%s, %s][%s, %s lsl %u][%s, %s uxtx][%s, %s uxtx, lsl %u][%s, %s sxtx][%s, %s sxtx, lsl %u]rhsarm64g_dirtyhelper_AESEarm64g_dirtyhelper_AESDarm64g_dirtyhelper_AESMCarm64g_dirtyhelper_AESIMCimcmcaes%c %s.16b, %s.16b aes%s %s.16b, %s.16b efccmp%s %s, %s, #%u, %s uaddlpuadalpsadalpsaddlpusqaddsuqaddclzclsnotcntsqnegsqabsfcmgtfcmgefnegfabs2sqxtnuqxtnsqxtunurecpeursqrtefrsqrtefrecpefcmeqfcmlefcmltrev64%s %s.%s, %s.%s rev32rev16rbitcm%s %s.%s, %s.%s, #0 abs %s.%s, %s.%s neg %s.%s, %s.%s %s %s.%s, %s.%s, #0.0 xtn%s%s %s.%s, %s.%s shll%s %s.%s, %s.%s, #%d fcvtn%s %s.%s, %s.%s fcvtxn%s %s.%s, %s.%s fcvtl%s %s.%s, %s.%s frint%c %s.%s, %s.%s fcvt%c%c %s.%s, %s.%s ok%ccvtf %s.%s, %s.%s fsqrtushrusrassrasshrurshrursrasrsrasrshrsqshrnuqshrnsqrshrnuqrshrnsqshrunsqrshrunucvtfscvtffcvtzufcvtzssh >= 1 && sh <= 64!isU%s d%u, d%u, #%u sri d%u, d%u, #%u sh >= 0 && sh < 64shl d%u, d%u, #%u sli d%u, d%u, #%u size >= 0 && size <= 3%s %c%u, %c%u, #%u size >= X00 && size <= X10size == X10 || size == X11bhsdfmov%s %s, %s fcvt %s, %s frint%c %s, %s zip1zip2uzp1uzp2trn1trn2%s %s.%s, %s.%s, %s.%s fcvtz%c %s, %s, #%d %ccvtf %s, %s, #%d fminnmfmulfsubfaddfdivfmaxfminfmaxnm%s %s, %s, %s fnmul%s %s, [%s, #%lld] (at-Rn) stldldrs%c %s, [%s], #%llu ldrs%c %s, [%s, #%llu]!ldrstr%s %s, [%s], #%lld %s %s, [%s, #%lld]! ldurstur(fallback implementation)aldrbldrhstrbstrh%s %s, [%s, #%u] ldurbldurhsturbsturhbL == 0 && bX == 0ldr %s, 0x%llx (literal) ldr %s, %s str %s, %s ldruh %s, %s strh %s, %s ldrub %s, %s strb %s, %s bitX == 0ldrsw %s, [%s, #%u] ldrsh %s, [%s, #%u] ldrsb %s, [%s, #%u] ldurs%c %s, [%s, #%lld]ldrsw %s, %s ldrsh %s, %s ldrsb %s, %s %s %s, [%s, #%lld] , #%u, %srbrhrld%sx%s %s, [%s] %s narrowFrom64(arm64)st%sx%s %s, %s, [%s] %s lda%s %s, [%s] stl%s %s, [%s] prfm prfop=%u, [%s, #%u] prfm prfop=%u, %s ARM64 front end: load_store lndres->len == 4dres->continueAt == 0b.%s 0x%llx b%s 0x%llx ret %s blr %s jmp %s cb%sz %s, 0x%llx tb%sz %s, #%u, 0x%llx svc #0 msr tpidr_el0, %s mrs %s, tpidr_el0 msr fpcr, %s mrs %s, fpcr msr fpsr, %s mrs %s, fpsr msr %s, nzcv arm64g_calculate_flags_nzcvmrs %s, nzcv mrs %s, dczid_el0 (FAKED) mrs %s, ctr_el0 mrs %s, cntvct_el0 mrs %s, cntfrq_el0 ic ivau, %s dc cvau, %s dsbdmbisb#0oshldoshstosh#4nshldnshstnsh#8ishldishstish#12sy%s %s nop brk #%u yield hint #%u clrex #%u ARM64 front end: branch_etc uaddlvsaddlvsmaxvumaxvsminvuminvaddvnm%s %s.%c, %s.%s %s %s, %s.%s %s%sv s%u, %u.4s %s %c%u, %c%u cm%s d%u, d%u, #0 abs d%u, d%u neg d%u, d%u %s %s, %s, #0.0 fcvtxn s%u, d%u fcvt%c%c %c%u, %c%u %ccvtf %c%u, %c%u frecpxfmlsfmlafmulxsqmullsqdmlalsqdmlslsqrdmulhsqdmulh%s %c%u, %c%u, %s.%c[%u] %s %c%u, %c%u, v%u.%c[%u] %s %c%u, %c%u, v%d.%c[%u] masslishlrshrnshrn%s %s.%u%c, %s.%u%c, #%u sri%s %s.%s, %s.%s, #%u shift >= 1sh < 32sh < 16sh < 8immh == 0%cshll%s %s.%s, %s.%s, #%u nLanes == 2 || nLanes == 4usubluaddlsaddlssublusubwuaddwsaddwssubwrsubhnraddhnaddhnsubhnuabdluabalsabalsabdlmullmlalmlslsqdmull1q%s%s %s.%s, %s.%s, %s.%s %c%s%s %s.%s, %s.%s, %s.%s size == X11arm64g_dirtyhelper_PMULLQpmulluqsubuqaddsqaddsqsubcmgtcmhicmgecmhssrshlurshlushlsshluqrshlsqrshlsubaddcmeqcmtstfacgtfacgefrsqrtsfrecps%s %c%u, %c%u, %c%u fabd %s, %s, %s fmulx %s, %s, %s bhsddup %s.%s, %s.%c[%u] dup %s.%s, %s ins %s.%c[%u], %s %cmov %s, %s.%s[%u] ins %s.%c[%u], %s.%c[%u] fcvt%c%c %s, %s %ccvtf %s, %s fmov s%u, w%u fmov d%u, x%u fmov v%u.d[1], x%u fmov w%u, s%u fmov x%u, d%u fmov x%u, v%u.d[1] mlamlsmul%s %s.%s, %s.%s, %s.%c[%u] %s%s %s.%s, %s.%s, %s.%c[%u] lsrlslasrsbcadcrormaddmsub%s%s %s, %s, %s, %s #%u arm64g_calculate_flag_c%s%s %s, %s, %s mov %s, %s %s %s, %s, %s, %s #%u %cmulh %s, %s, %s cselcsinccsinvcsneguxtbuxthuxtwuxtxsxtbsxthsxtwsxtx%s%s %s, %s, %s %s lsl %u ccm%c %s, #%u, #%u, %s ccm%c %s, %s, #%u, %s revcl%c %s, %s lslvlsrvasrvrorv%cdiv %s, %s, %s %cm%sl %s, %s, %s, %s arm64g_calc_crc32barm64g_calc_crc32harm64g_calc_crc32warm64g_calc_crc32xarm64g_calc_crc32cbarm64g_calc_crc32charm64g_calc_crc32cwarm64g_calc_crc32cxcrc32bcrc32hcrc32wcrc32xcrc32cbcrc32chcrc32cwcrc32cxfaddp d%u, v%u.2d faddp s%u, v%u.2s addp d%u, %s.2d %s%sp %c%u, v%u.2%c psbfmubfmbfm%ss %s, %s, 0x%x %s %s, %s, 0x%x adr%s %s, 0x%llx andeorands%s %s, %s, 0x%llx imm64 < 0x100000000ULLmovz %s, 0x%llx movn %s, 0x%llx movk %s, 0x%x, lsl %u hw <= 1%s %s, %s, immR=%u, immS=%u imm6 > 0 && imm6 < szBitsextr %s, %s, %s, #%u tbxtbluhsubuhaddshaddshsuburhaddsrhaddumaxuminsmaxsminuabduabasabasabdpmuluminpumaxpsmaxpsminp#0.0guest_arch == VexArchARM64 (arm64) 0x%llx: x3 = client_request ( x4 ) x3 = guest_NRADDR IR injection dup %s, %s.%s[%u] ornbslbitbifaddp %s.%s, %s.%s, %s.%s fabd %s.%s, %s.%s, %s.%s %s%sp %s.%s, %s.%s, %s.%s faddpsha1csha1psha1msha1su0sha256hsha256h2sha256su1arm64g_dirtyhelper_SHA1Carm64g_dirtyhelper_SHA1Parm64g_dirtyhelper_SHA1Marm64g_dirtyhelper_SHA1SU0arm64g_dirtyhelper_SHA256Harm64g_dirtyhelper_SHA256H2arm64g_dirtyhelper_SHA256SU1%s q%u, s%u, v%u.4s %s v%u.4s, v%u.4s, v%u.4s %s q%u, q%u, v%u.4s sha1hsha1su1sha256su0arm64g_dirtyhelper_SHA1Harm64g_dirtyhelper_SHA1SU1arm64g_dirtyhelper_SHA256SU0%s s%u, s%u %s v%u.4s, v%u.4s fcmp%s %s, %s fcsel %s, %s, %s, %s exp < (1ULL << E)frac < (1ULL << F)1 + E + F == Nfmov %s, #0x%llx disInstr(arm64): %s eonbicsq0q1q2q3q4q5q6q7q8q9q10q11q12q13q14q15q16q17q18q19q20q21q22q23q24q25q26q27q28q29q30q31d0d1d2d3d4d5d6d7d8d9d10d11d12d13d14d15d16d17d18d19d20d21d22d23d24d25d26d27d28d29d30d31s0s1s2s3s4s5s6s7s8s9s10s11s12s13s14s15s16s17s18s19s20s21s22s23s24s25s26s27s28s29s30s31h0h1h2h3h4h5h6h7h8h9h10h11h12h13h14h15h16h17h18h19h20h21h22h23h24h25h26h27h28h29h30h31b0b1b2b3b4b5b6b7b8b9b10b11b12b13b14b15b16b17b18b19b20b21b22b23b24b25b26b27b28b29b30b31w0w1w2w3w4w5w6w7w8w9w10w11w12w13w14w15w16w17w18w19w20w21w22w23w24w25w26w27w28w29w30wzrx0x1x2x3x4x5x6x7x8x9x10x11x12x13x14x15x16x17x18x19x20x21x22x23x24x25x26x27x28x29x30xzrpmzmapz putPCputQRegHI64dis_AdvSIMD_fp_to_from_fixedp_convVFPExpandImmdis_AdvSIMD_fp_immediatedis_AdvSIMD_fp_data_proc_2_sourcedis_AdvSIMD_fp_data_proc_1_sourcedis_AdvSIMD_vector_x_indexed_elemdis_AdvSIMD_two_reg_miscmath_REARRANGE_FOR_FLOATING_PAIRWISEmkVecMULmath_MULL_ACCdis_AdvSIMD_three_differentmkVecSHLNdis_AdvSIMD_shift_by_immediatedis_AdvSIMD_scalar_x_indexed_elementmkVecCMPGTSnewTempsV128_7dis_AdvSIMD_scalar_two_reg_miscmath_VEC_DUP_IMMmath_SQDMULHmkVecSUBnewTempsV128_2math_SQDMULL_ACCdis_AdvSIMD_scalar_three_differenttwo_to_the_plustwo_to_the_minusupdateQCFLAGwithDifferenceZHImath_ZERO_ALL_EXCEPT_LOWEST_LANEmkVecQANDqrsarNNARROWSUmkVecQANDqsarNNARROWSUmkVecQANDqrshrNNARROWUUmkVecQANDqrsarNNARROWSSmkVecQANDqshrNNARROWUUmkVecQANDqsarNNARROWSSmkVecSHRNmkVecSARNnewTempsV128_3math_QSHL_IMMdis_AdvSIMD_scalar_shift_by_immmkVecZEROHIxxOFV128math_DUP_VEC_ELEMmath_FOLDVmkVecADDmath_WIDEN_LO_OR_HI_LANESmkVecMINFmkVecMAXFdis_AdvSIMD_across_lanesmkVecCATEVENLANESdis_AdvSIMD_EXTsetFlags_ADD_SUB_conditionallygetShiftedIRegOrZRsetFlags_ADC_SBCgen_indexed_EAnameArr_Q_SZgetQRegLaneputQRegLaneputQReg128math_MAYBE_ZERO_HI64math_DUP_TO_64math_DUP_TO_V128nameQRegLOputQRegLOpreferredVectorSubTypeFromSizeoffsetQReg128offsetQRegLanegetQRegLOgen_narrowing_storegen_zwidening_loadmath_INTERLEAVE4_128math_INTERLEAVE4_64math_INTERLEAVE3_128math_INTERLEAVE3_64math_INTERLEAVE2_128math_INTERLEAVE2_64math_DEINTERLEAVE4_128math_DEINTERLEAVE4_64newTempsV128_4math_DEINTERLEAVE3_128math_DEINTERLEAVE3_64math_DEINTERLEAVE2_128math_get_doubler_and_halvermath_DEINTERLEAVE2_64dis_ARM64_load_storemk_arm64g_calculate_condition_dyndis_ARM64_branch_etcmkU8getIRegOrZRnewTempmathREPLICATEmathRORdbm_RORdbm_highestSetBitdbm_DecodeBitMasksputIReg32orZRputIReg32orSPputIReg64orSPsetFlags_D1_D2_NDdis_ARM64_data_processing_immediateoffsetIReg64putIReg64orZRdisInstr_ARM64_WRKdisInstr_ARM64typeOfIRTemp(irsb->tyenv, t_dep1 == Ity_I64)typeOfIRTemp(irsb->tyenv, t_dep2 == Ity_I64)typeOfIRTemp(irsb->tyenv, t_ndep == Ity_I64)typeOfIRExpr(irsb->tyenv, e) == Ity_I64typeOfIRExpr(irsb->tyenv, e) == Ity_V128typeOfIRExpr(irsb->tyenv, e) == Ity_I32typeOfIRExpr(irsb->tyenv, cond) == Ity_I64opZHI == Iop_ZeroHI64ofV128 || opZHI == Iop_ZeroHI96ofV128 || opZHI == Iop_ZeroHI112ofV128mas == 'm' || mas == 'a' || mas == 's'rearrL && *rearrL == IRTemp_INVALIDrearrR && *rearrR == IRTemp_INVALIDlaneSzBlg2 >= 0 && laneSzBlg2 <= 2sat2q && *sat2q == IRTemp_INVALIDsat2n && *sat2n == IRTemp_INVALIDrshift >= 1 && rshift < laneBitsrshift >= 0 && rshift < laneBits-1ext v%u.16b, v%u.16b, v%u.16b, #%u ext v%u.8b, v%u.8b, v%u.8b, #%u gen_indexed_EA: unhandled case optS == 0x%x shift >= 0 && shift < lanebitsshift >= 1 && shift <= (8 << size)fbits >= 1 && fbits <= (isD ? 64 : 32)fbits >= 1 && fbits <= (isI64 ? 64 : 32)%s %s, [%s], #%lld (at-Rn-then-Rn=EA) %s %s, [%s, #%lld]! (at-EA-then-Rn=EA) %sp %s, %s, [%s, #%lld] (at-Rn) %sp %s, %s, [%s, #%lld]! (at-EA-then-Rn=EA) %sp %s, %s, [%s], #%lld (at-Rn-then-Rn=EA) ldpsw %s, %s, [%s, #%lld] (at-Rn) ldpsw %s, %s, [%s, #%lld]! (at-EA-then-Rn=EA) ldpsw %s, %s, [%s], #%lld (at-Rn-then-Rn=EA) %snp %s, %s, [%s, #%lld] (at-Rn) %s%u {v%u.%s .. v%u.%s}, [%s]%s %s1 {v%u.%s .. v%u.%s}, [%s]%s ld%ur {v%u.%s .. v%u.%s}, [%s]%s %s%u {v%u.%s .. v%u.%s}[%u], [%s]%s szB == 8 || szB == 4 || szB == 2 || szB == 1prfum prfop=%u, [%s, #0x%llx] dres->whatNext == Dis_Continuedres->jk_StopHere == Ijk_INVALIDarchinfo->arm64_dMinLine_lg2_szB >= 2 && archinfo->arm64_dMinLine_lg2_szB <= 17 && archinfo->arm64_iMinLine_lg2_szB >= 2 && archinfo->arm64_iMinLine_lg2_szB <= 17arm64g_dirtyhelper_MRS_CNTVCT_EL0arm64g_dirtyhelper_MRS_CNTFRQ_EL0archinfo->arm64_iMinLine_lg2_szB >= 2 && archinfo->arm64_iMinLine_lg2_szB <= 17archinfo->arm64_dMinLine_lg2_szB >= 2 && archinfo->arm64_dMinLine_lg2_szB <= 17op != Iop_INVALID && nm != NULLsat1q != IRTemp_INVALID && sat1n != IRTemp_INVALIDshift >= 1 && shift <= lanebits%c%s%s %s.%s, %s.%s, %s.%c[%u] ARM64 front end: data_processing_register ARM64 front end: data_processing_immediate (archinfo->arm64_dMinLine_lg2_szB - 2) <= 15(archinfo->arm64_iMinLine_lg2_szB - 2) <= 150 == (guest_PC_curr_instr & 3ULL)branch-and-link-to-noredir x8 %s %s.%s, {v%u.16b .. v%u.16b}, %s.%s 0 == (imm & 0xFFFFFFFF00000000ULL)dres.len == 4 || dres.len == 20disInstr(arm64): unhandled instruction 0x%08x ?@GNUzRx <4BBB A(D0b (D BBBI tDP8BED C(F0 (A DBBL 'D[%AA^$$%AA^@%AA^\DPq K x%AA^%AA^%AA^%AA^%AA^%AA^ %AA^0<oFDF0iAAEP00poFDF0iAAEP0%AA^4ADF u ADK D AAJ ( oADF { ADE (LoADF t ADL x_Hj N 0As D L D L D L D L A 4ADF B ADN D AAJ CD_ M K _S8?AU J T?DQ K p%AA^-ON7dK8BEB A(D0 (A BBBD   WR a E <WR a E X)E\t)E\)E\)E\8BDA L FEJ A ABL D_ M  DK I (<BAK M KBH ,hIDF p DBG :(ADF k ADE 0BAA F0{  DABD 8 BEA H(F@ (D ABBE ,HBDA B DBI (xAAD a AAG <BBB E(A0n (B BBBN ,/BAA  ABC 8GFED D(IP (A ABBG HPBEB E(I0A8D@0 8D0A(B BBBG 6H]LHsHu<BGB B(A0i (E BBBF 88 BBA A(D0 (A ABBG ,t .BAC  ABG H BBB B(A0A8DP 8D0A(B BBBG H BEE B(A0A8D`: 8C0A(B BBBF 8< BBA C(K0[ (G FBBI (x D[ Q _ Q k M KH /BBJ E(D0A8F`p 8D0A(B BBBE H /BEJ E(A0A8F@ 8D0A(B BBBK H< BEJ B(A0C8D@[ 8A0D(B BBBM L FBB B(A0D8D] 8A0D(B BBBI L _BBB E(D0A8D 8A0A(E BBBK H( BBB B(A0A8G` 8A0D(B BBBJ Ht BBB J(A0A8D`\ 8C0A(B BBBB H OBBB B(A0A8D@ 8A0D(B BBBH H BBB B(D0C8F@o 8D0A(B BBBG @X BGG | AEN D DBF D ABI H BBE E(A0C8K@a 8I0A(B BBBH H _FBB B(A0A8D` 8A0D(B BBBO <4FBE D(D0 (D BBBK HtFBB B(D0D8Dp 8A0A(B BBBG <FBE D(D0 (D BBBK HFBB B(D0D8Dp 8A0A(B BBBG HL<BEE E(D0A8K` 8A0D(B BBBK HBBB E(D0C8F@ 8D0A(B BBBG `FBB B(D0A8DAIBM 8A0A(B BBBF LH~BBB B(A0A8D 8A0D(B BBBM HBBB B(A0A8D8D0A(B BBBLBBB D(D0p (D BBBH  (D BBBE <4"BBJ B(A0  (E BBBG DtBAG  IBI c IBJ S IBJ LBBB B(A0A8D 8A0D(B BBBO L ?BBB B(A0C8F 8D0A(B BBBA \FBE E(D0D8GpxNHHMp 8A0A(B BBBC xNHHMpxNHHIp`FBB B(D0A8DAIBM 8A0A(B BBBF HH>BBB B(A0A8Gp 8A0D(B BBBL xLFE E(A0A8DL8A0A(B BBBHH 8F0A(B BBBE HBBB B(D0A8DPY 8D0A(B BBBI `\JGE E(A0A8DPK 8A0A(B BBBJ HHPPDEE I(F0N (D BBBK ) (D BBBE tFEE B(D0D8Jv M_AG 8A0A(B BBBH ' FS ' MU tFBB E(D0A8D&AAD 8A0A(B BBBI  8A0A(B BBBD lU-FBB B(D0D8J 8A0A(B BBBJ H:A! H ttFBB E(D0A8D&AAD 8A0A(B BBBI  8A0A(B BBBD HwDE E(D0A8T`W 8A0A(B BBBA \8oLEB B(A0A8D`[8A0A(B BBBHH`(+AC Me J BDE B(A0A8DY 8D0A(B BBBG QCwBU`KBUHAiKAdX gDE G(K0K8XP. 8A0A(B BBBC D 8C0A(B BBBA pH pGL M(K0K8P_8A0A(B BBBAH[HXA`4kHK K(J0E8T8A0A(B BBBGHdkDH I(K0K8VtHV 8A0A(B BBBA $^EEF E(E0A8G 8A0A(B BBBI JA}CIACIBFGJBIKSBMDDIaEQAAHWA BADULJJJ\BADUL(BBB B(A0D8L 8A0A(B BBBF HxBBB B(A0A8G[ 8D0A(B BBBG \P|HH K(K0L8I 8A0A(B BBBE  KLF$ BDE B(A0A8DZ 8D0A(B BBBF 8EkA}GOEI0DBAV^AHEIGuIMEM DBAI  BBB B(A0A8G[ 8D0A(B BBBG AXBHXAEIPMJETMwKRA>HKKIHYB/ FE 5KgA4sFK K(L0M8Z\8D0A(B BBBEPFAAUFBA] BBBP JBCBOLSQWEHH  FBGE ) IABH ALEHBU FABJ rFH J(J0L8^ 8D0A(B BBBI  IOA.SJBErIoJIA\ dHE K(J0K8VGXFR 8A0A(B BBBH d wFK J(K0M8TBH  8A0A(B BBBE 4| kIK L(L0J8dABBUM8D0A(B BBBHH/ GBBF M ABBE SfACEIEBNDeBNCBIAIEHB]EOOTRGoA!.DEE D(D0A8G 8A0A(B BBBD ^RkFHYAoANF)_HFXH"~GH K(K0L8Mp 8A0A(B BBBB cxCFxFpl"BDH E(A0A8GAFAfPPAF 8A0A(B BBBD #^FBB E(D0I8G 8A0A(B BBBG  HXB HYBALEIGoDGBHXBDkAFbAHYBHXAJUBCFBCFAHYAPLHADkBMDjAKEkAG]BNG]BDjAHHGIG\AJOIBDjBDjAPCBAIqDkBHXA^HYADjBKsB{HXA3HXAHXBHYB  9`Rpk}`'%( $ @ @%3pL %azP %  %P%8%Wp%p%P %0@ o(A oQj %z P p  8 o o  _$t =P H @T @` @l @x @H   C _0?@p?%%8Q-f7tP"PW `W  ")9)M )cP)x @ 4  ' @:MWX p! @8*@/OhGs( @ 6! !Lp!"#  @%.0 I p&[ t `(} +  , 0 ,/ 0  // & 01D ] 03 t   =_ @  `C GO  % PJ' X@ pLL M] N_h    S   U  W P% Y; T \<s P ` p c  h~ P Pn v- F y"W 0p }    ?   P& ?@>Mf@` 0$=S0lU-@ ` o0+/ H T `J@ Pe @ "nH @y+ #D m` "^p $  $5NnP   * %$6 J`c |P pW0PkP `5 A M f@ " . @5`$yHh#P    $f#)>.G3W87=uBGMSY_ekqw}0` !* 9  K%+T1f7|=CIOU[agmsy/KU^@|@hD3Y !t'-39?EKQX^ekry0nJ1X:|.,/ dk!(/r6O=VDKRYH`]g~nvu(|z cg:Lz$+29@GNoU%\"c1jq6xH}N',<B`U\ 9d T'l.t5t<CJyQX_fmt{   %     ; ,  ;        # * 1 8P?xF`MT` [] bM iP pS w ~ ~   0    "  (U . { c A   P  &H -4 ;BI P W ^j e( l sm zB U   a {     7  S   [   m   =  "* ) 0 7p> E LSv Z" a h ov }`N b  C K                  % , 3: AHDOiVU]wd8k>rPyJP*1X?H"P ( / 7 j! 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A@H=C>1DH=G<1DH=+<1zDH=;1^DH=#;1BDH=R";1&DDH=391DEA AEAADD5H1ADD+"1DDH=n91DDH=L91kDDH=H0*91IDDDE AH=@u;1DDDE AH=;@;1DDH=81DDH=|81DDDE AH=O^W:1fDDH=s%81DDDDE AH=p:1DEEAAADD/H1ADD+R1DDDE AH= u91DDDE AH=ع@91ODDDE A@H=߷ 91DDDE AH=81DDH=91EHAD<HHHHH8= DEHHAAD‹EXZHIIHHHI,UAAI PH0H4DAAH==DA\A]IHIIHHHI,ARAI APH0H4AADH=HIIHHHI,WAI$APH0H4AADH=g"/AXAYPHIIHHHI,AI$APH0H4AADH=.XZHIIHHHI,UAAI$PH0H4DAAH=z.A\A]AIIHHI,IAH=c|H0AH4AADsIIHHI,IAH=~{H0AH4AAD|sIIHHI,IAH=zH0AH4AAD7srIIHHI,IAH=yH0AH4AADr-IIHHI,I AH= AH0AH4ADIIHHI,I AH=7AH0AH4ADIIHHI,I AH=/AH0AH4ADUIIHHI,I AH=AH0AH4ADB IIHHI,I AH=TAH0AH4ADIIHHI,I AH=2AH0AH4AD}IIHHI,I AH=AH0AH4ADj5IIHHI,I AH=AH0AH4AD"IIH=0HI,H4IAH0΃ADuIIH=#HI,H4IAH0΃AD8sIIH=VHI,H4IAH0΃AD6IIH=YHI,H4IAH0΃ADIIHHI,IAH=kH0AH4AADyol9IHHϾIH HL$H4ADDDL${HL$DDHH0[HL$DH,σ=DL$ADDDDDL$DL$HPD1ESUXZIIHHI,IAH=H0AH4AADZnIIH=XHI,H4IAH0΃ADXIIH= HI,H4IAH0΃AD7HHϾHHH4HL$ÃH @HL$ھDHH0HL$ھDH,σDD؉}H}AADD1`IIHHI,IAH=H0AH4AADlIIHHI,IAH=~H0AH4AADlIIH=wHI,H4IAH0΃AD^IIH=lHI,H4IAH0΃AD!\IIH=HI,H4IAH0΃ADIIH=ҜHI,H4IAH0΃ADHIIHHHI,ARAI$APH0H4AADH=j%A[[HIIHHHI,WAI$APH0H4AADH=q%AXAY8PHIIHHHI,AI$APH0H4AADH=!%XZIIHHI,IAH=H0AH4AADejHIIHHHI,AI(AH0PHH4DH$AAH=PjA\A]AIIHHI,IAH=H0AH4AADqjIIHHI,IAH=NH0AH4AAD,j鷿HIIHHHI,AI AH0PHH4H(AADH=P[]ZHIIHHHI,AI AH0PHH4H(AADH=P$AZA[IIHHI,IAH=yH0AH4AAD{h鶾HIIHHHI,WAI$APH0H4AADH=ߨ"AXAYaPHIIHHHI,AI$APH0H4AADH=E"XZIIHHI,IAH=`xH0AH4AADgɽIIHHI,IAH={wH0AH4AADIg鄽IIHHI,IAH=vH0AH4AADg?IIHHI,IAH=uH0AH4AADf0HIHϾHIHHH4DHL$H$T$H A܈D$AHL$T$H0σ|$D4AEAE  QH5]UEUDL$Dщ1A^_ /IHϾHIH4HL$AHDHL$DDHH0HL$D]5HHcHD4H Ӊt$xt$DHeADDDH5]1@IAH=HH4IAH0AD<IIIHI H4H=II0AH,AAD鼺IAH=-HH4IAH A҃DH郺IAH=,HH4IAH A҃DJIAH=m-HH4IAH A҃DIAH=,HH4IAH A҃DعIAH=kHH4IAH A҃Dd韹IAH=2HH4IAH A҃D+fIAH=yHH4IAH A҃D-IIIHI H4H= II0AH,AAD7HIIHHHI SI0AH,PAH4DAAH=Ȃc]A\鋸HIIHHHI AQI0AH,PAH4AADH= AZA[2IIIHI H4H=KII0AH,AAD\HIIHHHI AUI0AH,PAH4AADH=|gXZ鐷IIIHI H4H=5II0AH,AADEHIIHHHI WI0AH,PAH4AADH=AXAYIIHHI,IAH=vH0AH4AADm`騶IIHHI,IAH=uH0AH4AAD(`c*HIHH4HH,I08H-ADË|HHD$Aŋ|IHT$HDHneADDH51頵IIHHI,IAH=H0AH4AAD _[IIHHI,IAH=H0AH4AAD^IIH=HI,H4IAH0΃ADٴIIHHI,IAH=+H0AH4AADY^锴IIH=WsHI,H4IAH0΃ADWIAH=xHH4IAH0ADSIHH4H==dIH0ADe'IHϾHIH4HL$H$ADHL$DDH0σىDDDHgAADD]1JIAH=] HH4IAH0ADFIAH=DxHH4IAH0AD زIIH=HI,H4I AH0΃AD]X防IIH=%HI,H4I AH0΃ADXXIIH=KJHI,H4I AH0΃ADWIIH=K]HI,H4I AH0΃ADWرIIH=\HI,H4I AH0΃AD]W阱IIH= HI,H4I AH0΃ADWXIIH=˞HI,H4I AH0΃ADVIIH=;GHI,H4I AH0΃ADVذIIH=+EHI,H4I AH0΃AD]V阰IIHHI,I AH=*jAH0AH4ADPIIHHI,I AH=iAH0AH4AD]IIH=k9HI,H4I AH0΃ADUȯIIHHI,I AH=ZAH0AH4AD逯IIHHI,I AH=nAH0AH4AD8IIHHI,I AH=AH0AH4ADEIIHHI,I AH=AH0AH4AD騮IIH=GHI,H4I AH0΃AD-ThIIH=8HI,H4I AH0΃ADS(IIH=kHHI,H4I AH0΃ADSIIH=5HI,H4I AH0΃ADmS騭IIH=k7HI,H4I AH0΃AD-ShIIH=EHI,H4I AH0΃ADR(IIHHI,I AH=鹣IIHHI,I AH=4AH0AH4ADqII0L%H=H=H=H=H-HHHcH>IIHHI,I AH=üAH0AH4ADn|ɢIIHHI,I AH=+AH0AH4AD遢IIHHI,I AH=cAH0AH4ADn9IIHHI,I AH={3AH0AH4AD&IIHHI,ARAI j H0AH4ADAH=njA[[颡IIHHI,WAI j H0AH4ADAH= AXAYSIIHHI,PAI jH0AH4ADAH=XZIIHHI,UAI j H0AH4DAAH=A\A]鷠IIHHI,I AH=AH0AH4ADoIIHHI,I AH=aAH0AH4AD\'IIHHI,I AH=AH0AH4ADߟIIHHI,I AH=AH0AH4AD闟IIHHI,I AH=)AH0AH4ADOIIHHI,ARAI jH0AH4ADAH=ͿA[[IIHHI,WAI j H0AH4ADAH=zAXAY鱞IIHHI,I AH=CAH0AH4ADiIIHHI,I AH=AH0AH4ADV!IIHHI,I AH=SAH0AH4ADٝIIHHI,I AH=AH0AH4AD鑝IIHHI,I AH=AH0AH4AD~IIIH=\HI,H4I AH0΃ADB IIH=HI,H4I AH0΃ADBɜIIH=HI,H4I AH0΃ADNB鉜IIH=HHI,H4I AH0΃ADBIIIH=GHI,H4I AH0΃ADA IIH= HI,H4I AH0΃ADAɛIIH=HI,H4I AH0΃ADNA鉛IIH= .HI,H4I AH0΃ADAIIIHHI,I AH=VAH0AH4ADVIIHHI,I AH=sUAH0AH4AD鹚IIH=l3HI,H4I AH0΃AD>@yIIH=4HI,H4I AH0΃AD?9IIH=3HI,H4I AH0΃AD?IHHAI H,H=>AH0@ADP黙IHHAI H,H=0AH0@AD}IHHAI H,H=rAH0@ADԢ?IHHAI H,H=AH0@AD薢IHHAI H,H=F$AH0@ADØIHHAI H,H=)AH0@AD躣酘IHHAI H,H=*'AH0@AD|GIHHAI H,H=<%AH0@AD> IIHHI,I AH=AH0AH4ADfIIHHI,I AH=AH0AH4ADyIIHHI,I AH=AH0AH4ADf1IIHHI,I AH=sAH0AH4ADIIHHI,I AH=AH0AH4ADֻ顖IIHHI,I AH=AH0AH4ADYIIHHI,I AH=;AH0AH4ADVIIHHI,I AH=AH0AH4ADɕIIHHI,I AH=[AH0AH4AD趺違IIHHI,I AH=sDAH0AH4ADn9IIHHI,I AH= AH0AH4AD&IIHHI,I AH=sAH0AH4AD޹驔IIHHI,I AH=ˤAH0AH4AD薹aIIHHI,I AH=cAH0AH4ADNIHHAI H,H=NAH0@ADpۓIHHAI H,H=PAH0@AD2靓IIHHI,I AH=AH0AH4AD芸UIIHHI,I AH=AH0AH4AD費 IIHHI,I AH=?AH0AH4ADjŒIIHHI,I AH=)AH0AH4AD"}IIHHI,I AH=AH0AH4ADں5IIHHI,I AH=AH0AH4AD"H4H=5΃6ёH4H=Ti΃鵑H4H=΃陑H4H=΃}H4H=0΃ƸaH4H=΃誸EH4H=΃莸)H4H=΃r H4H=΃VH4H=΃:ՐH4H= ΃~鹐H4AAK HH8AEtsHcHA) ADHH=H1HHDHD$HT$+HHHMAԉl1H4H='5΃ݶȏH4H=K΃q鬏H=ˎH=ώHH8H-H8bHHcH>H-H wHHcH>H4H=΃3H4H=&D΃ܵH4H=΃H4H=^A΃褵ߎH4H=΃舵ÎH4H=V7΃l駎H4H=΃P鋎H4H=@΃4oH4H=΃SH4H=A΃7H4H= ΃IIaHJcH>HH,DH=H DFHH,DH=OH DX铍HH,DH=H DeHH,DH=H D7HH,DH=H D HH,DH=WH DیHH,DH= H Dr魌HH,DH= H DDHH,DH=H DQAD陊,H-HHHcH>H4H=΃TH4H=R΃8ӋH4H=΃̲鷋H4H=:΃谲雋H4H=΃H4H= ΃ȲcH4H=&΃\GH4H=΃@+H4H=΃tH4H= ΃XH4H=|΃׊H4H=΃б黊H=H=H-HHHcH>H4H=%΃+fH4H=yq΃JH4H=M΃.H4H=s΃װH4H=΃軰H4H=9΃蟰ډH4H==r΃胰龉H4H=v΃g颉H4H=t΃K醉H4H=)w΃/j]H4H5[1Hʉ9H4H= ΃H=}H=YH-H aHHcH>H4H=΃-ȈH4H=˭΃鬈H4H=o+΃襯鐈H4H=΃良tH4H=w΃mXH4H=K΃<1HHD$ 1HL$ HHL$ IёHھHL$ H<HL$ Hɑ1HHL$IfHH<H鰬1HHL$HɩD։DDT$vDT$VH H5H=H=IHAAI H,AAAAH=DIHAAI H,AAAAH=fD蹉餆ADIHAAI H,AAAAH=K\DcN藳HHX&IHAAI H,AAAAH=YDIHAAI H,AAAAH=^$Dƈ鱅HHAH \$H,HfADD$ f\$(H1A\$H1Ѓ\$0HHȃ%H tnAAЋL$t$AADH=c9$IHAAI H,AAAAH=0dDLD$8Ķ踶A諶LD$8|$0D$LD$0VDLD$0H|$(LD$0HT$8HHT$8HDHH=HLD$0A l$ 1HHHHD$ HDHD$HT$HLD$ HLH=H9s1HI蛵LljH=H11xAU1EH5jT$ L$AXZL1HLD$0HHG{HDHHڿH\$HƉ 1CILH讠HILHIHHH8=ukLH=H|$HIL+HH1HH DH H5H=ff.HAWHAVAUATUSHH#H96HH9MvCHH9h@@H{HH[]A\A]A^A_DH'HH9@@HU{HH[]A\A]A^A_ÐHH9HH9u+@@HS9{HH[]A\A]A^A_HH9@ H_zHH[]A\A]A^A_D@ H^zHH[]A\A]A^A_D@ H`^zHH[]A\A]A^A_DAAܱAń1HDH0-DILHIHLHDH蛙H=HDIL,HDHaDHHH51HDHHHEH=HH=HHH=HHHH=HDHuHH=txHHH[]A\A]A^A_fDHHHH51HHH=HH=HHH=HHHH=HHHPH=HH4H@@ HH[]A\A]A^A_f@@Hp[wHH[]A\A]A^A_DÀw4H<xHDHɖ迧H=16DATUSHH8H=AHH@H cUH5H=H=s390_cc_widenpriv/guest_s390_toIR.cs390_calculate_conds390_calculate_ccarchreg < 16archreg < 32rxb < 16s390_vr_get_type: m=%x lpqisPlausibleIRType(type)m5 < 3s390x_dirtyhelper_vec_opvmahvmalhvstrcm4 < 3vfae(m5 & 0b1100) == 0vfeem3 < 3(m5 & 0b1110) == 0vistrlochimvclevalue < 256clmhs390_do_cu12_cu14_helper1s390_do_cu12_helper2s390_do_cu14_helper2s390x_dirtyhelper_CUxycu14cu12value < 65536vgefvgegvlefvlegvlehvlebstcmhs390_do_ecagecagr1 % 2 == 0r2 % 2 == 0(r1 != 0) && (r2 != 0)s390x_dirtyhelper_PPNO_querys390x_dirtyhelper_PPNO_sha512ppnolfpcsrnmbsrnmiihhiilliihliilhvleihvleifvleibvleigbrcthstfhstocgstchstcystcstgstdstesteystdysthhsthsthymvhhiesxtreextrstocstystocfhststfpcmvhimvghis390_do_cvdcvdymvimviysthrlvstegvscefvscegvstebvstehvstefstgrlstrlcvdlzxrldeesdtreedtrsrnmtsllgipmstrvhbctgbrctgsllsllkstpqv3 >= v1v3 - v1 <= 16vstmstcmstcmytcebtcxbtcdbclsts390_do_cu41cu41s390_do_cu42cu42brctbcticicyclclecdlftrcdftrencode_bfp_rounding_modemsdbrmadbrmsebrmaebrmsdbmadbmsebmaebs390_do_cu24cu24lpgfrlngfrstrvrllgvstvlgvs390_do_cu21cu21mvcinmvcs390_irgen_VEC: unknown typevecs390_irgen_VECL: unknown typeveclltebrltdtrltdbrrlllpdfrldebrlcdfrcdfbrencode_dfp_rounding_modecdlgtrclfxtrclgxtrcfxtrcdgtrcdgtraldxtrledtrclfdtrclgdtrcfdtralcrs390x_dirtyhelper_STFLEstflecpsdralcgralclcebrlcdbrlpebrlpdbrslagtmlllndfrchhrtmhhtmhlchlrtmlhcgrclhlrclgrclrclhhrcrclrtcrtclgrtcgrtalcgpopcntltldebslbrcsgcltclgtslbgrsqebrlndbrcghiclfifiebrasqdbrclihcficihfidbrachiclgficgfilnebrslbcgfrclgfrrxsbgrosbgrnsbgslakslaslbgchhsibastmyclhfcliyclgcltmccgcycliltgfclhhsiclychficmhclcsldlsrdlclmyclmcscsysqeblzrfcghsiclghsichsilzrgsqdbs390x_dirtyhelper_STCKstcks390x_dirtyhelper_STCKEstckeclfhsibctgrlaelaeylalaysrdachychcgfs390x_dirtyhelper_STCKFstckfclgfcghiihficmyicmtdgdtlexbrtdcxttdgetcdlfbrldxbrledbrcegbrldetrcdgbrcrlcgrlclgrllrvhcefbrtdgxttdcettdcdtclrltrmdtrmdtraddtrddtraalsihnllilflghilgfillilllfhatnihhoihlsldtoihhnihlcgxtrcgdtroilhnillnilhoillclgxbrlatclfdbrcelfbrcelgbrsrdtclfebrclgdbrclgebrcdlgbrlgatclfxbriedtrefpcvstllocfhlfhadtradtrasdtrsdtrallgfrlgbrllihlllghrlgdrllilhlgfrllgcrllihflghrllihhmvstrrdtrqadtrsrlsrlgsrlkclgfrlclhrlcgfrlchrlclghrlcghrllocglgoilfmsfixihfcfebrnihfxilfcfxbrcgxbrnilfoihfcfdbrcgdbrcgebriilflhisrstmghillgfatllzrgfmhilarlllcrlhrlbrllhrbxlegbxhgbrxlebrxlgbrxhgbxlebxhbrxhbctrllchlbhllhhlhhlyllocstmstmystmhstmgstamstamymsgfinixiyoiyniyxioilerldrstrvglmlmylmhlmglamlamymsgrogrkogrngrkngrxgrknrxrknrkormsrorklghllgflgblgfllgcllghsgralgralgrkagrslgrslhhhralhhhragrkshhlrslgrkahhlrahhhrslhhlrsgrkalhhlrshhhrslrksrslraralrarksrkalrkm = %d lcbbbrasbraslclibcibdsgdsgfdsgrdsgfrs390_do_cvbcvbycvbflogrdebrddbrmdbrmeebrlgrlllclhylbllhlhvlrvmxvmnvmxlvmnlvsvavavgvavglvmaevmalevmalvmevmlevmhvmlvmlhvpkvesravvesrlvverllvveslvvxvovnvmrhvmrlvlpvuphvuplvuplhvupllvnovncvclzvctzm3 == 0vpopctm5 == 4vsbivacvselvesravesrlverllveslvsbcbivacccvcksmvlmvlvmaovmalovmovmlovfenevsrabvsravsrlbvsldbvslbvslverimvchvchlvceqvpksvpklsvperms390_irgen_VLVG: unknown typevlvgm3 < 4vlcvscbivaccm4 == 3vfchvfchevfces390_vr_fill: invalid IRTypefrom <= tos390_irgen_VGM: unknown typevgmvlrepvrepivsumqvsumgvsumvgbmvfmsvfmavfsqvfsvfavfdvfmmsgfrlzerlzdrslgfragfrmsgsgfrmsogoalgfroyxyngxxgnnymsytreadbrllgtatsebrsdbraebrvtmsrasgsslysrakalgagslgaysragalysyaalslvllvlbb(m4 & 2) == 0(m4 & 8) == 0vpdivllezvfpsos390_irgen_VSEG: unknown typevsegvclgdvcdlgvcgdvcdgvldevledvfivcgldltgrlaxglaoglanglaxlaolanlrlbcaihslfilcgrahikaghialfiaghikafialsihalghsikahiagfialgfislgfilcralhsikclfitcitclgitcgitlocfhrcdsgsldaleyleldylddebddbmdbmeebcextrcedtrcxtrcdtrcxbrkxbrcdbrkdbrcebrkebrwfcwfkcdbkdbcebkebmsgfmhymhllghrllgfrllghrlllgtrllgfrlltrvgfmsgfahyslgfshahalgfagfshydrdlrddldlgdlgrlrvglocgrlrvgrsfpcxcocncmlradbmlgrsebaeblcgfrmrsdbxgrxrlaalglaaglaallaalochhis390x_dirtyhelper_EXtrootrtolrvcgibclgibltgfrllhrllhrllxrrisbgrisbgnltgclgijclijcrbcgrbclrbclgrbcgijcrjcgrjclrjclgrjltxtrlxdtrcxlftrcxlgtrcxftriextrcxgtrsrxtslxtrrxtrqaxtrsxtrsxtraaxtraxtradxtrdxtramxtrmxtratrottrttlocrldercxgbrcxfbrlcxbrltxbrlnxbrlpxbrlxebrlxdbrcxlgbrcxlfbrfixbrasqxbrlxeblxdbs390_do_pfpopfposvcdxbrmxbrsxbraxbrasialgsiagsialsilrvrlocghilprlngrmlgmfylnrmmllpgrvgfmacdscdsylgrlrllgtcijbasrvsrlrisbhgrisblgcpyasarearldgrpfdvftcivrepvlvgppfdrlvex s390->IR: unknown insn: unimplemented insn: unimplemented special insn: specification exception: decoding error: s390_decode_and_irgen%02x%02x %02x%02x ex@mvcex@clcex@xcex@ocex@ncex@trex@mvcinex which was executed by exrlguest_arch == VexArchS390XdisInstr_S390_WRKtypeOfIRExpr(irsb->tyenv, emwarning) == Ity_I32s390_vr_offset_by_index: unknown types390_vr_offset_by_index: index = %d ; type = s390_vr_offset_by_index: invalid index for given types390_vr_get_type: reserved m valuetypeOfIRExpr(irsb->tyenv, expr) == Ity_I64typeOfIRExpr(irsb->tyenv, expr) == Ity_I32typeOfIRExpr(irsb->tyenv, expr) == Ity_I8typeOfIRTemp(irsb->tyenv, cc) == Ity_I64typeOfIRExpr(irsb->tyenv, condition) == Ity_I1s390_V128_get_complement: unknown types390_V128_calculate_carry_out: unknown typetypeOfIRExpr(irsb->tyenv, expr) == typetypeOfIRExpr(irsb->tyenv, emfailure) == Ity_I32s390x_dirtyhelper_PPNO_sha512_load_param_blocks390x_dirtyhelper_PPNO_sha512_save_param_blocktypeOfIRExpr(irsb->tyenv, expr) == Ity_I16typeOfIRExpr(irsb->tyenv, expr) == Ity_F32typeOfIRExpr(irsb->tyenv, expr) == Ity_F64typeOfIRExpr(irsb->tyenv, expr) == Ity_D64s390_irgen_VLGV: unknown o2typetypeOfIRExpr(irsb->tyenv, expr) == Ity_D32guest_IA_next_instr - guest_IA_curr_instr == S390_SPECIAL_OP_PREAMBLE_SIZE + S390_SPECIAL_OP_SIZEdis_res->whatNext == Dis_Continues390_getCountToBlockBoundary: invalid mtypeOfIRExpr(irsb->tyenv, expr) == Ity_V128m4 < sizeof(ops) / sizeof(ops[0])m5 < sizeof(mul_ops) / sizeof(mul_ops[0])(index >= 0) && (index < sizeof(ops) / sizeof(ops[0]))m3 < sizeof(ops) / sizeof(ops[0])m5 < sizeof(ops) / sizeof(ops[0])s390_irgen_VREPI: unknown types390_irgen_VSUMQ: invalid type s390_irgen_VSUMG: invalid type s390_irgen_VSUM: invalid type s390_irgen_VLLEZ: unknown types390_irgen_VFPSO: Invalid m5 value?s390_format_RSY_RDRMs390_vr_getVRindexs390_irgen_VESLs390_irgen_VERLLs390_irgen_VLMs390_irgen_VESRLs390_irgen_VESRAs390_irgen_VSTMs390_irgen_VGMs390_irgen_VPOPCTs390_irgen_VCTZs390_irgen_VCLZs390_irgen_VISTRs390_irgen_VMRLs390_irgen_VMRHs390_irgen_VESLVs390_irgen_VERIMs390_irgen_VERLLVs390_irgen_VESRLVs390_irgen_VESRAVs390_irgen_VFEExz{%&'s390_irgen_VFENEs390_irgen_VFAEput_vr_dw0s390_irgen_VPDIs390_irgen_VSTRCs390_irgen_VPKs390_irgen_VPKLSs390_irgen_VPKSs390_irgen_VMLHs390_irgen_VMLs390_irgen_VMHs390_irgen_VMLEs390_irgen_VMLOs390_irgen_VMEs390_irgen_VMOs390_irgen_VMALHs390_irgen_VMALs390_irgen_VMAHs390_irgen_VMALEs390_irgen_VMALOs390_irgen_VMAEs390_irgen_VMAOs390_irgen_VACCCs390_irgen_VACs390_irgen_VSBCBIs390_irgen_VSBIput_vrput_vr_dw1s390_irgen_VUPLLs390_irgen_VUPLHs390_irgen_VUPLs390_irgen_VUPHs390_irgen_VLCs390_irgen_VLPs390_irgen_VFCHs390_irgen_VAVGLs390_irgen_VAVGs390_irgen_VAs390_irgen_VSs390_irgen_VCEQs390_irgen_VCHLs390_irgen_VCHs390_irgen_VMNLs390_irgen_VMXLs390_irgen_VMNput_vr_qw@P`p 0@P`p 0vr_offsets390_irgen_VMXput_gpr_hw0put_gpr_hw1put_gpr_hw2put_gpr_hw3mkU16s390_cc_setput_fpc_w0emulation_warning_with_exprput_gpr_b3put_gpr_b2put_gpr_b1put_gpr_b0s390_irgen_PPNOput_gpr_w0restart_ifput_counter_w0put_counter_w1put_counter_dw0if_condition_gotoput_ar_w0  $(,048<put_gpr_b7put_gpr_b6put_gpr_b5put_gpr_b4put_dpr_dw0put_dpr_w0emulation_failure_with_exprmkU8if_condition_goto_computediterate_ifnext_insn_ifmkiteput_gpr_w1newTempput_fpr_dw0put_fpr_w0@P`p 0fpr_offset@HPX`hpxgpr_offsetput_gpr_dw0s390_decode_special_and_irgendisInstr_S390GNUzRx (BMD dEB4HoBBA A(H0J(G GBB$GUDPLBAC y ADT K ABJ G ADT G ADN 4nBGE A(J0}(G HBB48kBDD A(F0C(G GBB8pBGB B(D0w(B BBB8BGB B(D0w(B BBBA[ D 5Al$'D[0<MBIN P BBC DKI0pMBIN P BBC DKI0MBIN P BBC DKI0LBKI P ABG DJI0 LBKI P ABG DJI4@MBIH U BBD GHIx4BX F O4BX F OHeBIH G(L0P (A ABBD D(J DEIHeBIH G(L0P (A ABBD D(J DEI0PMBIN P BBC DKIHeBIH G(L0P (A ABBD D(J DEIHeBIH G(L0P (A ABBD D(J DEI4MBIH V BBC GHIHTaBIH G(I0P (A ABBG D(J HDB4MBIH V BBC GHI4NBLH R BBD HHITmBHE E(H0X (A BBBE N8J@K8A0A(A BBBThlBIF H(K0T (A BBBA D8K@S8A0A(A BBB4MBIH U BBD GHITmBLE H(K0P (A ABBD M8I@K8A0D(A ABBTPnBHE H(O0P (A ABBD N8I@K8A0D(A ABBTmBIH H(K0P (A ABBD M8I@K8A0D(A ABB4NBLH R BBD HHI08MBHM P BBE DKI0lMBHM P BBE DKI0MBHM P BBE DKI4BDB A(D0(A BBB< BBB D(E0 (A BBBB 8L BEA C(F0W (G DEBF 8 BBD A(F0] (G GBBJ ( BLA uBB %AA^ )d )d4 %AA^4P G@ I _ Q W I W I S M  ;\ $AAJ( uADF x ADH ( FAC rHB( uADF { ADE (< uADF { ADE (h uADF { ADE ( uADF { ADE ( uADF { ADE  _Hj N ( uADF x ADH 4 ?AU J HP FBF F(E0E8FPY 8H0A(B BBBB H FBF F(E0E8FPY 8H0A(B BBBB , IDA ^ BBH H FBE F(E0D8H` 8H0A(B BBBH Hd FBE F(E0E8FP9 8H0A(B BBBC H FBE F(E0C8FPG 8H0A(B BBBG H BEB E(E0C8FP 8H0A(B BBBH (H_IEG \ BBK 8tBBB E(D0(E HBBoH~ J 4uFBD C(H0P(H ABBoH~ J H FBB J(A0A8Fp8H0A(B BBBloH~ J ?DQ K LuFBB B(A0A8F~ 8H0A(B BBBE L7BBJ F(A0C8M 8A0D(B BBBL D&H]\)H`t?DQ K \|BAA T IEJ X IEJ ` IEJ x IEJ u IEE PBEE A(I0 (D EGBM d (D EGBJ (DoBDD s DBM $pIECH oHA$IECH oHA$IECH oHA$IECH oHA$IECH oHA$8IECH oHA4`{BBB A(K0Q(G HBB4{BBB A(K0Q(G HBB4yBGE D(D0K(M BBBHGFBE E(A0A8FPj 8H0A(B BBBK TA[ D tt"BBE B(A0A8DP 8A0A(B BBBI D 8F0A(B BBBM V8G0F(D BBBtBBB E(A0A8DP 8A0A(B BBBD D 8F0A(B BBBE H8G0D(E EGDtdBBB E(A0A8DPk 8A0A(B BBBJ I 8J0D(E GDBG D8F0A(B BBBtBBB E(A0A8DP 8A0A(B BBBG H 8G0D(E EGDH D8F0A(B BBBtTBBB E(A0A8DP 8A0A(B BBBD V 8G0F(D BBBK D8F0A(B BBBtBBB E(A0A8DP 8A0A(B BBBG D 8F0A(B BBBE H8G0D(E EGDDuE[ H LHdFBB B(A0A8Dp] 8H0A(B BBBH EW D sAj E B,FBA  IBA , LJA  IBD (PEAI V HAB (|EAI Y HAG (EAI Y HAG (EAI Y HAG $@ECI eHA$(MECI rHA$PMECI rHA$xMECI rHA(BGG  ABB (BGG  ABB 8FBA H(F0 (H ABBF (4mFAD M HBF (`mFAD M HBF (uFAD P HBK (uFAD P HBK (uFAD P HBK (mFAD M HBF (<FAD M HBF (hFAD M HBF (FAD M HBF (FAD M HBF (uFAD P HBK (uFAD P HBK (DuFAD P HBK $pUFDF zHB(oBAA x IEF (oBAA x IEF TE[ H kTE[ H k(0uFAD P HBK (\uFAD P HBK (uFAD P HBK (uFAD P HBK $TFFK rHB$UFDF zHB$0VFEF zHB(XFAD  HBG $VFEF zHB$VFEF zHB(FAD b HBI $bFHK ~HB$(bFHK ~HB$PbFHK ~HB$xbFHK ~HB$bFHK ~HB$bFHK ~HB(FAD a HBJ (FAD b HBI (HFAD  HBJ (tADF x ADH (ADF x ADH FE@$`FDL HB( ADF x ADH < E[ H @ H ` E[ H @ H , FBA  IBD 8 FEA C(K0u (H ABBD , FAA  HBJ 8 !FBA A(D0 (H ABBF <\!FBB A(C0 (H BBBE 8!FBA H(H0 (H ABBH ,!FAC z HBB 8"FEA C(K0x (H ABBA 8D"FBA A(D0 (H ABBK <"FGE D(A0 (H BBBE H"GFBE E(A0A8FPj 8H0A(B BBBK H #GFBE E(A0A8FPj 8H0A(B BBBK ,X#FDA k HBH ,#FDA W HBD ,#FDA k HBH H#JFBE F(A0A8D`8H0A(B BBBH4$~FBB B(A0H8MpJ8H0A(B BBBH$FBB J(A0C8L`I 8H0A(B BBBB 8$FBA H(H0 (H ABBE <%FBB D(A0 (H BBBC (H%EAH c HAF (t%EAH c HAF H%FBB J(A0A8F8H0A(B BBBD%LAA  HBF K HBK K HBK D4&LAA  HBF K HBK K HBK 4|&BGB A(D0(I EBB(&6BAD h DBK H&FBB B(D0C8H@ 8H0A(B BBBA H,'FBB B(D0C8H@ 8H0A(B BBBA Hx'FBB B(D0C8H@ 8H0A(B BBBA H'FBB B(D0C8H@ 8H0A(B BBBA H(FBB B(A0E8FP 8H0A(B BBBA H\(FBB B(A0E8FP 8H0A(B BBBA H(FBB B(A0E8FP 8H0A(B BBBA H(FBB B(A0E8FP 8H0A(B BBBA H@)FBB E(E0A8IpT 8H0A(B BBBE H)EFBB B(D0A8K@ 8H0A(B BBBE H)EFBB B(A0A8K@ 8H0A(B BBBH 8$*FBA A(D0e (H ABBH H`*uFEB E(A0A8K@; 8H0A(B BBBE *Cd$*NFEF rHB<*wBBB A(A0 (H BBBD H(+FBB B(A0C8Np 8H0A(B BBBC 8t+@FEE B(I0(B EBB8+FBD C(K0[ (H ABBF 8+@FEE B(I0(B EBB8(,FBD C(K0[ (H ABBF d,Cd<x,FBB A(F0$ (H BBBE <,FBB A(F0! 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Your platform probably doesn't support MIPS32 DSP ASE. vex mips->IR: unhandled instruction bytes: 0x%x 0x%x 0x%x 0x%x jmp_lit32jmp_lit64disInstr_MIPS_WRKdisInstr_MIPSnewTempmkNarrowTo32putIRegintegerGuestRegOffsetgetIReggetDSPControlgetAccaccumulatorGuestRegOffsetGNUzRx DZ R 8DY K T$GUl%AA^%AA^,BEA   EBE ,BEA   EBF 4BID  AEI ^ AEL 8<BBA D(F0 (A ABBD <xBBE A(D0Q (D BBBG oHY G oH^ J Cd(Hd L U K O I K M 80BBA A(F0 (C ABBJ 4lFOH c ABE ` DBJ <JBBB A(A0J (C BBBA St=TU=TU8(nFBA A(DP! (A ABBK   $. G$M%jp@%pH p'>I`b JP  89 RW\a&f k<peu>zOHmwp  #/AKX_jv o o C@   S= =&n4jmp_lit64__PRETTY_FUNCTION__.4624jmp_lit32__PRETTY_FUNCTION__.4618putPCintegerGuestRegOffset.part.0__PRETTY_FUNCTION__.4385accumulatorGuestRegOffset.part.0__PRETTY_FUNCTION__.4496putLO.part.0__PRETTY_FUNCTION__.4184__PRETTY_FUNCTION__.4628putHI.part.0dis_branch_likely.constprop.0dis_branch.constprop.0bstmt.7925__PRETTY_FUNCTION__.4705dis_branch_compact.constprop.0__PRETTY_FUNCTION__.4632__PRETTY_FUNCTION__.4640dis_instr_branch.isra.0.constprop.0disInstr_MIPS_WRK_00.isra.0.constprop.0__PRETTY_FUNCTION__.4715has_msa__PRETTY_FUNCTION__.7968__PRETTY_FUNCTION__.7932.LC0.LC1.LC2.LC3.LC4.LC5.LC8.LC6.LC7.LC9.LC10.LC11.LC12.LC13.LC14.LC17.LC18.LC20.LC19.LC15.LC16_GLOBAL_OFFSET_TABLE_IRConst_U64IRExpr_ConstIRStmt_PutirsbaddStmtToIRSBvex_assert_failIRConst_U32isPlausibleIRTypenewIRTempIRStmt_WrTmpmode64IRExpr_GetIRExpr_UnopIRExpr_RdTmpIRExpr_BinopIRStmt_ExittypeOfIRExpraccumulatorGuestRegOffsetgetAccgetDSPControlgetIRegputIRegvex_traceflagsIRConst_U8vex_printfmkNarrowTo32putLOputHIdisInstr_MIPSguest_code::B;O<V=s ?  ? !? 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#;_pr:03p h_generic_calc_Mul32x4h_generic_calc_Max32Sx4h_generic_calc_Min32Sx4h_generic_calc_Max32Ux4h_generic_calc_Min32Ux4h_generic_calc_Max16Ux8h_generic_calc_Min16Ux8h_generic_calc_Max8Sx16h_generic_calc_Min8Sx16h_generic_calc_CmpEQ64x2h_generic_calc_CmpGT64Sx2h_generic_calc_SarN64x2h_generic_calc_SarN8x16h_generic_calc_QNarrowBin32Sto16Ux8h_generic_calc_NarrowBin16to8x16h_generic_calc_NarrowBin32to16x8h_generic_calc_Perm32x4h_generic_calc_GetMSBs8x16 4@H\p@`p$8pL`0tp.symtab.strtab.shstrtab.text.data.bss.note.GNU-stack.note.gnu.property.rela.eh_frame@y!',< TO@` X   @^/1077 0 0 0 644 1296 ` ELF>P@@ BGBGB G BGBGBGBGGNUzRx cch_generic_calc_Perm32x8 .symtab.strtab.shstrtab.text.data.bss.note.GNU-stack.note.gnu.property.rela.eh_frame@c!',< T0O@  ^/1122 0 0 0 644 3792 ` ELF> @@ ffZZ Y\$t$%@ D$T$fZXD$\$D$ƒ= T$T$T$uL$fft  ЉD$fZD$f.ATUS \$L$fH~fI~H4fH~fӁfffA A Df`EWfH~H4f%f=@E1ҁ415f(f(f(YYf(f(Y\\Xf(XX\fD(fD(\D\E\\$L$ʁ@ʀT$T$f(A\YYYY\A\XXXXXfI~A\$D$ƒ= ȉD$T$EAtfInX/[]A\LH0f%f=tHD L!H IfI~fI~I0I0fAfAfAfAfH~H0Ač8fA=6fAII4fA RfAf94f5v%HKLH!H4H fHnA5AHAH!I4L fHnfAtfH~H0f%f=Y[]A\XAu*\$HT$L!D H IfHnXD$1AAu'LH0f%f=tHD L!H IfInXY-/XXf9H5L!H4H fHnAfA5HA5AH!I4L fHn@H5H%H4HLH!H fE;T$5fHnE1ff fT$\$0Af%D$f% fD$\$4f5Af%D$f% fD$\$fAf%D$f% fD$fEK5L\$E1HH4H!H fHnst4T$ff%fjfD$fD$YD$ YfHnE1\$ f9HKjLH!H4H fHnE1fAfEAAjAH%H!H4H fHnY\$E1T$Ajf%f fD$\$fInXY>Y A/YD$fH~H8xX\@CFAP9GNUzRx 80FAA  ABA D ABI   1.LC2.LC0.LC3.LC1.LC4h_generic_calc_MAddF32h_generic_calc_MAddF64C;L 4.symtab.strtab.shstrtab.rela.text.data.bss.rodata.cst8.note.GNU-stack.note.gnu.property.rela.eh_frame @Y@ &,1(>N fha@ 0 Ph   H p/1165 0 0 0 644 26424 ` ELF>xc@@HAWAAVAUATUSHhHD$ H (HD$(HylHD$0HE HD$8Hq&TsHD$@HY HD$HH) }$H|$HD$PHh[]A\A]A^A_ABHL$ D$ 1fHD9H u꺼}$ @HL$LH\$@Hk |;9|$(|@9T$~LH|$fwH 9L$0~SxuP9T$wH =H5H=H BH5H=Hc\$hLd$ HH;l$4 5H$HP9T$( 9T$0AMk Ll$A}AEHHIEH-|$49|$hub|$h9$u6HD$ H([]A\A]A^A_H H5H=H H5H=H H5H=H H5H=H H5H=H=D1H=AE%9D$ H|$fGHk HD$@H9L$(x A}HIHcH$EFPH$HDŽ$HDŽ$TAVH$H LOH$H?L62H vH5H=IN0l$hDŽ$E_8H A1҃1E1 D9T$0~DHA9ELEy[A|$uDA%9D$ H\$DCEyHk HD$@DPD9T$( D;T$XuuxDH H5H=tVAuPAC HD$`H\$HHLLHt$H|$`Ht$HHHHLAVPH4AVE_8HD$XLd$ HD$8$HHkPH$H$D;\$8HD$8Al%9D$HD$pHHD$DHD$xExsD9L$0~lIHk H\${u:IMcH$BTHD$8A|$tCHD$8E_8cH H5H=AhM$Ǎ@AKHc,HH"Lk HT$B|u B<H$9sӉ…I9jHD$xLcH$Ik H\$CkfCTHD$8A|$HkD$p HD$@xHIH$HDŽ$EFPH$HDŽ$BTAV H$Ht}LH$Hu^HD$8AD$tG{H ?H5H=H H5H=C8L_H$HuH 4H5H=H /H5H=Hk HD$HH 9%x@u@x1 HA9vA;|u@H H5H=H\$`Hl$HH$AVPHH4AVHH|$ H4zHc$HL$P$S9T$4*9T$4D9D$Xх%9D$0Hk HD$HxN@H HxH H5H=HD$`AIHILAMA݋@ $LEMIAD;l DH|$Hk H{tۃ{D$L$EML$$EFsLH$IPL$D$D$L$H$u 9$MED$EL$D9~EAI,MDMMAED9L$0McIk H\${LBDPh9$fCA9z%9D$H$Hk HD$@P9T$(x{DPD$H$H$BTEFPHDŽ$HDŽ$DAVH$D$H,LD$H$D$HtLD$D$HD$H$kfxHD$xCfDHD$8A|$HkD$p HD$@xHIH$HDŽ$EFPH$HDŽ$BTAV H$HtOLH$HtLHD$8AD$CIH$BTkH$HuH H5H=H H5H=H H5H=H ~H5H=H H5H=C*H {H5H=H=1$H=1H=H$HH H5H=H H5H=H vH5H=H uH5H=H xH5H=H H5H=$2H H5H=H H5H=H H5H=H H5H=D$4$H H5H=H H5H=AGA9GH H5H=H ]H5H=H H5H=H H5H=H bH5H=H$HH H5H=H ~H5H=H {H5H=priv/host_generic_reg_alloc2.crc >= HRcInt32 && rc <= HrcLAST0 == (con->guest_sizeB % LibVEX_GUEST_STATE_ALIGN)doRegisterAllocation: out-of-range vregvreg_lrs[k].reg_class == hregClass(vreg)doRegisterAllocation: first event for vreg is ReaddoRegisterAllocation: first event for vreg is ModifydoRegisterAllocation: first event for rreg is ReaddoRegisterAllocation: first event for rreg is Modify(rreg_live_after[j] == INVALID_INSTRNO && rreg_dead_before[j] == INVALID_INSTRNO) || (rreg_live_after[j] != INVALID_INSTRNO && rreg_dead_before[j] != INVALID_INSTRNO)rreg_lrs_la[j-1].live_after <= rreg_lrs_la[j].live_afterrreg_lrs_db[j-1].dead_before <= rreg_lrs_db[j].dead_beforevreg_lrs[j].reg_class == HRcINVALID0 == ((UShort)vreg->spill_offset % 16)0 == ((UShort)vreg->spill_offset % 8)rreg_state[hregIndex(reg)].disp == Unavailrreg_state[j].disp == Bound || rreg_state[j].disp == Free || rreg_state[j].disp == Unavailrreg_state[j].eq_spill_slot == FalsehregClass(con->univ->regs[j]) == hregClass(rreg_state[j].vreg)hregIsVirtual(rreg_state[j].vreg)hregIndex(rreg_state[k].vreg) == jhregClass(vregS) == hregClass(vregD)IS_VALID_VREGNO(hregIndex(vregD))IS_VALID_VREGNO(hregIndex(vregS))rreg_lrs_la_next <= rreg_lrs_usedii == rreg_lrs_la[rreg_lrs_la_next].live_aftervreg_lrs[m].reg_class != HRcINVALIDvreg_lrs[m].dead_before >= ii+1! sameHReg(reg_usage_arr[ii].vRegs[0], reg_usage_arr[ii].vRegs[1])vreg_lrs[p].reg_class != HRcINVALIDreg_usage_arr[ii].vMode[j] == HRmModifyreg_alloc: can't find a register in class: reg_alloc: can't create a free register.rreg_state[spillee].disp == BoundhregClass(con->univ->regs[spillee]) == hregClass(vreg)! sameHReg(rreg_state[spillee].vreg, vreg)rreg_lrs_db_next <= rreg_lrs_usedii+1 == rreg_lrs_db[rreg_lrs_db_next].dead_beforerreg_lrs_la_next == rreg_lrs_usedrreg_lrs_db_next == rreg_lrs_usedLibVEX_N_SPILL_BYTES is too low. Increase and recompile.size >= 0used == *sizepriv/host_generic_regs.hinstrs_in->arr_used <= 15000n_vregs < 32767n_rregs > 0hregIsVirtual(vreg) vreg %d, n_vregs %d OFFENDING VREG = %d doRegisterAllocation(1) OFFENDING RREG = OFFENDING instr = isR && isW!hregIsVirtual(rreg)ix < n_rregs!hregIsVirtual(reg)k < rreg_lrs_usedIS_VALID_VREGNO(k)vreg_state[k] == jIS_VALID_RREGNO(k)rreg_state[k].disp == BoundIS_VALID_VREGNO(m)IS_VALID_RREGNO(n)IS_VALID_VREGNO(vregno)spill1 || spill2rreg_state[n].disp == Boundn == INVALID_RREG_NOreload1 || reload2IS_VALID_RREGNO(spillee)vreg_lrs[m].dead_before > iirreg_lrs_db_next >= 0rreg_state[k].disp == UnavailhregClassfindMostDistantlyMentionedVRegsanity_check_spill_offsetsortRRLRarrayensureRRLRspace_SLOWdoRegisterAllocation_v2GNUzRx HLEB B(A0A8Du 8A0A(B BBBA hDQ K %%AA^L FBB B(A0A8G  8A0A(B BBBA P(=`V0%``%q 0  j @1N^%~+1x7X=CIO U[xag(ms@y>QpwdH,P  !h'?-3H9x?EK&QWr]`c8i\ou{8    !07BL[osortRRLRarray__PRETTY_FUNCTION__.3848ensureRRLRspace_SLOW__PRETTY_FUNCTION__.3825addHInstrhregClass.part.0__PRETTY_FUNCTION__.3585__PRETTY_FUNCTION__.3899__PRETTY_FUNCTION__.3815__PRETTY_FUNCTION__.3801.LC0.LC1.LC2.LC3.LC4.LC17.LC14.LC15.LC9.LC13.LC5.LC6.LC7.LC8.LC18.LC10.LC19.LC22.LC26.LC23.LC21.LC24.LC25.LC11.LC12.LC27.LC30.LC28.LC20.LC73.LC33.LC38.LC39.LC42.LC41.LC40.LC35.LC37.LC31.LC34.LC36.LC47.LC46.LC45.LC44.LC43.LC48.LC29.LC72.LC71.LC32.LC16.LC55.LC59.LC56.LC58.LC57.LC51.LC66.LC65.LC60.LC61.LC52.LC63.LC62.LC64.LC70.LC69.LC68.LC67.LC54.LC49.LC53.LC50_GLOBAL_OFFSET_TABLE_vex_assert_failprivate_LibVEX_alloc_currprivate_LibVEX_alloc_lastprivate_LibVEX_alloc_OOMaddHInstr_SLOWdoRegisterAllocation_v2newHInstrArrayvpanicvex_printfvex_bzeroaddToHRegRemapHRegUsage__containsppHRegClass L _`a` \ _ be qx_e`aY``T`w``fg f |' .3_C OV[_s | _ | _ | _ | _ |   _  g  g  g  g  f ` a `P  |\  c h _  |   _  |   ! _  |'  . "3 _:  |F  M #R _Y `^ be p g  g $ g % f  |  & _ ` a6h , '_ | (_g g'.gJQgX)]f*f |' .+3_ | ,_ | -_8 |D K.P_W |c j/o_v | 0_ | 1_ | 2 _ | $3)_0 |< C4H_O |[ b5g_n |z 6_ | 7_ | 8_ | 9_ | ,_  | :!_ | ;_ | 9_P` , <_ | =_ | >_ | ?_ | 3_%/g6@;f | 0_ | _i | &A+_i | B_ | C_ | D_ | E_g |s z_B |N U9Z_j i  |  D _  |  F _  |  G _! |! !9!_"! |.! 5!F:!_S! |_! f!Hk!_r!Iy!g!k!!g!J!f! |! !K!_! ! !/!_! |" "L "_" | " '"M,"_3" |?" F"NK"_R" |^" e"Bj"_}" |" "O"_" |" "0"_" |" "3"_" |" "P"_ # |# #Q!#_(# |4# ;#R@#_U# |a# h#Sm#_t# |# #T#_# |# #9#_# |# #U#_# |# #V#_$ | $ $K$_ $ |,$ 3$F8$_?$ |K$ R$9W$_Qc l0`.symtab.strtab.shstrtab.rela.text.data.bss.rodata.str1.8.rodata.str1.1.rodata.note.GNU-stack.note.gnu.property.rela.eh_frame @[$@># &$,$12$"@2,O`/W/g/ 0z@pbx 1 ^ 8;{b/1213 0 0 0 644 22232 ` ELF>S@@G ;G}HHcȃH4ʉG ff.PXH H5H=Hff.AWAVAUEhATUSH8E9HD$pH4$EF͉T$,H0DD$DL$HDD;,@DD$HHD$ HHHD$AD;,w:DH@H8uD`H<$Dt6HD$pAH0D;,vƃ|$D$H8[]A\A]A^A_fDt$D$A9HH\$ Ll$DL$(ADCIPA9tLDLtAH\$ D9t$ jD9t$Dd$pHD$pDt$ H0fDH\$ L$(9L$ /D$(Dd$D$ H=1|$,H=1H=D$D$(AUEATHUHSHHD$8\$0HJ Hc,DD9H @AE1AH (f;w}x)D9v AADHH A9k1AŅuHHDL2 Et?LL2A1fD9fE;A})uH H5H=AHD[]A\A]@HE[D]A\A]AUATULSHLd$HLL$PD9HH1{DS EAD9l$@I DDH'O9f9S{Ht$KHDH$EAPHD$AQH4$HAD$ A;D$I$HcȃH4AD$ Ht$HuFHC HSH%H@HDH@HD[]A\A]AD$ A;D$@I$HcȃH4AD$ H NH5H=fH H5H=H HH5H=H IH5H=H LH5H=H MH5H=H OH5H=Ht$HH VH5H=LcL]AWAVAUATUSHF8PDoIHEE1H@$H$H=H@H|$HHHHT$HHH9 HHHD$H9WIcG Ht$HHH5HHHD$(HH9 DHHHH9XH:HD$0EtiAULHHLDAE1Af8H fD@@@@fDH@@fDPH9u$H|$HL$~qHLrH HqL$:r9/zu%Hk H LH0@H HBfD$:$HHLDAA9ILY@@H$HH H5H=H5IH H5H=H H5H=HD$`1ɺ?HHH?)9$FT$uF9$Hk L?9xCH;Tz*9tH H5H=H H5H=H H5H=L1Ƀ:zH 9 $uHD$t$:1H HH 9$VHk A| u1;H  HHf;1f;q|H H5H=H H5H=H H5H=B%9D$ HLxu/@ %9H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=priv/host_generic_regs.h reserve_phaseIS_VALID_VREGNO((v_idx))IS_VALID_RREGNO(r_idx)n_rregs > 0instrs_in->arr_used <= 15000hregIsVirtual(vreg)vreg %u (n_vregs %u) Offending vreg = %u Offending instruction = 0 Offending rreg = isR && isWIS_VALID_VREGNO(vs_idx)IS_VALID_VREGNO(vd_idx)! sameHReg(vregS, vregD)IS_VALID_VREGNO(v_idx)rreg_lrs->lrs_used > 0IS_VALID_RREGNO(_r_free_idx)move != NULLhregIsInvalid(rreg)rc >= HRcInt32 && rc <= HrcLASTdoRegisterAllocation_v3: cannot find a register in class: doRegisterAllocation_v3: cannot find a register.priv/host_generic_reg_alloc3.cvreg_state[v_idx].disp == AssignedhregClass(con->univ->regs[r_idx]) == hregClass(vreg)vreg_state[v_idx].dead_before > (Short) current_iivreg_state[v_idx].reg_class != HRcINVALIDspill1 != NULL || spill2 != NULL(con->guest_sizeB % LibVEX_GUEST_STATE_ALIGN) == 0doRegisterAllocation_v3: out-of-range vregvreg_state[v_idx].reg_class == hregClass(vreg)doRegisterAllocation_v3: first event for vreg is "Read" (should be Write)doRegisterAllocation_v3: first event for vreg is "Modify" (should be Write)doRegisterAllocation_v3: first event for rreg is "Read" (should be Write)doRegisterAllocation_v3: first event for rreg is "Modify" (should be Write)hregClass(vregS) == hregClass(vregD)vreg_state[v_idx].reg_class == HRcINVALID(vreg_state[v_idx].spill_offset % 16) == 0(vreg_state[v_idx].spill_offset % 8) == 0!hregIsVirtual(vreg_state[v_idx].rreg)rreg_state[r_idx].disp == BoundhregIndex(rreg_state[r_idx].vreg) == v_idxhregClass(vreg_state[v_idx].rreg) == hregClass(con->univ->regs[r_idx])hregIsVirtual(rreg_state[r_idx].vreg)hregIndex(vreg_state[v_idx].rreg) == r_idxrreg_state[r_idx].eq_spill_slot == Falserreg_lrs->lr_current_idx < rreg_lrs->lrs_usedrreg_lrs->lr_current->live_after <= (Short) ii(Short) ii < rreg_lrs->lr_current->dead_beforehregIsInvalid(vreg_state[vs_idx].rreg)vreg_state[v_idx].dead_before >= (Short) (ii + 1)! sameHReg(reg_usage[ii].vRegs[0], reg_usage[ii].vRegs[1])reload1 != NULL || reload2 != NULLN_SPILL64S is too low in VEX. Increase and recompile.spill_vregfind_free_rreghregClassdoRegisterAllocation_v3GNUzRx %0%AA^HLBBB F(A0C8Dp 8A0A(B BBBC HBGE D(D0 (D ABBE D(D DBB8BBA D(D@! (D ABBI FBB B(A0A8G   H X A 9 D a O U " J G E R _ B \ B 8 D d O R  8A0A(B BBBA % 0% 5`O0j0 0 `)BP @"(.4Y:e@FL0RX^dj.pv|u`G8pP ^8  "1AU`lsaddHInstrhregClass.part.0__PRETTY_FUNCTION__.3585find_vreg_to_spill.isra.0find_free_rreg.constprop.0__PRETTY_FUNCTION__.3941spill_vreg__PRETTY_FUNCTION__.3892__PRETTY_FUNCTION__.3948.LC0.LC1.LC2.LC3.LC4.LC5.LC6.LC11.LC7.LC8.LC9.LC10.LC12.LC13.LC25.LC21.LC22.LC23.LC17.LC20.LC14.LC15.LC16.LC35.LC26.LC29.LC34.LC32.LC31.LC30.LC33.LC28.LC18.LC19.LC24.LC50.LC54.LC38.LC42.LC55.LC52.LC53.LC51.LC56.LC27.LC36.LC40.LC49.LC48.LC44.LC43.LC47.LC46.LC45.LC41.LC39.LC37_GLOBAL_OFFSET_TABLE_addHInstr_SLOWvex_assert_failHRegUsage__containsvex_printfppHRegClassvpanicdoRegisterAllocation_v3private_LibVEX_alloc_currprivate_LibVEX_alloc_lastnewHInstrArrayvex_bzeroprivate_LibVEX_alloc_OOMaddToHRegRemap5 A H QNOOPQPR N N   N N N# /6;NC OV[Nc ov{N NMMTCUxTTVuTUT W T U T'  ,3 : ? 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|H5H=HHcH>HHHHHHHHHHHHHHHHHPH=ff.HHPH;sHpxPff.HHL@L;sCLpxP HwHÐH H5H=ff.HtJHOLGHw HPH;sPHHp L@w@HHHOHPH;sHHHHDH H5H=H=DUSHH/t]w1H={H=1{ KH[H=1]f.wu1H=1{HH=1[]H=1H=ff.HJBtDA9g=@"DAAx ȃHG8 ΃΀@7RWBJ DD94@4J8΄@7Bqx+J DFAxrAA Ax 8 ȈGRHGWH=P=@lG$HG8D@7RWH H5H=@dHH=H .H5H=Jwu˅xHG ʃ8 ʈH==@ DAAVxBxuv ȃwM8 ȃ@RHGWf.H /H5H=H LH5H=H 1H5H=w8D@7BqCzbxuJ DFAI1xerw5AA AxuH 8 ȈGRHGWsH RH5H=H SH5H=HH=fDHHPH;sHxPHHPH;sHxPHHPH;sHHxPHttltPH=@Ptnt9H=DwH=HDHHxHHH=H41HxH=1HDwJH=1HfHH H5H=H |H5H=H H5H=H xH5H=@HHPH;sHxPHHPH;sHxPtNHXPt_t*H=fDw1H=xHHH=H41HxucH=1HHwSH=1HH H5H=H H5H=H |H5H=H xH5H=H=DHHPH;sHxPHHPH;sHHxPUSHH_+tYsH=1{H=1{ KH[H=1]fDst9H=1{HH=1[]H=1H=H=tuHHPH= HHcH>HHHHHHHHHHPH=ff.t7ttPH=HHH;HHcH>HHHHHHHHHHHHHHHHHHHPH=ff.DKHHcH>HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHPH=ff.HHH H; sH xHpPPf.HHHH H; sCH xHpHP tHfH GH5H=ff.HHH H; sH xp PPff.HHP H;sHxHpPff.fHHP H;sHxp Pff.HHP H;sHHxpPff.fHHP H;sH@xHpPff.HHP H;sH@xHpPff.HHL@ L;sKxLp PHw HfDH |H5H=@HHP H;sHHx PHHL@ L;Lx p PHHwYHH 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.CوCfC}迍PACوCfDk}蔍ƒ$@HH{HEUplAffD#Le} eSH=AfD Le9U H{艏HUHMHH@I HEH{Up-H H5H=H H5H=H H5H=H H5H=AfDH - H5H=H H5H=H N H5H=H H5H=H H5H=H H5H=H{fHEuPȌsCHUH{]XCHUH{B=H H5H=H{9t)H-C HS 1C HS $URHMHH@I kuy0LA0LAe Lu A IH H5H=H=H H5H=H ;H5H=H=H=H=H=ff.fDAUATUSH>ILnHHL9A|$A|$HA$LL)HYH H fAD$HHL[]A\A]H  H5H=fH % H5H=H & H5H=H ( H5H=H ) H5H=H < H5H=ATH >It"H ^ H5H=~u؀~ uH~HL$HT$H|$HT$H|$HHL$IDH9uA$fAD$H LA\H I H5H=fPXH Huw H5H=v H5H=priv/host_x86_defs.c1 <= i && i <= 70 <= i && i <= 6priv/host_generic_regs.hhregClass(r) == HRcFlt64!hregIsVirtual(r)n <= 5hregClass(r) == HRcInt32n <= 7(reg|regmem) < 8gregEnc < 8mapRegs_X86AModemapRegs_X86RMaddRegUsage_X86AModeaddRegUsage_X86RMr >= 0 && r < 8%sr >= 0 && r < 6%%fake%d%%xmm%dppHRegX86ALWAYSobnbznzbenbesnspnplnllenlenoppX86CondCodeshift >= 0 && shift <= 3dopyX86AMode(0x%x(),,%d)ppX86AModeshift < 4(regindex|regbase) < 8doAMode_M: unknown amode$0x%xppX86RMIppX86RIppX86RMnegnotshowX86UnaryOpmulmovaddsubadcsbbandorxorcmpshowX86AluOpshrsarshlshowX86ShiftOp2xm1divscaleatanyl2xyl2xp1premprem1sqrtabschssincostanroundshowX86FpOppunpcklqmov(?!)maxmincmpFeqcmpFltcmpFlecmpFunrcprsqrtandnpaddbpaddwpadddpaddqpaddusbpadduswpaddsbpaddswpsubbpsubwpsubdpsubqpsubusbpsubuswpsubsbpsubswpmullwpmulhuwpmulhwpavgbpavgwpmaxwpmaxubpminwpminubpcmpeqbpcmpeqwpcmpeqdpcmpgtbpcmpgtwpcmpgtdpsllwpslldpsllqpsrlwpsrldpsrlqpsrawpsradpackssdwpacksswbpackuswbpunpckhbpunpckhwpunpckhdpunpckhqpunpcklbpunpcklwpunpckldshowX86SseOpop != Xalu_MULis_sane_RetLoc(rloc)cond != Xcc_ALWAYSszSmall == 1 || szSmall == 2sz == 1 || sz == 2sz == 4 || sz == 2 || sz == 1sz == 2 || sz == 4 || sz == 8hregClass(dst) == HRcVec128sz == 4 || sz == 8op != Xsse_MOVorder >= 0 && order <= 0xFFfastslowllwdmode64 == False%sl %%cl,$%d,testl $%d,leal %cmull %cdivl %sdl %%cl, $%d,pushl call%s[%d,] 0x%x(xDirect) if (%%eflags.%s) { movl $0x%x,; (xIndir) if (%%eflags.%s) { movl (xAssisted) movl cmov%s mov%c%cl mov%c setl%s bs%cl mfence(%s)lock cmpxchg%c {%%eax->%%ebx},g%sD gld%c , gst%c gild%s gist%s gdtof gcmov%s fldcw fstsw %%axgcmp const $0x%04x,movups movs%s %sps %sss %spd %ssd %s pshufd $0x%x,(evCheck) decl ; jns nofail; jmp *; nofail:ppX86InstraddRegUsage_X86RMIaddRegUsage_X86RIgetRegUsage_X86InstrmapRegs_X86RMImapRegs_X86RImapRegs_X86InstroffsetB >= 0!hregIsVirtual(rreg)nbuf >= 32 emit_X86Instr:call:regparmsdelta > 0 && delta < 40disp_cp_xindir != NULLemit_X86Instr:mfence:hwcaps! hregIsInvalid(swap)do_fop1_st: unknown opdo_fop2_st: unknown opemitX86Instr(FpLdSt,load)emitX86Instr(FpLdSt,store)0hregClass(r) == HRcVec128(gregEnc|eregEnc) < 8p - p0 == 3p - p0 == 5p - p0 == 8!(*is_profInc)emit_X86Instrp - &buf[0] <= 32endness_host == VexEndnessLEp[0] == 0xBAp[5] == 0xFFp[6] == 0xD2delta == 0LL || delta == -1LLvalidsizeof(ULong*) == 4%eax%ecx%edx%ebx%esp%ebp%esi%edirc >= HRcInt32 && rc <= HrcLASTdoAMode_M: can't emit amode IRRSdoAMode_M: can't emit amode IRop == Xsh_SHL || op == Xsh_SHRregparms >= 0 && regparms <= 30 == (hwcaps & ~(VEX_HWCAPS_X86_MMXEXT |VEX_HWCAPS_X86_SSE1 |VEX_HWCAPS_X86_SSE2 |VEX_HWCAPS_X86_SSE3 |VEX_HWCAPS_X86_LZCNT))sz == 4 || sz == 8 || sz == 10movl $disp_cp_chain_me_to_%sEP,%%edx; call *%%edx }; movl $disp_indir,%%edx; jmp *%%edx }; movl $IRJumpKind_to_TRCVAL(%d),%%ebp; movl $disp_assisted,%%edx; jmp *%%edx }lock cmpxchg8b {%%edx:%%eax->%%ecx:%%ebx},(profInc) addl $1,NotKnownYet; adcl $0,NotKnownYet+4getRegUsage_X86Instr:Call:regparmsi->Xin.Sse32Fx4.op != Xsse_MOVi->Xin.Sse32FLo.op != Xsse_MOVi->Xin.Sse64Fx2.op != Xsse_MOVi->Xin.Sse64FLo.op != Xsse_MOVgenSpill_X86: unimplemented regclassgenReload_X86: unimplemented regclassgenMove_X86: unimplemented regclassspill_off >= 0 && spill_off < 10000! sameHReg(i->Xin.Alu32R.dst, vreg)! sameHReg(i->Xin.CMov32.dst, vreg)i->Xin.Sh3232.op == Xsh_SHL || i->Xin.Sh3232.op == Xsh_SHRdisp_cp_chain_me_to_slowEP != NULLdisp_cp_chain_me_to_fastEP != NULLemit_X86Instr.Xin_XAssisted: unexpected jump kindi->Xin.CMov32.cond != Xcc_ALWAYSemitX86Instr(FpBinary,PREM/PREM1/SCALE)emitX86Instr(Xin_FpLdStI-load)emitX86Instr(Xin_FpLdStI-store)i->Xin.SseLdzLO.sz == 4 || i->Xin.SseLdzLO.sz == 8read_misaligned_UInt_LE(&p[1]) == (UInt)(Addr)disp_cp_chain_me_EXPECTED9)=-% 59)! 1;+# 3patchProfInc_X86unchainXDirect_X86chainXDirect_X86doAMode_R_enc_encvregEncpush_word_from_tagsfregEncdo_fld_stdo_fstp_stmkSIBiregEncmkModRegRMdoAMode_R_enc_regemit_X86InstrdirectReload_X86genReload_X86genSpill_X86mapRegs_X86InstrgetRegUsage_X86InstrppX86InstrX86Instr_SseShufX86Instr_SseCMovX86Instr_Sse64FLoX86Instr_Sse64Fx2X86Instr_Sse32FLoX86Instr_Sse32Fx4X86Instr_SseLdzLOX86Instr_SseConstX86Instr_FpCMovX86Instr_FpLdStIX86Instr_FpLdStX86Instr_ACASX86Instr_MFenceX86Instr_StoreX86Instr_LoadEXX86Instr_CMov32X86Instr_CallX86Instr_Sh3232X86Instr_Alu32MX86AMode_IRRShregClassppHRegX86GNUzRx %AA^8%AA^TFh B pFh B Fy A /D] G (yAG ~ AI O AA ,GD q AK GCX  t\W$<ORY E ^ J ^Rd5)|2mdHv B HL D m A 4EAG G AJQ a JAL jD H $/j8/jL0k8`Hn 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;WH7HcʃHΉW DHI|$(W ;Wf.Iv>0LHID$A;\$s)I|$(W ;W-VfDH H5H=H1H=1A|$ I~1A;|$$HDI|$(HTfDIvLdA~P1@HƒI|$(H~TfIvLIvLI1L@ljƃI|$(H/T=f.IvLID$A;\$4I|$(HSH1H=1HsLtL1I|$(HSIvLA~PHHH¿I|$(HVSd~L{HID$A;\$D,u GDI|$(HR fIvL$IvLI5HL]f.HID$A;\$`IvLD, +HsL,LI|$(H`RnH H5H=fHsLCIvLLIvIDH1H=1OIvLIvLIXL¾IvLYA~P1HI|$(HQH1H=1INHt$8H|$4LqA;\$ID$H8IT$|$40,RI|$(HQ|$8RI|$(HPHHD$HD$LH{HDI|$(HPIvL+A~PALIVLDINLHt$8H|$4pIvL1Ɖ|$8ILHI|$(HPIŋ|$4A~PHIIŋt AEINHt$8LH|$4@p|$8LHI|$(HOH1H=1!HHD$(HD$(8HHD$(HD$(H1H=1H1H=1HHD$(HD$( H1H=1H1H=1H1H=1sH H5H=H H5H=HHD$HD$HHD$(HD$(H1H=1kHHD$HD$HHD$HD$sHHD$HD$HHD$HD$HHD$HD$jHHD$HD$H H5H=H H5H=HHD$HD$IvDHI|$(HMH=ff.AWAVAUATUSHD:D$XDl$PD$ AzHHC8H;C0IDEHMH5HC(L Ic@ LCHHHH L9HH HsL9HHD$`HKDk D{C$MDR11A< w8wlH=uAѿAD HH袡P{TPDDHƺH{(HŋG ;GHHcȃH,ʉG HC(S0PH[]A\A]A^A_DH=1HH=1DH=1H nH5H=fH1H=1[LuA>PD{ IA~1;{$HDH=1HH=1DH=1H{(HŋG ;G'HHcȃH,ʉG H1H=1HH衟Pu~y[PD{ Ht;H1H=1HH NH5H=H MH5H=H H5H=HHH !H5H=HHL advance4(x86,host)priv/host_generic_regs.hix <= 0xFFFFFenc == 0 priv/host_x86_isel.chregClass(src) == HRcVec128hregClass(dst) == HRcVec128hregClass(src) == HRcInt32hregClass(dst) == HRcInt32ety == Ity_V128tmp < env->n_vregmapiselVecExpr_wrkhregClass(r) == HRcVec128hregIsVirtual(r)e->Iex.Load.ty == Ity_I64iselInt64ExprhregClass(*rHi) == HRcInt32hregIsVirtual(*rHi)hregClass(*rLo) == HRcInt32hregIsVirtual(*rLo)ty == Ity_F64iselDblExpr(x86): conste->Iex.Load.ty == Ity_F64iselDblExpr_wrkhregClass(r) == HRcFlt64ty == Ity_F32e->Iex.Load.ty == Ity_F32iselFltExpr_wrkty == e->Iex.CCall.rettyhregClass(r) == HRcInt32ty == Ity_I32sane_AMode(am)sane_AMode(rm->Xrm.Mem.am)sane_AMode(rmi->Xrmi.Mem.am)nGSPTRs == 0 || nGSPTRs == 1retTy != Ity_V256nVECRETs == 00argreg >= 0argregX >= 0!hregIsInvalid(r_vecRetAddr)not_done_yet == 0*stackAdjustAfterCall == 0is_RetLoc_INVALID(*retloc)sizeof(void*) == 4iselCondCode(x86): CmpXX16iselCondCode(x86): CmpXX32iselCondCode(x86): CmpXX64iselCondCode -- cas->expdHi == NULLcas->dataHi == NULLiselStmtarch_host == VexArchX86iselBB: IRTemp type -- PUT(%d) = ; exit-cdst->tag == Ico_U32rc >= HRcInt32 && rc <= HrcLASTn > 0 && n < 256 && (n%4) == 0sane_AMode: unknown x86 amode tage->Iex.Const.con->tag == Ico_V128vexGetAllocMode() == VexAllocModeTEMPiselVecExpr (hwcaps = %s): can't reduce typeOfIRExpr(env->type_env,e) == Ity_I64e->Iex.Const.con->tag == Ico_U64! hregIsInvalid(env->vregmapHI[tmp])e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U64cee->regparms >= 0 && cee->regparms <= 3ty == Ity_I32 || ty == Ity_I16 || ty == Ity_I8e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U8e->Iex.Unop.arg->Iex.Get.ty == Ity_I8e->Iex.Unop.arg->Iex.Get.ty == Ity_I16iselIntExpr_R: cannot reduce treeiselIntExpr_RMI.Iex_Const(x86h)hregClass(ri->Xri.Reg.reg) == HRcInt32hregIsVirtual(ri->Xri.Reg.reg)iselIntExpr_RI: unknown x86 RI taghregClass(rm->Xrm.Reg.reg) == HRcInt32hregIsVirtual(rm->Xrm.Reg.reg)iselIntExpr_RM: unknown x86 RM taggenGuestArrayOffset(x86 host)(1)genGuestArrayOffset(x86 host)(2)hregClass(rmi->Xrmi.Reg.reg) == HRcInt32hregIsVirtual(rmi->Xrmi.Reg.reg)iselIntExpr_RMI: unknown x86 RMI tagretTy == Ity_V128 || retTy == Ity_V256retTy != Ity_V128 && retTy != Ity_V256pushArg(x86): can't handle arg of this typetypeOfIRExpr(env->type_env, arg) == Ity_I32typeOfIRExpr(env->type_env,e) == Ity_I1e->Iex.Const.con->tag == Ico_U1e->Iex.Const.con->Ico.U1 == True || e->Iex.Const.con->Ico.U1 == FalseiselCondCode(x86): CmpXX8(expr,0:I8)iselCondCode(x86): CmpXX8(expr,expr)cal->Iex.CCall.retty == Ity_I32con->Iex.Const.con->tag == Ico_U32iselStmt(x86): Ist_Exit: dst is not a 32-bit value0 == (hwcaps_host & ~(VEX_HWCAPS_X86_MMXEXT | VEX_HWCAPS_X86_SSE1 | VEX_HWCAPS_X86_SSE2 | VEX_HWCAPS_X86_SSE3 | VEX_HWCAPS_X86_LZCNT))archinfo_host->endness == VexEndnessLEiselNextiselIntExpr_R_wrkiselIntExpr_RiselCondCode_wrkmk_iMOVsd_RRlookupIRTempiselIntExpr_AMode_wrkiselIntExpr_AModeadd_to_esplookupIRTemp64callHelperAndClearArgspushArgdoHelperCallmk_vMOVsd_RRiselVecExpr_wrkiselVecExpriselFltExpr_wrkiselFltExpriselDblExpr_wrkiselDblExpriselIntExpr_RM_wrkiselIntExpr_RMiselInt64Expr_wrkiselInt64ExpriselIntExpr_RMI_wrkiselIntExpr_RMIhregClassiselIntExpr_RI_wrkiselIntExpr_RIiselStmtmkHRegiselSB_X86GNUzRx )DX A 8oD\ P TWAe J T L xFp J Dz R ;\;\;\L}BBA C(K0 (D ABBG | (D ABBC (<AI @ AE N JH 4hADD U AAH FJA0'BBI I0  IBBL (BFI0w IBM Dm G j F H "BEE B(A0A8D 8A0A(B BBBH Xl2&BBB B(A0A8D 8A0A(B BBBC E CH H BBB B(D0D8D` 8A0A(B BBBA LBBD D(D@  (A ABBA  (C ABBJ dDb J TBBB B(D0D8D CS ~ 8A0A(B BBBH Db J <BBB B(D0 (B BBBA (4BDG  ABJ (`BDG  DBC HBBB E(D0D8G@ 8G0F(B BBBK 8wBBB A(G@ (I BBBF (BDG  DBC 0@ BBB E(A0A8GdtBBB B(A0DU 0A(B BBBE  0D(B EBBH ; GN X"BBE B(D0A8D# 8A0A(B BBBG   DJ H8FBB B(A0A8DP 8A0A(B BBBA ) 0o*W:Gp `p y P;;;}  '2 ="I8^rp  !2&Pr  ,y@@V`G bwq|w(` ( 0X0S 9 RXdp}-v<Un`@X@0(/ D]"f\q  ` ,:CEZv @ $*h06C<BQHmNTZ`f@l)rhx~B(R0Xk`8P (&,2{8>DJPVx\bNh`ntz$1(Pp(4  PU=i x   .;BRalw  " 3 F O a q            $ E T b          ) 9 C S j      ( 8 Q i        $ = U o      0H_y:Z~ #;Sk':Jds%0Jds|advance4mkHReg__PRETTY_FUNCTION__.3595addInstr.isra.0mk_vMOVsd_RR__PRETTY_FUNCTION__.3601__PRETTY_FUNCTION__.5032mk_iMOVsd_RR__PRETTY_FUNCTION__.5027newVRegF.isra.0newVRegV.isra.0newVRegI.isra.0do_sse_Not128sub_from_espadd_to_esp__PRETTY_FUNCTION__.5037roundToF64set_FPU_rounding_defaultsane_AModeiselVecExprp_zwiden_load64.5907iselIntExpr_AMode__PRETTY_FUNCTION__.5901__PRETTY_FUNCTION__.5891iselIntExpr_RMIiselInt64ExpriselIntExpr_R__PRETTY_FUNCTION__.4935iselCondCode_wrkdoHelperCall.isra.0.part.0__PRETTY_FUNCTION__.5557genGuestArrayOffsetp_CmpwNEZ64_Or64.5754iselDblExpriselIntExpr_RMset_FPU_rounding_mode__PRETTY_FUNCTION__.5548__PRETTY_FUNCTION__.5097__PRETTY_FUNCTION__.4942__PRETTY_FUNCTION__.5819__PRETTY_FUNCTION__.5813iselFltExpriselFltExpr_wrk__PRETTY_FUNCTION__.5797__PRETTY_FUNCTION__.5791iselIntExpr_R_wrk__PRETTY_FUNCTION__.5178p_LDle8_then_8Sto32.5271p_LDle16_then_16Uto32.5274p_32to1_then_1Uto8.5264p_LDle8_then_8Uto32.5268__PRETTY_FUNCTION__.5171__PRETTY_FUNCTION__.5381__PRETTY_FUNCTION__.5387iselIntExpr_RI__PRETTY_FUNCTION__.5428__PRETTY_FUNCTION__.5435__PRETTY_FUNCTION__.5449__PRETTY_FUNCTION__.5457__PRETTY_FUNCTION__.5404__PRETTY_FUNCTION__.5412__PRETTY_FUNCTION__.5056__PRETTY_FUNCTION__.5067p_CmpNEZ32_And32.5474p_CmpNEZ32_Or32.5478p_CmpNEZ64_Or64.5485__PRETTY_FUNCTION__.5468iselStmtCSWTCH.282__PRETTY_FUNCTION__.6209__PRETTY_FUNCTION__.6333__PRETTY_FUNCTION__.6283.LC0.LC1.LC2.LC3.LC4.LC5.LC6.LC7.LC8.LC9.LC10.LC11.LC12.LC18.LC19.LC13.LC14.LC20.LC21.LC15.LC16.LC17.LC28.LC22.LC29.LC30.LC31.LC32.LC23.LC27.LC24.LC25.LC26.LC36.LC33.LC37.LC35.LC34.LC40.LC38.LC39.LC41.LC46.LC45.LC43.LC42.LC44.LC47.LC49.LC48.LC52.LC50.LC51.LC53.LC55.LC56.LC54.LC57.LC59.LC58.LC63.LC61.LC60.LC62.LC77.LC69.LC64.LC67.LC68.LC78.LC65.LC66.LC75.LC76.LC71.LC72.LC73.LC70.LC74.LC89.LC79.LC83.LC84.LC87.LC88.LC80.LC81.LC82.LC86.LC85.LC90.LC94.LC91.LC92.LC93.LC98.LC95.LC96.LC97.LC99.LC100.LC101_GLOBAL_OFFSET_TABLE_dopyX86AModevpanicvex_assert_failvex_traceflagsppX86Instrvex_printfaddHInstr_SLOWX86Instr_SseReRgX86RMI_RegX86Instr_Alu32RX86Instr_Sse32Fx4X86RMI_ImmX86AMode_IRX86Instr_FpLdStX86Instr_PushX86Instr_FpLdCWtypeOfIRExprmatchIRExprX86Instr_SseLdStLibVEX_ppVexHwCapsppIRExprX86Instr_SseConstvexGetAllocModevexSetAllocModeIRExpr_BinderIRExpr_LoadIRExpr_UnopX86Instr_SseLdzLOX86Instr_SseShufX86RMI_MemX86Instr_Unary32X86RI_RegX86Instr_Alu32MX86Instr_Sse32FLoX86Instr_Sse64FLoh_generic_calc_NarrowBin32to16x8X86Instr_Lea32X86Instr_Callh_generic_calc_NarrowBin16to8x16X86Instr_Sse64Fx2X86Instr_SseCMovh_generic_calc_CmpNEZ8x8X86Instr_Sh32h_generic_calc_CmpNEZ32x2X86Instr_MulLX86Instr_Divh_generic_calc_Add8x8X86Instr_FpLdStIX86Instr_Sh3232X86RM_RegX86Instr_CMov32h_generic_calc_Perm8x8h_generic_calc_CatEvenLanes16x4h_generic_calc_CatOddLanes16x4h_generic_calc_InterleaveLO32x2h_generic_calc_InterleaveLO16x4h_generic_calc_InterleaveLO8x8h_generic_calc_InterleaveHI32x2X86Instr_Test32h_generic_calc_QAdd16Ux4h_generic_calc_QAdd8Ux8h_generic_calc_Add32x2h_generic_calc_Add16x4h_generic_calc_QSub8Sx8h_generic_calc_QSub16Ux4h_generic_calc_QSub8Ux8h_generic_calc_Sub32x2h_generic_calc_Sub16x4h_generic_calc_Sub8x8h_generic_calc_QAdd16Sx4h_generic_calc_QAdd8Sx8h_generic_calc_CmpGT16Sx4h_generic_calc_CmpGT8Sx8h_generic_calc_CmpEQ32x2h_generic_calc_CmpEQ16x4h_generic_calc_CmpEQ8x8h_generic_calc_Min8Ux8h_generic_calc_Min16Sx4h_generic_calc_Max8Ux8h_generic_calc_Max16Sx4h_generic_calc_Avg16Ux4h_generic_calc_Avg8Ux8h_generic_calc_MulHi16Sx4h_generic_calc_MulHi16Ux4h_generic_calc_Mul32x2h_generic_calc_Mul16x4h_generic_calc_QSub16Sx4h_generic_calc_InterleaveHI16x4h_generic_calc_InterleaveHI8x8h_generic_calc_NarrowBin32to16x4h_generic_calc_NarrowBin16to8x8h_generic_calc_QNarrowBin32Sto16Sx4h_generic_calc_QNarrowBin16Sto8Sx8h_generic_calc_QNarrowBin16Sto8Ux8h_generic_calc_SarN32x2h_generic_calc_SarN16x4h_generic_calc_SarN8x8h_generic_calc_ShrN32x2h_generic_calc_ShrN16x4h_generic_calc_ShlN32x2h_generic_calc_ShlN16x4h_generic_calc_ShlN8x8h_generic_calc_CmpGT32Sx2X86Instr_Set32h_generic_calc_CmpNEZ16x4IRExpr_BinopX86Instr_FpBinaryX86Instr_FpUnaryX86Instr_FpCMovX86Instr_Fp64to32X86Instr_LoadEXX86Instr_FpStSW_AXX86Instr_Bsfr32h_generic_calc_GetMSBs8x8X86Instr_FpCmpX86AMode_IRRSX86RI_ImmX86RM_MemsizeofIRTypeppIRStmttypeOfIRTempX86Instr_DACASX86Instr_MFenceIRExpr_ConstX86Instr_XAssistedX86Instr_ACASX86Instr_XDirectX86Instr_StoreiselSB_X86private_LibVEX_alloc_currprivate_LibVEX_alloc_lastnewHInstrArrayppIRTypeX86Instr_EvCheckppIRJumpKindX86Instr_ProfIncX86Instr_XIndirprivate_LibVEX_alloc_OOM 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160addRegUsage_AMD64RMImapRegs_AMD64AModemapRegs_AMD64RMIALWAYSobnbznzbenbesnspnplnllenlenoppAMD64CondCodeshift >= 0 && shift <= 3(0x%x(),,%d)ppAMD64AModeshift < 4doAMode_M: unknown amode$0x%xppAMD64RMIppAMD64RIppAMD64RMnegnotshowAMD64UnaryOpimulmovaddsubadcsbbandorxorcmpshowAMD64AluOpshrsarshlshowAMD64ShiftOp2xm1scaleyl2xyl2xp1premprem1sqrtsincostanroundatanshowA87FpOpvcvtph2ps.movupsmuldivmaxmincmpFeqcmpFltcmpFlecmpFunrcprsqrtcvtdq2ps.cvtps2dq.andnpaddbpaddwpadddpaddqpaddusbpadduswpaddsbpaddswpsubbpsubwpsubdpsubqpsubusbpsubuswpsubsbpsubswpmullwpmulhuwpmulhwpavgbpavgwpmaxwpmaxubpminwpminubpcmpeqbpcmpeqwpcmpeqdpcmpgtbpcmpgtwpcmpgtdpsllwpslldpsllqpslldqpsrlwpsrldpsrlqpsrldqpsrawpsradpackssdwpacksswbpackuswbpunpckhbpunpckhwpunpckhdpunpckhqpunpcklbpunpcklwpunpckldpunpcklqpshufbpmaddubswvcvtps2ph(rm_field=$0x4).showAMD64SseOpop != Aalu_MULsz == 4 || sz == 8is_sane_RetLoc(rloc)cond != Acc_ALWAYSsz == 1 || sz == 2 || sz == 4sz == 8 || sz == 4nregs >= 1 && nregs <= 7szB == 8 || szB == 4szS == 4 || szS == 8szD == 4 || szD == 8op != Asse_MOVorder >= 0 && order <= 0xFFhregClass(gpr) == HRcInt64hregClass(xmm) == HRcVec128qwfastslowfld%c fstp%c cvtsd2ss cvtss2sd mode64 == Truemovabsq $0x%llx,%sq %%cl,$%d,testq $%d,leaq %sl %cmulq showAMD64ScalarSz%cdiv%s pushq call%s[%d,] 0x%llx(xDirect) if (%%rflags.%s) { movabsq $0x%llx,%%r11; movq %%r11,; (xIndir) movq (xAssisted) cmov%s mov%c , }mov%clq movl mov%c%cq setq%s bs%cq mfencelock cmpxchg%c {%%rax->%%rbx},ffree %%st(7..%d)f%sfldcw fstsw ldmxcsr ucomis%s ; pushfq ; popq cvtsi2s%s cvts%s2si movss movsd movups movs%s %sps %sss %spd %ssd %s pshufd $0x%x,%s $%u, (evCheck) decl ; jns nofail; jmp *; nofail:ppAMD64InstraddRegUsage_AMD64RIi->Ain.Alu32R.op != Aalu_MOVaddRegUsage_AMD64RMgetRegUsage_AMD64InstrmapRegs_AMD64RImapRegs_AMD64RMmapRegs_AMD64InstroffsetB >= 0!hregIsVirtual(rreg)nbuf >= 64delta >= 0 && delta < 100delta > 0 && delta < 40disp_cp_xindir != NULLreg < 16n >= 0 && n <= 7p - p0 == 3p - p0 == 5p - p0 == 8!(*is_profInc)emit_AMD64Instrp - &buf[0] <= 64endness_host == VexEndnessLEp[0] == 0x49p[1] == 0xBBp[10] == 0x41p[11] == 0xFFp[12] == 0xD3validp[2] == 0x00p[3] == 0x00p[4] == 0x00p[5] == 0x00p[6] == 0x00p[7] == 0x00p[8] == 0x00p[9] == 0x00p[10] == 0x49p[12] == 0x03%eax%ecx%edx%ebx%esp%ebp%esi%edi%r8d%r9d%r10d%r11d%r12d%r13d%r14d%r15d%rax%rcx%rdx%rbx%rsp%rbp%rsi%rdi%r8%r9%r10%r11%r12%r13%r14%r15rc >= HRcInt32 && rc <= HrcLASTppHRegAMD64_lo32: invalid regclassdoAMode_M: can't emit amode IRdoAMode_M: can't emit amode IRRSregparms >= 0 && regparms <= 6cond != Acc_ALWAYS && (szB == 4 || szB == 8)szSmall == 1 || szSmall == 2 || szSmall == 4sz == 8 || sz == 4 || sz == 2 || sz == 1sz == 4 || sz == 8 || sz == 16movabsq $disp_cp_chain_me_to_%sEP,%%r11; call *%%r11 }; movabsq $disp_indir,%%r11; jmp *%%r11 }; movl $IRJumpKind_to_TRCVAL(%d),%%rbp; movabsq $disp_assisted,%%r11; jmp *%%r11 }lock cmpxchg%db {%%rdx:%%rax->%%rcx:%%rbx},(profInc) movabsq $NotKnownYet, %%r11; incq (%%r11)getRegUsage_AMD64Instr:Call:regparmsi->Ain.Sse32Fx4.op != Asse_MOVi->Ain.Sse32FLo.op != Asse_MOVi->Ain.Sse64Fx2.op != Asse_MOVi->Ain.Sse64FLo.op != Asse_MOVgenSpill_AMD64: unimplemented regclassgenReload_AMD64: unimplemented regclassgenMove_AMD64: unimplemented regclassspill_off >= 0 && spill_off < 10000! sameHReg(i->Ain.Alu64R.dst, vreg)disp_cp_chain_me_to_slowEP != NULLdisp_cp_chain_me_to_fastEP != NULLemit_AMD64Instr.Ain_XAssisted: unexpected jump kindi->Ain.CMov64.cond != Acc_ALWAYSi->Ain.CLoad.cond != Acc_ALWAYSi->Ain.CLoad.szB == 4 || i->Ain.CLoad.szB == 8i->Ain.CStore.cond != Acc_ALWAYSi->Ain.CStore.szB == 4 || i->Ain.CStore.szB == 8i->Ain.A87Free.nregs > 0 && i->Ain.A87Free.nregs <= 7i->Ain.A87PushPop.szB == 8 || i->Ain.A87PushPop.szB == 4(gregEnc3210|eregEnc3210) < 16i->Ain.SseCStore.cond != Acc_ALWAYSi->Ain.SseCLoad.cond != Acc_ALWAYSi->Ain.SseLdzLO.sz == 4 || i->Ain.SseLdzLO.sz == 8read_misaligned_ULong_LE(&p[2]) == (Addr)disp_cp_chain_me_EXPECTED9)! 1;+# 3patchProfInc_AMD64unchainXDirect_AMD64chainXDirect_AMD64doAMode_M_encrexAMode_M_encdoAMode_R_enc_encvregEnc3210iregEnc3210rexAMode_R_enc_encdoAMode_R_enc_regiregEnc210iregEnc3mkSIBrexAMode_M__wrkdo_ffree_stemit_AMD64InstrdirectReload_AMD64genReload_AMD64genSpill_AMD64mapRegs_AMD64InstrgetRegUsage_AMD64InstrppAMD64InstrAMD64Instr_SseMOVQAMD64Instr_SseShufAMD64Instr_SseCMovAMD64Instr_Sse64FLoAMD64Instr_Sse64Fx2AMD64Instr_Sse32FLoAMD64Instr_Sse32Fx4AMD64Instr_SseLdzLOAMD64Instr_SseCLoadAMD64Instr_SseCStoreAMD64Instr_SseLdStAMD64Instr_SseSF2SIAMD64Instr_SseSI2SFAMD64Instr_SseUComISAMD64Instr_A87PushPopAMD64Instr_A87FreeAMD64Instr_DACASAMD64Instr_ACASAMD64Instr_StoreAMD64Instr_LoadEXAMD64Instr_CStoreAMD64Instr_CLoadAMD64Instr_CMov64AMD64Instr_CallAMD64Instr_DivAMD64Instr_Alu32RAMD64Instr_Alu64MppHRegAMD64_lo32AMD64AMode_IRRShregClassppHRegAMD64GNUzRx 4WADG \ DCI G FAE TFh B pFh B Ff D Fg K Ex S X H Ns O gQFW S $Ff D @DG E \~D S n R <HD \P D AC l AK G CE (}AG S AD O AA \5) 2m4dHv B 4PEAG G AJQ a JAL #D+ A /j/j0kIUSIUS/j$/j$87NM]g I D L `/jt0k<OAD T AJM aJAT -aHTL $<3nP6qddHu C 5p2m2m3nqH| D 4olHx H 0k 0HP H p H T:uh6q|9tdHs E tHC E tHC E 6qtHB F tH~ J 02mD6qX,gluHx H lHx H dHp H lH{ E /j0k0k0k,lHz F HHC E dHC E 6qnHA A dHt D dHt D dHw A dHs E  dHs E <dHs E XdHs E t5pdHs E dHv B 5pHX H 4o ,g FAD  ABH  ABK Q CBJ  ABK  ABF V ABO  ABN D CIH G ABN  CBL v ABG ~ ABO # ABE I ABE ? HBE v ABE ~ ABE D eFAA ] DBE E DBE  ABK h` FAA g ABF Z ABK ] ABA q ABK  ABF u ABE H E | D H E | D  K[ J P H 8 HV B ^ B H\ 87FBB B(A0A8D@ 8A0A(B BBBE  8 FBA A(D0 (I ABBG }FD0 GG  oH G W`$ = Vb {X ph 0 p  (3=O@ h~x @  } P#q 0PI0b {    p ` *@ C \ u    ` @   $ = V o  ` @ (    7 P i   @       # /= V o`  0G`rz 6 : & ,$2&8)>+D.J0P3V=\MbhhpnrtfznwhH   ( $"9(>.r4D:I@PFUL[R`Xd^hdljwpvn}d]TKB90'      % , 3 : A H O V x] rd lk fr _y W P I B : 2 , &                    % + 1 7 = C I P W ^ e l s z      + @ U @ j y             " ) 0 7 > mE fL _S Z va h o v I}   ) 9 "                      % `, 3 n: yA gH O ^V D] d #k  r 9y P   . ? [ L )     '    H  y e 4   ! ( / 6 0= XD K R Y `  g B n Hu  |  X     @ w 9   S  " _       k    $ +x2 9 @ G6 N U \) cC jP q] xj w     `  8 5JP 2Xr d/0/`0II0/`/7&/20>0H -YPh Hyp`P36d@522 3@ q! 41!l@p!0P!``":s"6"9 #d#t$t$6$tP%t%2&6'P&,9&uI'lZp'dm'lP(/(0(0(0)l) * *6+n2p+dG+d[P,do,d0-d-d.d.5.d0/d/5 / 0431,F01S\@AesIM0OPQS87 N3LЌ}ayPoaddRegUsage_AMD64AModeiregEnc3210__PRETTY_FUNCTION__.3585__PRETTY_FUNCTION__.5537vregEnc3210__PRETTY_FUNCTION__.5542iregEnc210__PRETTY_FUNCTION__.5527iregEnc3__PRETTY_FUNCTION__.5532ppHRegAMD64_lo32ireg32_names.4677__PRETTY_FUNCTION__.4680ireg64_names.4668__PRETTY_FUNCTION__.4670rexAMode_RdoAMode_RdoAMode_R_enc_reg__PRETTY_FUNCTION__.5603rexAMode_M__wrk__PRETTY_FUNCTION__.5634addRegUsage_AMD64RMImapRegs_AMD64RMIrRegUniverse_AMD64_initted.4662rRegUniverse_AMD64.4661__PRETTY_FUNCTION__.4715doAMode_M__wrk__PRETTY_FUNCTION__.5554__PRETTY_FUNCTION__.4982__PRETTY_FUNCTION__.5018__PRETTY_FUNCTION__.5030__PRETTY_FUNCTION__.5042__PRETTY_FUNCTION__.5069__PRETTY_FUNCTION__.5077__PRETTY_FUNCTION__.5085__PRETTY_FUNCTION__.5099__PRETTY_FUNCTION__.5106__PRETTY_FUNCTION__.5127__PRETTY_FUNCTION__.5133__PRETTY_FUNCTION__.5138__PRETTY_FUNCTION__.5145__PRETTY_FUNCTION__.5169__PRETTY_FUNCTION__.5177__PRETTY_FUNCTION__.5185__PRETTY_FUNCTION__.5199__PRETTY_FUNCTION__.5206__PRETTY_FUNCTION__.5213__PRETTY_FUNCTION__.5220__PRETTY_FUNCTION__.5227__PRETTY_FUNCTION__.5234__PRETTY_FUNCTION__.5241__PRETTY_FUNCTION__.5248__PRETTY_FUNCTION__.5261__PRETTY_FUNCTION__.5268__PRETTY_FUNCTION__.5281__PRETTY_FUNCTION__.5295__PRETTY_FUNCTION__.5360__PRETTY_FUNCTION__.5431__PRETTY_FUNCTION__.5493__PRETTY_FUNCTION__.5505__PRETTY_FUNCTION__.5522__PRETTY_FUNCTION__.5701__PRETTY_FUNCTION__.5675CSWTCH.1058CSWTCH.1055__PRETTY_FUNCTION__.5670CSWTCH.1057__PRETTY_FUNCTION__.5615__PRETTY_FUNCTION__.5587__PRETTY_FUNCTION__.5643CSWTCH.1056shortCTR.6040__PRETTY_FUNCTION__.6036__PRETTY_FUNCTION__.6048__PRETTY_FUNCTION__.6059.LC0.LC1.LC2.LC3.LC4.LC5.LC6.LC7.LC10.LC8.LC9.LC11.LC12.LC13.LC14.LC15.LC16.LC18.LC17.LC34.LC19.LC20.LC35.LC21.LC22.LC23.LC24.LC25.LC26.LC27.LC28.LC29.LC30.LC31.LC32.LC33.LC36.LC37.LC39.LC41.LC42.LC38.LC40.LC43.LC46.LC47.LC45.LC44.LC49.LC48.LC50.LC51.LC53.LC52.LC54.LC55.LC56.LC64.LC57.LC58.LC59.LC60.LC61.LC62.LC63.LC65.LC69.LC67.LC68.LC66.LC70.LC71.LC81.LC72.LC73.LC74.LC75.LC76.LC77.LC78.LC79.LC80.LC82.LC83.LC152.LC151.LC150.LC149.LC148.LC147.LC146.LC145.LC144.LC143.LC142.LC141.LC140.LC139.LC138.LC137.LC136.LC135.LC134.LC133.LC132.LC131.LC130.LC129.LC128.LC127.LC126.LC125.LC124.LC123.LC122.LC121.LC120.LC119.LC118.LC117.LC116.LC115.LC114.LC113.LC112.LC111.LC110.LC109.LC108.LC107.LC106.LC105.LC104.LC103.LC102.LC101.LC100.LC99.LC98.LC97.LC96.LC95.LC94.LC93.LC92.LC91.LC90.LC89.LC88.LC87.LC86.LC85.LC84.LC153.LC154.LC155.LC157.LC156.LC158.LC159.LC160.LC161.LC162.LC163.LC164.LC165.LC166.LC167.LC168.LC169.LC170.LC171.LC172.LC182.LC208.LC238.LC237.LC236.LC235.LC234.LC233.LC197.LC232.LC210.LC211.LC181.LC180.LC229.LC225.LC224.LC223.LC228.LC226.LC227.LC179.LC178.LC221.LC220.LC218.LC219.LC217.LC216.LC215.LC209.LC214.LC212.LC241.LC242.LC243.LC205.LC203.LC206.LC207.LC202.LC204.LC196.LC198.LC199.LC200.LC176.LC177.LC201.LC175.LC194.LC195.LC193.LC173.LC192.LC190.LC184.LC185.LC183.LC188.LC244.LC240.LC239.LC187.LC189.LC222.LC191.LC186.LC174.LC231.LC230.LC213.LC245.LC252.LC253.LC251.LC247.LC250.LC254.LC248.LC246.LC249.LC257.LC255.LC256.LC258.LC259.LC260.LC261.LC262.LC263.LC264.LC265.LC290.LC279.LC271.LC289.LC281.LC278.LC282.LC267.LC275.LC273.LC284.LC288.LC277.LC280.LC272.LC285.LC283.LC270.LC286.LC276.LC268.LC274.LC269.LC287.LC266.LC297.LC291.LC292.LC293.LC294.LC295.LC296.LC298.LC302.LC299.LC300.LC301.LC303.LC304.LC305.LC306.LC307.LC308_GLOBAL_OFFSET_TABLE_addHRegUsevpanicvex_assert_failvex_printfppHRegppHRegAMD64lookupHRegRemapgetRRegUniverse_AMD64RRegUniverse__initRRegUniverse__check_is_saneshowAMD64CondCodeAMD64AMode_IRprivate_LibVEX_alloc_currprivate_LibVEX_alloc_lastprivate_LibVEX_alloc_OOMAMD64AMode_IRRSppAMD64AModeAMD64RMI_ImmAMD64RMI_RegAMD64RMI_MemppAMD64RMIppAMD64RMI_lo32AMD64RI_ImmAMD64RI_RegppAMD64RIAMD64RM_RegAMD64RM_MemppAMD64RMshowAMD64UnaryOpshowAMD64AluOpshowAMD64ShiftOpshowA87FpOpshowAMD64SseOpAMD64Instr_Imm64AMD64Instr_Alu64RAMD64Instr_Alu64MAMD64Instr_Sh64AMD64Instr_Test64AMD64Instr_Unary64AMD64Instr_Lea64AMD64Instr_Alu32RAMD64Instr_MulLAMD64Instr_DivAMD64Instr_PushAMD64Instr_CallAMD64Instr_XDirectAMD64Instr_XIndirAMD64Instr_XAssistedAMD64Instr_CMov64AMD64Instr_CLoadAMD64Instr_CStoreAMD64Instr_MovxLQAMD64Instr_LoadEXAMD64Instr_StoreAMD64Instr_Set64AMD64Instr_Bsfr64AMD64Instr_MFenceAMD64Instr_ACASAMD64Instr_DACASAMD64Instr_A87FreeAMD64Instr_A87PushPopAMD64Instr_A87FpOpAMD64Instr_A87LdCWAMD64Instr_A87StSWAMD64Instr_LdMXCSRAMD64Instr_SseUComISAMD64Instr_SseSI2SFAMD64Instr_SseSF2SIAMD64Instr_SseSDSSAMD64Instr_SseLdStAMD64Instr_SseCStoreAMD64Instr_SseCLoadAMD64Instr_SseLdzLOAMD64Instr_Sse32Fx4AMD64Instr_Sse32FLoAMD64Instr_Sse64Fx2AMD64Instr_Sse64FLoAMD64Instr_SseReRgAMD64Instr_SseCMovAMD64Instr_SseShufAMD64Instr_SseShiftNAMD64Instr_SseMOVQAMD64Instr_EvCheckAMD64Instr_ProfIncppAMD64InstrppRetLocgetRegUsage_AMD64InstrmapRegs_AMD64InstrgenSpill_AMD64ppHRegClassgenReload_AMD64genMove_AMD64directReload_AMD64emit_AMD64InstrppIRJumpKindevCheckSzB_AMD64read_misaligned_ULong_LEwrite_misaligned_ULong_LEwrite_misaligned_UInt_LEunchainXDirect_AMD64read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H{1I;(HfDHH=1"AG@AH H5H=HsLD$lHs0LHD$aHs LD$$aIOACA;GsH{, H{( DωDL$(q1I0He0DL$( DS1I0HG0|$$0 91I0H-0\$(HH|$4I0H/ H葮IONjCA;GD,D0I0H/Hs LuDHHH=1)HHKHt$XLD$TH|$THAHD$`L@s݃D$hY^wR|$\{uOKDD$TEH H5H={H H5H=Iu>LnHIGA;_qHsL'jAH HHH H5H=H H5H=H H5H=IuLiIuLH^Ɓt1@Ǎ|?HIuLOiIuLH@dHڿHLǾH=18LǾH=1D~dLhHIGA;_0?D,u "DQ|$T'CA;GDIWH:!IO@ D*HI0HJ,D$\x@ DHI0H,t$TL\0|$TCIWA;GD,H0IGA;_Iu,Lr ,IuLqIGA;_45H !H5H=LǾH=1IuL[A}P Ht1@Ǎ|?IuLaA}P HHHH߾H=1A I}AH1I;(HHuLHپ1uHbHH=1HHH=1HHH=1H6LLD$8LD$8H H5H=H H5H=n'DHI0Hz'H ,H5H=H +H5H=LL XHH H5H=IuL譒A}P ھ1HIuLA}P LI+Lھ1LLD$LD$VIuL'A}P ھ1HzLLD$8LD$8IuLaIuLHϤHپ12H UH5H=H TH5H=IuLaIuLHАHپ1IuL^aIuHHHH=1HHH=1Xpriv/host_generic_regs.hix <= 0xFFFFFenc == 0priv/host_amd64_isel.ctmp < env->n_vregmap hregClass(src) == HRcVec128hregClass(dst) == HRcVec128hregClass(src) == HRcInt64hregClass(dst) == HRcInt640!preShift32Rc->tag == Ico_U8ty == e->Iex.CCall.rettyis_sane_RetLoc(rloc)rloc.pri == RLPri_IntaddToSp == 0hregClass(r) == HRcInt64hregIsVirtual(r)sane_AMode(rm->Arm.Mem.am)-10000 < bias && bias < 10000elemSz == 1 || elemSz == 8ty == Ity_I64sane_AMode(am)sane_AMode(rmi->Armi.Mem.am)eiselCondCode(amd64): CmpXX16iselCondCode(amd64): CmpXX64iselCondCode(amd64): CmpXX32iselCondCode(amd64)e->tag != Iex_VECRETe->Iex.Get.ty == Ity_I64!hregIsInvalid(r_vecRetAddr)nVECRETs == 1nVECRETs == 0nGSPTRs == 0 || nGSPTRs == 1*stackAdjustAfterCall == 0is_RetLoc_INVALID(*retloc)ty == Ity_F32e->Iex.Load.ty == Ity_F32hregClass(r) == HRcVec128iselFltExpr_wrkty == Ity_F64iselDblExpr(amd64): conste->Iex.Load.ty == Ity_F64iselDblExpr_wrkty == Ity_V128iselVecExpr_wrkty == Ity_V256iselDVecExpr_wrkhregClass(*rHi) == HRcVec128hregClass(*rLo) == HRcVec128hregIsVirtual(*rHi)hregIsVirtual(*rLo)iselInt128ExprhregClass(*rHi) == HRcInt64hregClass(*rLo) == HRcInt64arch_host == VexArchAMD64iselBB(amd64): IRTemp type -- d->tmp == IRTemp_INVALIDrloc.pri == RLPri_Nonerloc.pri == RLPri_V128SpReladdToSp >= 16rloc.pri == RLPri_V256SpReladdToSp >= 32cas->expdHi == NULLcas->dataHi == NULLiselStmt(amd64) -- PUT(%d) = ; exit-cdst->tag == Ico_U64rc >= HRcInt32 && rc <= HrcLASTn > 0 && n < 256 && (n%8) == 0sane_AMode: unknown amd64 amode tage->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U8typeOfIRExpr(env->type_env, arg1) == Ity_I64typeOfIRExpr(env->type_env, arg2) == Ity_I64typeOfIRExpr(env->type_env, arg2) == Ity_I8vexGetAllocMode() == VexAllocModeTEMPiselIntExpr_R(amd64): cannot reduce treety == Ity_I64 || ty == Ity_I32 || ty == Ity_I16 || ty == Ity_I8hregClass(rm->Arm.Reg.reg) == HRcInt64hregIsVirtual(rm->Arm.Reg.reg)iselIntExpr_RM: unknown amd64 RM tagiselIntExpr_RMI.Iex_Const(amd64)hregClass(ri->Ari.Reg.reg) == HRcInt64hregIsVirtual(ri->Ari.Reg.reg)iselIntExpr_RI: unknown amd64 RI taggenGuestArrayOffset(amd64 host)hregClass(rmi->Armi.Reg.reg) == HRcInt64hregIsVirtual(rmi->Armi.Reg.reg)iselIntExpr_RMI: unknown amd64 RMI tagtypeOfIRExpr(env->type_env,e) == Ity_I1e->Iex.Const.con->tag == Ico_U1e->Iex.Const.con->Ico.U1 == True || e->Iex.Const.con->Ico.U1 == FalseiselCondCode(amd64): CmpXX8(expr,0:I8)iselCondCode(amd64): CmpXX8(expr,expr)cal->Iex.CCall.retty == Ity_I64con->Iex.Const.con->tag == Ico_U64doHelperCall(AMD64): cannot currently handle > 6 argstypeOfIRExpr(env->type_env, args[i]) == Ity_I64typeOfIRExpr(env->type_env, e) == Ity_I64e->Iex.Const.con->tag == Ico_U64typeOfIRExpr(env->type_env,e->Iex.ITE.cond) == Ity_I1e->Iex.Const.con->tag == Ico_V128iselVecExpr (amd64, subarch = %s): can't reduce ! hregIsInvalid(env->vregmapHI[tmp])e->Iex.Const.con->tag == Ico_V256iselDVecExpr (amd64, subarch = %s): can't reduce typeOfIRExpr(env->type_env,e) == Ity_I1280 == (hwcaps_host & ~(VEX_HWCAPS_AMD64_SSE3 | VEX_HWCAPS_AMD64_SSSE3 | VEX_HWCAPS_AMD64_CX16 | VEX_HWCAPS_AMD64_LZCNT | VEX_HWCAPS_AMD64_AVX | VEX_HWCAPS_AMD64_RDTSCP | VEX_HWCAPS_AMD64_BMI | VEX_HWCAPS_AMD64_AVX2 | VEX_HWCAPS_AMD64_F16C | VEX_HWCAPS_AMD64_RDRAND))archinfo_host->endness == VexEndnessLEiselStmt(amd64): Ist_Exit: dst is not a 64-bit value!"#$%&'()*+,-./0123EFGEFGiselNextiselIntExpr_R_wrkiselIntExpr_RiselCondCode_wrkmk_iMOVsd_RRlookupIRTempiselIntExpr_AMode_wrkiselIntExpr_AModeadd_to_rsplookupIRTempPairiselIntExpr_single_instructiondoHelperCallmk_vMOVsd_RRiselDVecExpr_wrkiselDVecExpriselVecExpr_wrkiselVecExpriselFltExpr_wrkiselFltExpriselDblExpr_wrkiselDblExpriselIntExpr_RM_wrkiselIntExpr_RMiselInt128Expr_wrkiselInt128ExpriselIntExpr_RMI_wrkiselIntExpr_RMIhregClassiselIntExpr_RI_wrkiselIntExpr_RIgenGuestArrayOffsetiselStmtmkHRegiselSB_AMD64GNUzRx oD\ P 8%AA^ TWAe J W I xFp J Dz R ;\;\L BBA C(K0 (D ABBC  (D ABBH 4(AFL0 AAD Q JAL 4`ADD U AAH IJA(BFI0w IBM (AI @ AE Q JE Dm G j F 8BAA ] ABD _ ABF 8LBAA  ABD v HDF t'BBB B(D0D8DCRA 8A0A(B BBBH  8C0A(B BBBF Db J (BDG  DBC LHBBA A(G@ (A ABBH q (J ABBH (BDG   ABF HBEE B(D0A8G@^ 8F0D(B BBBF @BBB B(D0GP 0A(B BBBE (TBDG  DBD 8BEB A(K@ (I BBBK |BBB B(A0DPT 0A(B BBBF  0D(B EBBH  0F(B BBBF XF`QXAPd<" BEE E(D0D8J7 8A0A(B BBBA  8J0A(B BBBE HM BBB B(D0D8DPu 8A0A(B BBBE Db J H BBB E(A0D8DP 8A0A(B BBBA HXxBBB B(A0A8Dp 8D0A(B BBBA HBBB B(A0A8DpX 8A0A(B BBBH HBBB B(A0A8Dp 8A0A(B BBBJ t<FBB B(A0A8D 8A0A(B BBBA SOB VJAo1!p%< UWer   P;; 8 6O\`g0| 'PU" 9`l1-H@X<jF{k`x@C2X'@@3V7e~  #< Upn`M ~  0  - FP_px8 x ( '0G \^z$* 0@6<BPHN0T(Z`hflrx~=VgX0@ Nh 1&,28h>HDJbPV\bh(ntwz^D*nP|89M app"(.4:@GNU\cjqx.X<zf     0 > J \ o |           3 ? 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0x20alwaysno-flagcr7.so=0cr7.eq=0cr7.gt=0cr7.lt=1cr7.gt=1cr7.eq=1cr7.so=1cr7.lt=0ppPPCCondCodeflag == Pcf_NONEflag != Pcf_NONEct != Pct_ALWAYSdopyPPCAMode0(%d(),ppPPCAModeimm16 != 0x8000%d%uppPPCRH0x%llxppPPCRIsimm5 >= -16 && simm5 <= 15hregClass(reg) == HRcVec128ppPPCVI5spopcntdnotcntlzwcntlzdextswpopcntwnegshowPPCUnaryOpxoriaddsubandororiandi.subiaddixorshowPPCAluOpsradisrwsrawsrdsrawisrdisldsrwisldislwislwsradshowPPCShftOprrdtrdiexqfmulfdivfmaddfmsubfmaddsfmsubsfaddsfsubsfmulsfdivsfsqrtfabsfnegfmrfresfrsqrtefrimfrinfripfrizxsaddqpxsubqpxsmulqpxsdivqpxsmaddqpxsmsubqpxsnmaddqpxsnmsubqpxsaddqpoxsubqpoxsmulqpofaddxsmaddqpoxsmsubqpoxsnmaddqpoxsnmsubqpoxscvqpdpxscvqpdpoxscvdpqpxscvsdqpxscvudqpxscvqpsdzxscvqpswzxscvqpudzxscvqpuwzdadddaddqdsubdsubqdmuldmulqddivdddivqdctdpdrspdctfixdcffixdctqpqdcffixqdquadquaqdxexdxexqdiexfsubshowPPCFpOpxvcvdphpxvcvhpdpvorvxorvnotvupkhsbvupkhshvupklsbvupklshvupkhpxvupklpxvaddu_mvaddu_svadds_svsubu_mvsubu_svsubs_svmuluvmulouvmulosvmuleuvmulesvavguvavgsvmaxuvmaxsvminuvminsvcmpequvcmpgtuvcmpgtsvslvsrvsravrlvpku_umvpku_usvpks_usvpks_ssvpkpxvmrghvmrglvmrgowvmrgewvshasigmawvmrbcdadd.bcdsub.bcdcfsq.bcdctsq.vmul10uqvmul10cuqvmul10euqvmul10ecuqxsrqpi|xxsrqpxpvpmsumv_cipher_vclz_vctz_vgbbdxvcvhpspxvcvsphpvandshowPPCAvOpvrfizvaddfpvmaddfpvmaxfpvminfpvcmpeqfpvcmpgtfpvcmpgefpvrefpvrsqrtefpvcfuxvcfsxvctuxsvctsxsvrfimvrfipvrfinvsubfpshowPPCAvFpOp!syned0 == (argiregs & ~mask)is_sane_RetLoc(rloc)cond.test != Pct_ALWAYSsz == 4 || sz == 8tmp == True || tmp == FalsePPCInstr_FpCftI(ppc_host)ceicmpcmplufastslowstdstw6432xzfc?????fcfidufctidfctidufctiwfctiwufcfidfcfidus1mtlrmflrebehewissmr li %s %s%s %s%c%s %%cr%u,mul%c%c%s div%c%s%s call: if (%s) { ; mtctr r10 ; bctrl [r%d] }(xDirect) if (%s) { imm64 r30,0x%llx; std r30,imm32 r30,0x%llx; stw r30,; mtctr r30; bctrl }(xIndir) imm%s r30,$disp_cp_xindir; mtctr r30; bctr }(xAssisted) cmov (%s) : }l%c%s%s l%carx ,%%r0,st%c%s st%ccx. set (%s),: { li ,1 }: { mfcr r0 ; rlwinm ,r0,%u,31,31; xori ,1mfcr mfence (=sync)lf%c%s stf%c%s stfiwz ,0(frsp fpcmov (%s) if (fr_dst != fr_src) { fmr mtfsf 0xFF,,0, %sfcmpo %%cr1,; mfcr ; rlwinm ,8,28,31 ; lv%sx stv%sx %%r30%s(b) %s(h) %s(w) vperm vsel lvsl lvsr vsldoi ,%dvsplt%s%c , %davcmov (%s) if (v_dst != v_src) { vmr mtvscr drintx drintxq dquaq dxexq diexq dcmpo %%cr1,dcmpoq %%cr1,(evCheck) lwz r30,; addic. r30,r30,-1; ; bge nofail; lwz r30,; mtctr r30; bctr; nofail: ppPPCInstr: No such tag(%d) ppPPCInstraddRegUsage_PPCRHaddRegUsage_PPCAModeaddRegUsage_PPCRIaddRegUsage_PPCVI5sgetRegUsage_PPCInstrmapRegs_PPCRHmapRegs_PPCAModemapRegs_PPCRImapRegs_PPCVI5smapRegs_PPCInstr!hregIsVirtual(rreg)!mode64nbuf >= 32srcR->Prh.Imm.synedsrcR->Prh.Imm.imm16 != 0x8000!srcR->Prh.Imm.synedsz32n > 0 && n < 32n > 0 && n < 64n >= 0 && n < 32syned == srcR->Prh.Imm.synedimm_srcR != 0x8000!i->Pin.MulL.syneddelta >= 16 && delta <= 32disp_cp_xindir != NULLr_src < 0x20delta >= 8 && delta <= 24cond.flag != Pcf_NONEcc.test != Pct_ALWAYSfreg < 0x20shift <= 0xF!(*is_profInc) => emit_PPCInstrp - &buf[0] <= 64endness_host == VexEndnessBE0 == (3 & (HWord)p)len == (mode64 ? 28 : 16)len == 20len == 8%r0%r1%r2%r3%r4%r5%r6%r7%r8%r9%r10%r11%r12%r13%r14%r15%r16%r17%r18%r19%r20%r21%r22%r23%r24%r25%r26%r27%r28%r29%r30%r31rc >= HRcInt32 && rc <= HrcLASThregClass(r) == (mode64 ? HRcInt64 : HRcInt32)idx >= -0x8000 && idx < 0x8000syned == True || syned == False(Long)imm64 == (Long)(Int)(UInt)imm64sz == 1 || sz == 2 || sz == 4 || sz == 8imm64-fixed5 r30,$disp_cp_chain_me_to_%sEP; imm32-fixed2 r30,$disp_cp_chain_me_to_%sEP; li r31,$IRJumpKind_to_TRCVAL(%d); (profInc) imm64-fixed5 r30,$NotKnownYet; ld r29,(r30); addi r29,r29,1; std r29,(r30)(profInc) imm32-fixed2 r30,$NotKnownYet; lwz r29,4(r30); addic. r29,r29,1; stw r29,4(r30)lwz r29,0(r30); addze r29,r29; stw r29,0(r30)0 == (argir & ~((1<<3)|(1<<4)|(1<<5)|(1<<6) |(1<<7)|(1<<8)|(1<<9)|(1<<10)))genSpill_PPC: unimplemented regclassgenReload_PPC: unimplemented regclassgenMove_PPC: unimplemented regclassdisp_cp_chain_me_to_slowEP != NULLdisp_cp_chain_me_to_fastEP != NULLi->Pin.XDirect.cond.flag != Pcf_NONEi->Pin.XDirect.cond.flag == Pcf_NONE0 == (((ULong)i->Pin.XDirect.dstGA) >> 32)delta >= 16 && delta <= 64 && 0 == (delta & 3)i->Pin.XIndir.cond.flag != Pcf_NONEi->Pin.XIndir.cond.flag == Pcf_NONEdelta >= 16 && delta <= 32 && 0 == (delta & 3)i->Pin.XAssisted.cond.flag != Pcf_NONEi->Pin.XAssisted.cond.flag == Pcf_NONEemit_ARMInstr.Pin_XAssisted: unexpected jump kindi->Pin.CMov.cond.test != Pct_ALWAYS0 == (am_addr->Pam.IR.index & 3)sz == 1 || sz == 2 || sz == 4 || sz == 16sz == 8 || sz == 16 || sz == 32hregClass(i->Pin.AvSplat.src->Pvi.Reg) == HRcVec128ERROR: emit_PPCInstr default case Error: emit_PPCInstr case Pin_DfpExtractExp, case inst Default Error: emit_PPCInstr case Pin_Dfp128Unary, case inst Default ERROR: emit_PPCInstr quad default case %d Pin_DfpQuantize128: default case, couldn't find inst to issue evCheckSzB_PPC() == (UChar*)p - (UChar*)p0(endness_host == VexEndnessBE) || (endness_host == VexEndnessLE)isLoadImm_EXACTLY2or5(p, 30, (Addr)disp_cp_chain_me_EXPECTED, mode64, endness_host)fetch32(p + (mode64 ? 20 : 8) + 0, endness_host) == 0x7FC903A6fetch32(p + (mode64 ? 20 : 8) + 4, endness_host) == 0x4E800421isLoadImm_EXACTLY2or5(p, 30, (Addr)place_to_jump_to_EXPECTED, mode64, endness_host)fetch32(p + (mode64 ? 20 : 8) + 4, endness_host) == 0x4E800420isLoadImm_EXACTLY2or5(p, 30, 0x6555655565556555ULL, True , endness_host)fetch32(p + 20, endness_host) == 0xEBBE0000fetch32(p + 24, endness_host) == 0x3BBD0001fetch32(p + 28, endness_host) == 0xFBBE0000isLoadImm_EXACTLY2or5(p, 30, 0x65556555ULL, False , endness_host)fetch32(p + 8, endness_host) == 0x83BE0004fetch32(p + 12, endness_host) == 0x37BD0001fetch32(p + 16, endness_host) == 0x93BE0004fetch32(p + 20, endness_host) == 0x83BE0000fetch32(p + 24, endness_host) == 0x7FBD0194fetch32(p + 28, endness_host) == 0x93BE0000 J J J HIpatchProfInc_PPCunchainXDirect_PPCchainXDirect_PPCmkFormXFXdo_load_or_store_machine_worddo_load_or_store_word32mkFormMmkFormXfregEnciregEncmkFormZ23mkFormZ22mkFormVXvregEncmkFormBmkFormVAmkFormVXImkLoadImmmkFormVXRmkFormVSXRNDmkFormVX_BX_TXmkFormXFLdoAMode_IRdoAMode_RRmkFormAmkFormVXR0mkFormDmkMoveRegmkFormXOmkFormXSmkFormMDemit_PPCInstrgenReload_PPCgenSpill_PPCgetRegUsage_PPCInstrPPCInstr_AvCMovPPCInstr_FpCMovPPCInstr_FpCftIPPCInstr_FpLdStPPCInstr_StoreCPPCInstr_StorePPCInstr_LoadLPPCInstr_LoadPPCInstr_CMovPPCInstr_CallPPCInstr_MulLPPCInstr_LIPPCVI5s_RegPPCVI5s_ImmPPCRH_ImmPPCAMode_IRinvertCondTestmk_PPCCondCodehregClassppHRegPPCGNUzRx Dj B 8Dy C TDQ K pD{ A DC I kDz B Gb G DY C DK A DK A 4DP D PDR J lD| H DC I DU G De G De G Fh B Fh B 0Fr H LM`A G D I 8BFJ n DKI m DKL D A  A ,BAA  DBE ,-Df F  G P HdFBB B(A0A8FX 8H0A(B BBBC $RS K gQJ N oHU K  Cd lHy G <2mPH} K ~ A pEi J g I H I /j0OyXgak M D L Z E 0k /j0 OqXc E k E D L Z E TdHr F pH{ E 0OqXc E k E D L Z E TLX]S %8E9PlHx H l9t=x>y>y5ptHE C B} HT D p H $;v87rL:u`lHy G |HZ F HY G HZ F HY G 3n/j,g(5p<8sP5pd8sx8s<wtH I 2m2m5p8s 9t <w4 <wH @{\ 6qp <w <w @{ 8s 8s 8s @{ 5p <w$ 4o8 ,gL J E h lHx H  :u 5p 3n ;v 5p 8s 9t 8s$ 8s8 8sL 8s` 8st 5p 8s 8s 7r 9t 7r lHx H  /j 5p0 8sD 9tX 8sl jFBA C(D0l (A ABBN V (A ABBL u (A ABBM  (C ABBF  (A ABBI  (C ABBI K (A ABBO  (A ABBK Q (C ABBG `@  FBB B(D0A8F` 8D0A(B BBBG  8A0A(B BBBD D DFAD ^ ABD K ABB ] ABA , XH F @ H | D R F ,XH F @ H | D R F LKv G x H pi_FBB B(A0A8D` 8A0A(B BBBG RhBpFxKX`HhPpNxKX`PhBp`hA`AhBp_xJZ`U 8A0A(B BBBB ]hKpKhB`@hJpZxKX`FhPpKxL]`FhQpKxJZ`hJpZxKX`FhPpKxKX`MhOpKxKVhGp`hA`_hKpVxKVhGpZhA`^hBpKxKX`FhLpYxJZ`FhQpLhA`}hBpWhB`whOpSxKX`HhQpKxJZ`{hPpPxJZ`FhQpKhB`chKpThB`HhMpOhB`hGpUhB`hIpThA`$hMpOhA`$hLpOhA`^hBpKxIb`PhGp[hL`AhHpNxJZ`khOpNxJ\`FhQpKxJZ`xhMpKhB`phKpXxJ^`FhPpLhA`PhHpYhB`AhBp`hA`ZhBpFxKX`HhPpNxIb`\hHplhA`AhBpNxJZ`hMpQhA`MhEp_hA`IhGpThA`hNpOhA`2hMpGhA`hKpVxKVhGp^hB`hKpYhA`ZhIpThA`hNpQhB`WhKpXhA`hKpOhB`hMpqhA`bhKpUhB`IhKpWhA`FhKpQhB`LhKpRhA`LhKpRhB`LhMpOhA`LhKpRhB`LhKpRhB`LhMpOhB`LhMpThA`FhNpQhB`IhJpOhB`LhKpQhB`IhOpLhA`LhMpNhB`LhMpOhB`LhJpOhA`LhMpOhA`OhMpPhB`OhMpPhA`OhMpShB`hGp]hB`YhLpUhA`IhMpNhA`OhMpNhB`OhMpOhB`OhMpOhA`OhJpUhB`LhMpOhB`OhMpRhB`OhLpUhA`IhMpQhA`OhMpNhB`MhNpNhB`MhNpRhB`JhNpOhB`thPpLhA`VhNpOhB`LhMpLhB`VhNpOhA`LhMpLhB`LhMpLhB`MhMpPhB`LhJpShB`JhMpUhA`FhJpShB`JhMpUhA`GhMpPhB`LhMpLhB`MhMpPhB`LhJpShB`JhMpUhA`FhJpShB`JhMpUhA`GhMpPhB`LhMpLhB`MhMpPhB`LhJpShB`JhMpUhA`FhMpLhB`MhMpPhB`LhJpShB`JhMpUhA`hNpOhA`LhNpRhB`IhNpOhB`LhNpThA`FhNpOhB`hMpRhA`LhOpLhA`LhNpQhB`IhMpOhB`LhMpOhB`LhMpNhB`LhMpOhA`| hBpE J hHpE J hHpE MhLpLhA`U hHpE M hGpE JhKpKhB`UhMpJhB`'hMpLhA`hNpQhB`ghMpThA`FhMpJhB`hMpGhB` hHpE AhMpJhA`hMpVhB`uhMpUhA`FhNpOhA`nhNpThA`hEp_hB`hKpShA`LhMpOhA`ehKpShB`ThMpOhB`ehKpShB`ehHpUhB`+hOpLhA`nhIpThA`phHpUhB`mhLpPhG`hOpOhB`"hMpNhB`chNpRhB`hNpQhB`fhNpOhB`LhNpRhB`ehNpOhB`LhNpThA`FhNpOhB`hNpNhB`X <lFBE G(D0 (D EBBD <FBE G(D0 (D EBBD ,FED  BBC .6Od }p 8 kx x0E( ^tX p    " ; P i` h      1 9R@ZsMP @ P   B[0eH ~-  P $p=` VP o@ 0   7PipP8 (1 (<G ` y `@  )3=GQ^ ht!'-39?EKQW]"c<i oNu`{r'.QuZHc? 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S@mkFormM.constprop.0__PRETTY_FUNCTION__.6484mkFormD__PRETTY_FUNCTION__.6375mkFormVX.constprop.0__PRETTY_FUNCTION__.6648mkFormB.constprop.0__PRETTY_FUNCTION__.6471mkFormVXI.constprop.0__PRETTY_FUNCTION__.6699mkFormXFX__PRETTY_FUNCTION__.6433mkFormVX_BX_TX.constprop.0__PRETTY_FUNCTION__.6676mkFormVA.constprop.0__PRETTY_FUNCTION__.6723mkFormVXR.constprop.0__PRETTY_FUNCTION__.6711mkFormZ22.constprop.0__PRETTY_FUNCTION__.6509mkFormVXR0.constprop.0__PRETTY_FUNCTION__.6688mkFormX__PRETTY_FUNCTION__.6399mkFormMD.constprop.0__PRETTY_FUNCTION__.6387mkFormXO.constprop.0__PRETTY_FUNCTION__.6412mkFormVSXRND.constprop.0__PRETTY_FUNCTION__.6661mkFormZ23.constprop.0__PRETTY_FUNCTION__.6522mkFormA.constprop.0__PRETTY_FUNCTION__.6497fregEnc__PRETTY_FUNCTION__.3585__PRETTY_FUNCTION__.6350vregEnc__PRETTY_FUNCTION__.6355iregEnc__PRETTY_FUNCTION__.6345mkLoadImm_EXACTLY2or5.constprop.0doAMode_RR.constprop.0__PRETTY_FUNCTION__.6545doAMode_IR__PRETTY_FUNCTION__.6533ppLoadImmireg32_names.5153__PRETTY_FUNCTION__.5155do_load_or_store_word32.constprop.0__PRETTY_FUNCTION__.6622mkLoadImm__PRETTY_FUNCTION__.6553do_load_or_store_machine_word__PRETTY_FUNCTION__.6594isLoadImm_EXACTLY2or5.constprop.0rRegUniverse_PPC_initted.5146rRegUniverse_PPC.5145__PRETTY_FUNCTION__.5174__PRETTY_FUNCTION__.5178__PRETTY_FUNCTION__.5184__PRETTY_FUNCTION__.5221__PRETTY_FUNCTION__.5279__PRETTY_FUNCTION__.5284__PRETTY_FUNCTION__.5515__PRETTY_FUNCTION__.5562__PRETTY_FUNCTION__.5580__PRETTY_FUNCTION__.5607__PRETTY_FUNCTION__.5615__PRETTY_FUNCTION__.5623__PRETTY_FUNCTION__.5631__PRETTY_FUNCTION__.5639__PRETTY_FUNCTION__.5701__PRETTY_FUNCTION__.5850__PRETTY_FUNCTION__.5868__PRETTY_FUNCTION__.5992__PRETTY_FUNCTION__.6154__PRETTY_FUNCTION__.6311__PRETTY_FUNCTION__.6325__PRETTY_FUNCTION__.6737CSWTCH.506CSWTCH.505__PRETTY_FUNCTION__.6448__PRETTY_FUNCTION__.6637__PRETTY_FUNCTION__.6460__PRETTY_FUNCTION__.7491__PRETTY_FUNCTION__.7502__PRETTY_FUNCTION__.7512.LC0.LC1.LC2.LC3.LC4.LC5.LC6.LC7.LC8.LC9.LC10.LC11.LC12.LC13.LC14.LC15.LC16.LC17.LC18.LC19.LC20.LC21.LC22.LC23.LC24.LC25.LC26.LC27.LC28.LC29.LC30.LC31.LC32.LC34.LC38.LC36.LC39.LC33.LC35.LC37.LC41.LC40.LC42.LC43.LC44.LC48.LC52.LC49.LC47.LC50.LC46.LC51.LC45.LC53.LC54.LC55.LC56.LC57.LC58.LC62.LC59.LC61.LC60.LC63.LC65.LC64.LC66.LC67.LC68.LC69.LC70.LC71.LC72.LC73.LC76.LC80.LC77.LC78.LC75.LC79.LC74.LC81.LC91.LC82.LC83.LC90.LC84.LC89.LC85.LC88.LC86.LC87.LC92.LC105.LC94.LC100.LC103.LC102.LC95.LC97.LC104.LC93.LC99.LC101.LC96.LC98.LC173.LC136.LC143.LC157.LC170.LC169.LC137.LC129.LC113.LC166.LC111.LC110.LC134.LC141.LC133.LC140.LC132.LC128.LC138.LC130.LC156.LC155.LC154.LC153.LC152.LC151.LC150.LC149.LC148.LC147.LC146.LC145.LC144.LC112.LC135.LC142.LC165.LC161.LC127.LC126.LC124.LC125.LC123.LC122.LC121.LC120.LC119.LC118.LC107.LC171.LC106.LC167.LC164.LC163.LC162.LC117.LC116.LC115.LC114.LC109.LC139.LC168.LC160.LC159.LC158.LC131.LC108.LC172.LC231.LC233.LC232.LC218.LC220.LC234.LC223.LC222.LC221.LC227.LC226.LC225.LC224.LC174.LC175.LC236.LC235.LC186.LC185.LC177.LC184.LC183.LC182.LC181.LC180.LC179.LC178.LC219.LC229.LC228.LC230.LC217.LC216.LC215.LC214.LC213.LC212.LC211.LC210.LC209.LC208.LC207.LC206.LC205.LC204.LC203.LC202.LC201.LC200.LC199.LC198.LC197.LC196.LC195.LC194.LC193.LC192.LC191.LC190.LC189.LC188.LC187.LC176.LC237.LC238.LC241.LC256.LC240.LC242.LC255.LC239.LC251.LC252.LC253.LC254.LC243.LC244.LC245.LC246.LC247.LC248.LC249.LC250.LC257.LC258.LC259.LC261.LC260.LC262.LC263.LC264.LC265.LC266.LC300.LC363.LC376.LC311.LC312.LC313.LC314.LC317.LC274.LC275.LC318.LC320.LC305.LC306.LC307.LC308.LC309.LC270.LC273.LC268.LC304.LC297.LC303.LC388.LC389.LC269.LC271.LC272.LC302.LC377.LC267.LC301.LC381.LC354.LC355.LC356.LC382.LC378.LC383.LC384.LC385.LC316.LC386.LC387.LC342.LC341.LC280.LC332.LC330.LC331.LC281.LC329.LC326.LC327.LC298.LC328.LC324.LC277.LC276.LC325.LC279.LC278.LC322.LC323.LC321.LC379.LC380.LC334.LC337.LC338.LC339.LC340.LC333.LC345.LC346.LC343.LC344.LC375.LC296.LC370.LC368.LC369.LC357.LC366.LC293.LC294.LC295.LC358.LC360.LC365.LC364.LC362.LC361.LC351.LC290.LC352.LC348.LC349.LC350.LC292.LC291.LC353.LC284.LC285.LC347.LC372.LC373.LC374.LC310.LC282.LC288.LC283.LC289.LC319.LC315.LC390.LC391.LC392.LC359.LC367.LC335.LC336.LC371.LC299.LC286.LC287.LC393.LC394.LC396.LC399.LC400.LC397.LC395.LC398.LC401.LC404.LC405.LC402.LC403.LC406.LC407.LC408.LC409.LC410.LC411.LC456.LC448.LC454.LC455.LC435.LC438.LC434.LC431.LC426.LC429.LC453.LC436.LC423.LC424.LC442.LC441.LC432.LC433.LC452.LC428.LC425.LC440.LC446.LC430.LC427.LC444.LC437.LC422.LC415.LC419.LC416.LC420.LC421.LC414.LC413.LC443.LC417.LC445.LC412.LC439.LC418.LC450.LC451.LC449.LC447.LC458.LC457.LC459.LC460.LC461.LC462.LC463.LC464.LC465.LC478.LC468.LC472.LC471.LC466.LC467.LC473.LC474.LC469.LC470.LC475.LC476.LC477_GLOBAL_OFFSET_TABLE_vex_assert_failvpanicvex_printfppHReggetRRegUniverse_PPCRRegUniverse__initRRegUniverse__check_is_saneppHRegPPCshowPPCCondCodemk_PPCCondCodeinvertCondTestPPCAMode_IRprivate_LibVEX_alloc_currprivate_LibVEX_alloc_lastprivate_LibVEX_alloc_OOMPPCAMode_RRdopyPPCAModeppPPCAModePPCRH_ImmPPCRH_Reg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IAA5HHcH>DHD$pHCHC DS@HCHD{,HC`Lk8&CXA*!fA H sH5H=@DQ(AAADAE<D fAAADY|DQADiAAAAAAaDYLAAAAADQtAAAH H5H=H dH5H=H yH5H=AADE,DpADAH uH5H=DH=DLH{0AƁ*!DLDHH{PHŋG ;GrHHcȃH,ʉG )HCPSXPH([]A\A]A^A_ÉH=1LH=1DH=1H GH5H=fD8AAACXA,Ms01IW@9 @HT$*!{@H{0HCHHT$Hz1H9LHH=1LH=1DH=12s0HH=1H{PHŋG ;GHHcȃH,ʉG s0HH=1yDLHf{0AŁ*!{@HtILDs0HH=1HHLDYH H5H=Hz19pDLHLHpriv/host_generic_regs.hix <= 0xFFFFFenc == 0priv/host_ppc_isel.c!env->mode64tmp < env->n_vregmap n <= 1024 && (n%16) == 0env->mode64hregClass(r_src) == HRcInt64ety == Ity_F64iselDblExpr(ppc): conste->Iex.Load.ty == Ity_F64hregClass(r) == HRcFlt64hregIsVirtual(r)iselDblExpr_wrk(ppc)ty == Ity_F32e->Iex.Load.ty == Ity_F32iselFltExpr_wrk(ppc)ty == Ity_I8!ri->Prh.Imm.synedmode64ty == e->Iex.CCall.rettyis_sane_RetLoc(rloc)rloc.pri == RLPri_IntaddToSp == 0iselIntExpr_R.const(ppc)ty == Ity_I64ty == Ity_I32sane_AMode(env, am)advance4(ppc,host)iselInt128Expr(ppc64)hregIsVirtual(*rHi)hregIsVirtual(*rLo)hregIsVirtual(ri->Pri.Reg)hregClass(vSrc) == HRcVec128ri->Prh.Imm.syned == synedri->Prh.Imm.imm16 != 0x8000doHelperCall(PPC): invalid IRargreg < PPC_N_REGPARMSarg->tag != Iex_VECRETargreg < PPC_N_REGPARMS-10!hregIsInvalid(r_vecRetAddr)nVECRETs == 1nVECRETs == 0nGSPTRs == 0 || nGSPTRs == 1*stackAdjustAfterCall == 0is_RetLoc_INVALID(*retloc)rloc.pri == RLPri_2Intenv->mode64 == FalseiselInt64Expr(ppc)hregClass(*rHi) == HRcInt32hregClass(*rLo) == HRcInt32iselDfp128Expr(ppc64)ty == Ity_D64e->Iex.Load.ty == Ity_D64shift->tag == Pri_ImmiselDfp64Expr_wrk(ppc)ty == Ity_D32e->Iex.Load.ty == Ity_D32iselDfp32Expr_wrk(ppc)iselCondCode(ppc): CmpXX32iselCondCode(ppc): CmpXX64iselCondCode(ppc)hregIsVirtual(*rMedHi)hregIsVirtual(*rMedLo)ty == Ity_V128e->Iex.Load.ty == Ity_V128iselVecExpr_wrk(ppc)hregClass(r) == HRcVec128ty == Ity_F128iselFp128Expr(ppc64) -- tyRes == Ity_I1d->tmp == IRTemp_INVALIDrloc.pri == RLPri_Nonerloc.pri == RLPri_V128SpReladdToSp >= 16iselStmt(ppc)(hwcaps_host & mask32) == 0(hwcaps_host & mask64) == 0iselBB(ppc): IRTemp type -- PUT(%d) = ; exit-! hregIsInvalid(env->vregmapMedLo[tmp])rc >= HRcInt32 && rc <= HrcLASThregClass(r_dst) == hregClass(r_src)hregClass(r_src) == HRcInt32 || hregClass(r_src) == HRcInt64hregClass(r_srcHi) == HRcInt32hregClass(r_srcLo) == HRcInt32mode->Iex.Const.con->tag == Ico_U32mode->Iex.Const.con->Ico.U32 == 0x8iselDblExpr(ppc): No such tag(%u) iselFltExpr(ppc): No such tag(%u) ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32 || ((ty == Ity_I64) && mode64)ri->Prh.Imm.imm16 >= 1 && ri->Prh.Imm.imm16 <= 31hregClass(ri->Prh.Reg.reg) == HRcGPR(env->mode64)hregIsVirtual(ri->Prh.Reg.reg)iselIntExpr_RH5u: unknown ppc RI tagri->Prh.Imm.imm16 >= 1 && ri->Prh.Imm.imm16 <= 63iselIntExpr_RH6u: unknown ppc64 RI tagvexGetAllocMode() == VexAllocModeTEMPiselIntExpr_R(ppc): cannot reduce treehregClass(r) == HRcGPR(env->mode64)sane_AMode: unknown ppc amode taggenGuestArrayOffset(ppc host)(1)genGuestArrayOffset(ppc host)(2)genGuestArrayOffset(ppc host)(3)genGuestArrayOffset(ppc host)(4)typeOfIRExpr(env->type_env,mode) == Ity_I32typeOfIRExpr(env->type_env, env->previous_rm) == Ity_I32hregClass(r_rmIR) == HRcGPR(env->mode64)typeOfIRExpr(env->type_env,e) == Ity_I128iselInt128Expr(ppc64): No such tag(%u) hregClass(*rHi) == HRcGPR(env->mode64)hregClass(*rLo) == HRcGPR(env->mode64)ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32 || ((ty == Ity_I64) && env->mode64)iselIntExpr_RI.Iex_Const(ppch)hregClass(ri->Pri.Reg) == HRcGPR(env->mode64)iselIntExpr_RI: unknown ppc RI tagty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32iselIntExpr_RH.Iex_Const(ppch)iselIntExpr_RH: unknown ppc RH tagdoHelperCall(PPC): cannot currently handle > 8 argsty == Ity_I32 || ty == Ity_I64typeOfIRExpr(env->type_env,e) == Ity_I64e->Iex.Const.con->tag == Ico_U64!(ty == Ity_I32 || (mode64 && ty == Ity_I64))iselInt64Expr(ppc): No such tag(%u) typeOfIRExpr(env->type_env,e) == Ity_D128ERROR: iselDfp128Expr_wrk, UNKNOWN binop case %d ERROR: iselDfp64Expr_wrk, UNKNOWN unop case %d typeOfIRExpr(env->type_env,e) == Ity_I1iselCondCode(ppc): No such tag(%u) iselInt128Expr_to_32x4_wrk: Binop case 0x%x not found iselInt128Expr_to_32x4_wrk: e->tag 0x%x not found hregClass(*rMedHi) == HRcInt32hregClass(*rMedLo) == HRcInt32e->Iex.Const.con->tag == Ico_V128iselVecExpr(ppc) (subarch = %s): can't reduce iselStmt(ppc): Ist_Exit: dst is not a 32-bit valueiselStmt(ppc64): Ist_Exit: dst is not a 64-bit valuearch_host == VexArchPPC32 || arch_host == VexArchPPC64(archinfo_host->endness == VexEndnessBE) || (archinfo_host->endness == VexEndnessLE)cdst->tag == (env->mode64 ? Ico_U64 :Ico_U32)iselNextiselWordExpr_RH6u_wrkiselWordExpr_RH6uiselWordExpr_RH5u_wrkiselWordExpr_RH5uiselWordExpr_R_wrkiselWordExpr_RiselWordExpr_RH_wrkiselWordExpr_RHiselCondCode_wrkadd_to_splookupIRTempmk_iMOVds_RRlookupIRTempPairdoHelperCalliselDfp128Expr_wrkiselDfp128ExpriselDfp64Expr_wrkiselDfp64Exprmk_AvDuplicateRIisNaniselVecExpr_wrkiselVecExpriselWordExpr_RI_wrkiselWordExpr_RIiselFp128Expr_wrkiselFp128ExpriselDfp32Expr_wrkiselDfp32ExpriselFltExpr_wrkiselFltExprFPU_rounding_mode_isOddiselDblExpr_wrkiselDblExprlookupIRTempQuadiselInt128Expr_to_32x4_wrkiselInt128Expr_to_32x4iselInt128Expr_wrkiselInt128Exprmk_LoadRR32toFPRmk_LoadR64toFPRroundModeIRtoPPC_set_FPU_rounding_modeiselInt64Expr_wrkiselInt64ExprhregClassiselWordExpr_AMode_wrkiselWordExpr_AModeiselStmtmkHRegiselSB_PPCGNUzRx oD\ P 8DD H T%AA^4pjADJ e AAJ O JAF ;\;\(DDJ n IGH St4AAD r AAF ` JAE 4HAAG0V AAG P JAM LGBBA E(J@? (D ABBD ^ (D ABBI 8BBB D(K@ (D BBBI H BBB E(D0H8DPm 8D0A(B BBBK HXXBEE B(D0A8D` 8A0A(B BBBH `BBB E(D0D8D` 8A0A(B BBBE Y 8A0A(B BBBE Db J \$6BBE B(D0A8JCTA 8A0A(B BBBF 8BED D(G0 (A ABBC HBBB E(D0D8GP 8G0A(H BBBI d  BBB E(D0E8JP 8A0A(B BBBG  8J0A(B BBBE HtBBB B(A0A8DP# 8A0A(B BBBE ,BDD b ABA H BBF E(D0G8DP 8D0A(B BBBH H<]DEB E(G0A8DP 8D0A(B BBBI 8BED D(I0 (A ABBD L BBE B(A0A8J 8A0A(B BBBA 1BBB B(A0A8DDOB 8A0A(B BBBG  R[ApR[AL!BBB B(A0A8D 8A0A(B BBBA (oADG V AAD | BEB E(D0A8Dp 8A0A(B BBBE  8A0A(B BBBA I 8A0A(B BBBE Db J @BBE A(D0G@ 0A(A BBBA X BBB B(A0DPB 0A(B BBBH  0A(B BBBH HPBBB B(A0A8D@ 8A0A(B BBBG HBEB E(D0A8D 8A0A(B BBBH `BEB B(D0D8DP 8A0A(B BBBF  8A0A(B BBBH L Db J h BBE B(D0D8D 8A0A(B BBBB  8A0A(B BBBK DOA(DJABBH FBB B(A0A8D`" 8A0A(B BBBA o!p9@R %mX Pj;;@h h S`H (04GE0Un  X[  0 $6 `  @0 IPW1e~`$y ]#k3?XpfeuvopP* C\upPpm s] !" ;T m@X! &4Mf0`0@ 0'@I b {@ '0ERg(Hpi@ &h,T2,8:>DJHP V\bhnvtzPipph8=0 S X g * {" ( . (4 : P@ F L R X ^ d j p 7v ~|  Q p S         x      : P   V  l 8 z  ! ( / 6 6= hD K R Y ` ( g Hn H u _|   v  h     c 9    " U   q 0  h     $     + A Q ` k v              + = L \ n            % 3 C S c q }         -<H[hr~2G^s"=Qd'7GZizpmkHReg__PRETTY_FUNCTION__.3595lookupIRTempQuad.isra.0__PRETTY_FUNCTION__.5463lookupIRTemp.isra.0.part.0__PRETTY_FUNCTION__.5447addInstr.isra.0newVRegF.isra.0newVRegV.isra.0mk_iMOVds_RR__PRETTY_FUNCTION__.3601__PRETTY_FUNCTION__.5644newVRegI.isra.0add_to_sp__PRETTY_FUNCTION__.5650sub_from_spget_sp_aligned16mk_LoadR64toFPR__PRETTY_FUNCTION__.5677mk_LoadRR32toFPR__PRETTY_FUNCTION__.5670iselDblExpriselWordExpr_AMode__PRETTY_FUNCTION__.6677iselCondCode_wrk__PRETTY_FUNCTION__.6669iselWordExpr_R_set_FPU_rounding_modeiselFltExpr_wrk__PRETTY_FUNCTION__.6637iselFp128ExpriselInt64Expr__PRETTY_FUNCTION__.5796__PRETTY_FUNCTION__.6645iselFltExprdoHelperCall.isra.0.constprop.0__PRETTY_FUNCTION__.5860genGuestArrayOffsetp_32to1_then_1Uto8.5858p_LDbe16_then_16Uto32.5997iselWordExpr_RIiselVecExpr__PRETTY_FUNCTION__.5850iselDfp64ExpriselInt128ExpriselWordExpr_RHiselDfp128Expr__PRETTY_FUNCTION__.6328__PRETTY_FUNCTION__.6311__PRETTY_FUNCTION__.6321__PRETTY_FUNCTION__.6338__PRETTY_FUNCTION__.6238__PRETTY_FUNCTION__.6247__PRETTY_FUNCTION__.5780__PRETTY_FUNCTION__.5771__PRETTY_FUNCTION__.6390__PRETTY_FUNCTION__.6399__PRETTY_FUNCTION__.5454__PRETTY_FUNCTION__.6288__PRETTY_FUNCTION__.6297mk_AvDuplicateRI__PRETTY_FUNCTION__.5816isNan__PRETTY_FUNCTION__.5843__PRETTY_FUNCTION__.6260__PRETTY_FUNCTION__.6272__PRETTY_FUNCTION__.5730__PRETTY_FUNCTION__.6455__PRETTY_FUNCTION__.6447iselInt128Expr_to_32x4iselDfp128Expr_wrk__PRETTY_FUNCTION__.6983__PRETTY_FUNCTION__.6991iselDfp64Expr_wrk__PRETTY_FUNCTION__.6897iselDfp32Expr__PRETTY_FUNCTION__.6887__PRETTY_FUNCTION__.6789__PRETTY_FUNCTION__.6781__PRETTY_FUNCTION__.6349__PRETTY_FUNCTION__.6425__PRETTY_FUNCTION__.6435__PRETTY_FUNCTION__.7070__PRETTY_FUNCTION__.7060iselFp128Expr_wrk__PRETTY_FUNCTION__.6811__PRETTY_FUNCTION__.6802iselStmt__PRETTY_FUNCTION__.7508__PRETTY_FUNCTION__.7621__PRETTY_FUNCTION__.7572.LC0.LC1.LC2.LC3.LC4.LC5.LC6.LC7.LC8.LC9.LC10.LC11.LC12.LC13.LC14.LC15.LC24.LC25.LC16.LC17.LC22.LC23.LC19.LC20.LC21.LC18.LC28.LC29.LC26.LC27.LC43.LC42.LC47.LC46.LC39.LC41.LC30.LC44.LC33.LC40.LC35.LC31.LC32.LC34.LC37.LC45.LC38.LC36.LC51.LC48.LC49.LC50.LC53.LC54.LC52.LC55.LC57.LC56.LC58.LC61.LC62.LC59.LC63.LC64.LC65.LC66.LC60.LC70.LC67.LC69.LC71.LC68.LC72.LC73.LC76.LC75.LC77.LC74.LC80.LC82.LC79.LC83.LC87.LC90.LC84.LC86.LC85.LC89.LC88.LC81.LC78.LC96.LC97.LC93.LC94.LC91.LC98.LC95.LC99.LC92.LC101.LC100.LC102.LC107.LC103.LC105.LC104.LC106.LC110.LC108.LC109.LC114.LC115.LC111.LC112.LC113.LC116.LC117.LC118.LC119.LC120.LC121.LC125.LC126.LC122.LC127.LC124.LC123.LC128.LC129.LC130.LC138.LC134.LC132.LC131.LC133.LC135.LC137.LC136.LC140.LC139.LC142.LC141.LC143.LC144.LC145.LC146_GLOBAL_OFFSET_TABLE_vex_assert_failvex_traceflagsppPPCInstrvex_printfaddHInstr_SLOWPPCRH_RegPPCInstr_AluPPCRH_ImmPPCInstr_LIPPCAMode_IRPPCInstr_StorePPCInstr_FpLdSttypeOfIRExprppIRExprvpanicPPCInstr_FpUnaryPPCInstr_FpCMovPPCInstr_FpCftIPPCInstr_FpBinaryPPCInstr_FpRSPPPCInstr_AvLdStPPCInstr_FpMulAccPPCInstr_Fp128UnaryPPCInstr_LoadmatchIRExprPPCInstr_CMovsizeofIRTypePPCInstr_AvUnaryPPCInstr_Dfp64UnaryPPCInstr_UnaryPPCInstr_ShftPPCInstr_Setmk_PPCCondCodeh_calc_DPBtoBCDPPCInstr_Callh_calc_BCDtoDPBvexGetAllocModevexSetAllocModeIRExpr_BinderIRExpr_UnopIRExpr_LoadPPCInstr_ExtractExpD128PPCInstr_DivPPCInstr_DfpD128toD64PPCInstr_CmpPPCInstr_MfCRPPCInstr_MulLPPCInstr_FpSTFIWPPCInstr_Dfp128CmpPPCRI_RegPPCInstr_Dfp64CmpPPCInstr_FpCmpPPCAMode_RRPPCInstr_FpLdFPSCRdopyPPCAModePPCRI_ImmPPCVI5s_ImmPPCInstr_AvSplatPPCInstr_AvBin32x4PPCInstr_AvBin8x16PPCInstr_AvBin16x8IRConst_U32IRExpr_ConstPPCInstr_AvBinaryPPCInstr_AddSubCPPCInstr_DfpQuantize128PPCInstr_Dfp128BinaryPPCInstr_DfpShift128PPCInstr_InsertExpD128PPCInstr_DfpRound128PPCInstr_DfpI64StoD128PPCInstr_Dfp128UnaryPPCInstr_Dfp64BinaryPPCInstr_DfpQuantizePPCInstr_DfpRoundPPCInstr_DfpShiftinvertCondTestPPCInstr_AvUn32Fx4LibVEX_ppVexHwCapsPPCInstr_AvCipherV128UnaryPPCInstr_AvBin32Fx4PPCInstr_AvBin64x2PPCInstr_AvCipherV128BinaryPPCInstr_AvPermPPCInstr_AvBinaryIntPPCInstr_AvBCDV128BinaryPPCInstr_AvHashV128BinaryPPCInstr_AvShPPCInstr_Fp128TrinaryPPCInstr_Fp128BinarytypeOfIRTempppIRStmtPPCInstr_StoreCPPCInstr_MFencePPCInstr_XAssistedPPCInstr_LoadLPPCInstr_XDirectiselSB_PPCprivate_LibVEX_alloc_currprivate_LibVEX_alloc_lastnewHInstrArrayPPCInstr_EvCheckppIRTypeppIRJumpKindPPCInstr_ProfIncPPCInstr_XIndirprivate_LibVEX_alloc_OOM3?_F`KS__fak<bc<bd<be%T1b8dAyf_`+_2`7xd_gdbhdbi7C_J`OfDb&j+EbfJ`s(HOfVxfffHOfVhofvbkd_gbl     ; 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EEtAOvAOAOR ҁ B< % Љ    =AHE8 LuA> xP  _A~P ] x_1EA Љ D Љ@ DH H5H=//H H5H== EB@ BD % p 97EۍAD D A D D EۍAD D A D %D H H5H=H H5H=H H5H=H H5H=} ]}A]DA A@D } ]}A]}A]DDAE ADD ƒ@ J]}A\DA A@% D #2$  `Q  @ S  Q‰ %@ Љʃ @ S‰ %@ Љʃ CU DHXH‹ED 0/HBH)vH)nH H5H=\ ~w\D$i\D[\D,M\D$H H5H= \D,g\s EB@ BD % p H  H5H=[ /LuA~Eq[D<HEx1YDDA> AA}AunEtAvvAvAvm1  DƁ   EEtENAvAENENADC< 6 qEAF<6 闿AEtAOvAOAOrL YDL$L$DD$ R *YD4eWǃ/}X} A'XDA A  D оHE1pY(EAD D D  D % lHE1VA~V}L$VL$1E1A@ƍ<0dE D  B  ‰%  ԽOVADVHE1}W} AVDA A  D @ uUADAUD  D D$D @  FVA9VAD})V} AVA %D @ @ ƼUAB C,6D D  D @  C4  B  D  D@  ʁ STADATD  ЉD  D$D  P  鹻‰ %@ Љʃ 酻H H5H=H H5H=H H5H=H ) H5H=H H5H=H H5H=H rH5H=H H5H=H H5H=H H5H=H H5H=H X H5H=EtA~vA~A~t?|H sH5H=H H5H=H H5H=AFz<tT,H 2 H5H=H H5H=H tH5H=S H  H5H=H  H5H=PH H5H=H H5H=H >H5H=H <H5H=H -H5H=H +H5H=H H5H=H H5H=H G H5H=H F H5H=H H5H=H I H5H=H H5H=H H5H=H V H5H= E1 E1UH H5H=NH H5H=H LH5H=H H5H=H H5H=fDHlH5?։ ;0t H 4H5H=@ @;Pux= 0 && rD <= 14priv/host_generic_regs.h0hregClass(r) == HRcInt32!hregIsVirtual(r)n <= 15hregClass(r) == HRcFlt64n <= 31hregClass(r) == HRcFlt32hregClass(r) == HRcVec1286432816showARMNeonDataSizerD <= 12am->tag == ARMam1_RIsimm12 >= 0 && simm12 <= 4095r >= 0 && r < 16r%dr >= 0 && r < 32d%ds%dq%dppHRegARMnveqhslomiplvsvchilsgeltgtlealneshowARMCondCode0 <= shift && shift <= 3%d()(,,%u)-255 <= simm9 && simm9 <= 2550 == (simm11 & 3)[], imm8 >= 0 && imm8 <= 255imm4 >= 0 && imm4 <= 15sh >= 0 && sh < 320x%ximm5 > 0 && imm5 <= 31%uARMNImm_to_Imm640x%llX%llX[%u]xoraddadcsubsubssbcandbicorraddsshowARMAluOpshrsarshlshowARMShiftOpnotclznegshowARMUnaryOpumullsmullmulshowARMMulOpdivshowARMVfpOpcpyabssqrtshowARMVfpUnaryOp??invalid??vceqveorvaddvrhaddvextvandvpaddvabdvsubvrecpsvminvtblvqdmullvmaxvqrdmulhvqdmulhvqaddvqsubvpminvcgtvmulvpmaxvmullvcgevmulivorrshowARMNeonBinOp.f.u.s.p.ishowARMNeonBinOpDataTypevabsvrsqrtevrsqrtefpvabsfpvrecipvqmovunvmovvmvnvcntvclsvclzvdupvpaddlvnegvqshlvrecipfvqshluvrev16vrev32vrev64vcvtvqmovnshowARMNeonUnOp.f16.f32.u32.f32.s32.f32.f32.u32.f32.s32.f32.f16showARMNeonUnOpDataTypeshowARMNeonUnarySOpvshlshowARMNeonShiftOpshowARMNeonShiftOpDataTypevzipvuzpvtrnshowARMNeonDualOpicc != ARMcc_NVcond != ARMcc_ALis_sane_RetLoc(rloc)amt >= 1 && amt <= 63cmptst ldrshldrhfastslowbhdr3:dssdfsitodftosidfuitodftouidf64f32vmaxnmvminnm%-4s %s mov imm , 0x%xldr%s str%s %s%s%sstrh%s ldrb%s strb%s ldrsb%s (xDirect) if (%%cpsr.%s) { movw r12,0x%x; movt r12,0x%x; str r12,blx r12 }(xIndir) str (xAssisted) mov%s call%s 0x%x [nArgRegs=%d, %-5s r0, r2, r3r1:r0, r2, r3ldrex%s %sr2, [r4]strex%s r0, %sr2, [r4]fldd fstd flds fsts f%-3sd f%-3ss fcmpd ; fmstatfcpyd%s fcpys%s fcvt%s vmov -lo64, ; vmov -hi64, -lo64-hi64vmov %s vrintr.%s.%s %s.%s fmxr fpscr, fmrx , fpscr(mfence) dsb sy; dmb sy; isbclrexvld1.32 {vst1.32 {} %s%s%s , #0, #%uvshl.i64 vmov%s add32 (evCheck) ldr r12,; subs r12,r12,$1; str r12,; bpl nofail; ldr r12,; bx r12; nofail:ppARMInstr(1)mode64 == FalseaddRegUsage_ARMRI84addRegUsage_ARMRI5addRegUsage_ARMAmode1addRegUsage_ARMAmode2getRegUsage_ARM:Call:regparmsgetRegUsage_ARMInstrmapRegs_ARMRI84mapRegs_ARMRI5mapRegs_ARMAmode1mapRegs_ARMAmode2mapRegs_ARMInstroffsetB >= 0!hregIsVirtual(rreg)offsetB <= 40950 == (offsetB & 3)offsetB <= 1020nbuf >= 320 == (((HWord)buf) & 3)imm5 >= 1 && imm5 <= 31simm8 >= 0 && simm8 <= 255!(bL == 0 && bS == 1)delta > 0 && delta < 40(delta & 3) == 0notCond <= 13disp_cp_xindir != NULL0 == (off8 & 3)0 == (off8 & 0xFFFFFF00)cc < 16 && cc != ARMcc_ALqDhi != dHi && qDhi != dLoqDlo != dHi && qDlo != dLosz1 + sz2 < 2ARMin_NeonImmregD != regN!(*is_profInc)emit_ARMInstr((UChar*)p) - &buf[0] <= 32endness_host == VexEndnessLE0 == (3 & (HWord)p)p[2] == 0xE12FFF3C0 == (delta & (Long)3)uimm24 == simm24validsizeof(ULong*) == 4rc >= HRcInt32 && rc <= HrcLAST0 == (ri->ARMri84.I84.imm4 & ~0x0F)0 == (ri->ARMri84.I84.imm8 & ~0xFF)-4095 <= simm13 && simm13 <= 4095simm11 >= -1020 && simm11 <= 1020szB == 8 || szB == 4 || szB == 2 || szB == 1; movw r12,LO16($disp_cp_chain_me_to_%sEP); movt r12,HI16($disp_cp_chain_me_to_%sEP); ; movw r12,LO16($disp_cp_xindir); movt r12,HI16($disp_cp_xindir); movw r8,$IRJumpKind_to_TRCVAL(%d); movw r12,LO16($disp_cp_xassisted); movt r12,HI16($disp_cp_xassisted); (profInc) movw r12,LO16($NotKnownYet); movw r12,HI16($NotKnownYet); ldr r11,[r12]; adds r11,r11,$1; str r11,[r12]; ldr r11,[r12+4]; adc r11,r11,$0; str r11,[r12+4]ppARMInstr: unhandled case (tag %d)genSpill_ARM: unimplemented regclassgenReload_ARM: unimplemented regclassgenMove_ARM: unimplemented regclassdisp_cp_chain_me_to_slowEP != NULLdisp_cp_chain_me_to_fastEP != NULLi->ARMin.XDirect.cond != ARMcc_NVi->ARMin.XIndir.cond != ARMcc_NVi->ARMin.XAssisted.cond != ARMcc_NVemit_ARMInstr.ARMin_XAssisted: unexpected jump kindhregClass(regDreg) == HRcFlt64hregClass(regMreg) == HRcFlt64cc < 16 && cc != ARMcc_AL && cc != ARMcc_NVevCheckSzB_ARM() == (UChar*)p - (UChar*)p0is_imm32_to_ireg_EXACTLY2( p, 12, (UInt)(Addr)disp_cp_chain_me_EXPECTED)  patchProfInc_ARMunchainXDirect_ARMis_imm32_to_ireg_EXACTLY2chainXDirect_ARMimm32_to_ireg_EXACTLY2do_load_or_store32imm32_to_iregiregEncqregEncdregEncfregEncskeletal_RI84skeletal_RI5emit_ARMInstrgenReload_ARMgenSpill_ARMmapRegs_ARMInstrgetRegUsage_ARMInstrppARMInstrARMInstr_NShl64ARMInstr_NCMovQARMInstr_VCMovSARMInstr_VCMovDARMInstr_StrEXARMInstr_LdrEXARMInstr_CallARMInstr_CMovARMInstr_Ld8SARMInstr_LdSt8UARMInstr_LdSt16ARMInstr_LdSt32ppARMRI5ARMRI5_I5ROR32ppARMRI84ARMRI84_I84mkARMAModeVppARMAMode2ARMAMode2_RIppARMAMode1ARMAMode1_RRSARMAMode1_RIhregClassppHRegARMGNUzRx sT4%AA^P%AA^lFh B Jh F Jh F Fh B $LDJ B y G u K D D  Dk A <\,XRF H gQ^ J Z F %lHy G dHs E EH K c E lHy G 2m,EE F LHx H 4hEu F r N O I i O i G 2m/jOEm F RHz F /j8Hg I b F c M ^ J D L ^ E TdHp H p/j0O\]g I ^ J D L Z E +faU+&UI.i (Em N { E LdHTL|HTLHTLUIUIy $<HUSTUIl@iOPyOX]S$X9t9t5p7r3n,2m@lHx H \lH{ E xlHx H dHt D 9t6q9tdHt D HF B p A ,/j@lHp H \lHp H x7r7r8s8s5p5p2mdHs E  dHs E <6qP9td9tx6q:u6q>y3n,g,g 7r 7r, <w@ >yT <wh @{| 3n dHs E  @{ dHv B   4o ,g UFBA A(D0 (A ABBG K (C ABBE b (A ABBH  (C ABBL l (A ABBF  (C ABBJ  (A ABBM 4 FAD | ABF  ABF P PFAA m ABH Z ABC h ABE C ABJ ,X FAA  ABH , FAA  ABH , Kk J K E M C r F H KFBB B(A0A8DP 8A0A(B BBBE 4 H >H/ I y G l H K  IEAKs (%9@ R%p  ( P0   L!4 M[8 t PP 0    % > W p      p ` 8P Q@ j0        2 Kx dh }X  ( H   p 4P MRW)\aBfDk]pouwz  HQU8M<'Ycf ilo!r'u-x3{9~?EKQW]pciou{F3Kbev #)/5;AGMSY_ekqw)}!%.wL|[VlrQ !(@.5<bCgJQX_fmt{gsIS!)3y:nNXb]   A  # * 1 8 ? F M T  [ b 3i ]p Sw X~ N o q     6 J  0              & x- p4 ; B I P W ^ e l s z b T [ 4 ; -   ' z    s k a [ M P     " ) 0 7 > E PL xS {Z a h o v }    r  =   `       * B     @      % i, I3 : A H O iV W] d Vk r  y - a   C  v           8  *    `   !  ( (/ `6  = { D K Z R Y `` u g n u |       n 7  B R        &     "29M`| ` % ldpl)26BPNZ2i /wPO@/pd/0+@a+U@ .p 0"#H$P#H3#H@#UMP$U_$p& '()H)UP*@*P *X@+$5p+9B+9Q+5`0,7rp,3,2,l`-l-l@.d.9.60/9p/d/p0/)0l81lG17W17g28v@28252532@3d3d 46`494946 5:&`5665>J53Y 6,iP6,x67677<@7>7<7@83@8d8@ 8d`9):4:P:,K:UV_StZP ^ b fgKP `>PIimm32_to_ireg__PRETTY_FUNCTION__.6007hregClass.part.0__PRETTY_FUNCTION__.3585imm32_to_ireg_EXACTLY2.part.0__PRETTY_FUNCTION__.6022iregEnc__PRETTY_FUNCTION__.5974dregEnc__PRETTY_FUNCTION__.5979fregEnc__PRETTY_FUNCTION__.5984qregEnc__PRETTY_FUNCTION__.5989showARMNeonDataSizedo_load_or_store32__PRETTY_FUNCTION__.6039skeletal_RI84__PRETTY_FUNCTION__.5994rRegUniverse_ARM_initted.4832rRegUniverse_ARM.4831__PRETTY_FUNCTION__.4839__PRETTY_FUNCTION__.4869__PRETTY_FUNCTION__.4876__PRETTY_FUNCTION__.4884__PRETTY_FUNCTION__.4904__PRETTY_FUNCTION__.4917__PRETTY_FUNCTION__.4937__PRETTY_FUNCTION__.4979__PRETTY_FUNCTION__.4973__PRETTY_FUNCTION__.4991__PRETTY_FUNCTION__.5010__PRETTY_FUNCTION__.5022__PRETTY_FUNCTION__.5434__PRETTY_FUNCTION__.5443__PRETTY_FUNCTION__.5451__PRETTY_FUNCTION__.5458__PRETTY_FUNCTION__.5485__PRETTY_FUNCTION__.5493__PRETTY_FUNCTION__.5502__PRETTY_FUNCTION__.5507__PRETTY_FUNCTION__.5557__PRETTY_FUNCTION__.5564__PRETTY_FUNCTION__.5681__PRETTY_FUNCTION__.5697__PRETTY_FUNCTION__.5752__PRETTY_FUNCTION__.5804__PRETTY_FUNCTION__.5868__PRETTY_FUNCTION__.5928__PRETTY_FUNCTION__.5948__PRETTY_FUNCTION__.6058CSWTCH.480CSWTCH.483CSWTCH.481CSWTCH.482__PRETTY_FUNCTION__.6000__PRETTY_FUNCTION__.6609shortCTR.6613__PRETTY_FUNCTION__.6032__PRETTY_FUNCTION__.6624__PRETTY_FUNCTION__.6634.LC0.LC1.LC2.LC3.LC4.LC5.LC6.LC7.LC8.LC9.LC10.LC11.LC15.LC16.LC12.LC13.LC14.LC17.LC18.LC19.LC20.LC21.LC22.LC27.LC28.LC24.LC26.LC25.LC23.LC29.LC44.LC30.LC31.LC45.LC32.LC33.LC34.LC35.LC36.LC37.LC38.LC39.LC40.LC41.LC42.LC43.LC46.LC47.LC48.LC51.LC52.LC53.LC49.LC50.LC54.LC55.LC56.LC57.LC58.LC59.LC60.LC61.LC63.LC62.LC64.LC65.LC66.LC67.LC68.LC77.LC69.LC70.LC78.LC71.LC72.LC73.LC74.LC75.LC76.LC79.LC83.LC81.LC82.LC80.LC87.LC85.LC86.LC84.LC91.LC89.LC90.LC88.LC92.LC93.LC96.LC94.LC95.LC97.LC118.LC119.LC117.LC120.LC112.LC109.LC107.LC99.LC122.LC116.LC115.LC108.LC102.LC101.LC105.LC121.LC106.LC100.LC124.LC113.LC111.LC110.LC98.LC114.LC123.LC103.LC104.LC125.LC127.LC126.LC128.LC130.LC129.LC131.LC152.LC144.LC146.LC153.LC138.LC140.LC148.LC133.LC134.LC135.LC147.LC136.LC145.LC139.LC141.LC143.LC142.LC132.LC151.LC150.LC149.LC137.LC154.LC156.LC157.LC158.LC159.LC160.LC155.LC161.LC162.LC164.LC163.LC165.LC169.LC167.LC168.LC166.LC170.LC171.LC172.LC173.LC174.LC175.LC260.LC262.LC273.LC259.LC251.LC245.LC246.LC247.LC248.LC195.LC194.LC196.LC197.LC254.LC242.LC240.LC241.LC239.LC238.LC188.LC189.LC244.LC243.LC258.LC255.LC190.LC192.LC252.LC253.LC236.LC234.LC235.LC201.LC202.LC200.LC176.LC177.LC199.LC269.LC270.LC271.LC272.LC268.LC267.LC266.LC265.LC263.LC205.LC178.LC226.LC222.LC211.LC219.LC223.LC224.LC225.LC217.LC218.LC220.LC221.LC210.LC212.LC213.LC214.LC183.LC182.LC215.LC216.LC209.LC184.LC233.LC179.LC180.LC207.LC229.LC230.LC231.LC227.LC228.LC232.LC203.LC274.LC275.LC198.LC261.LC185.LC186.LC187.LC256.LC257.LC237.LC204.LC249.LC250.LC191.LC193.LC208.LC206.LC181.LC264.LC276.LC278.LC280.LC282.LC279.LC277.LC281.LC285.LC283.LC286.LC284.LC287.LC288.LC289.LC290.LC291.LC292.LC293.LC294.LC295.LC296.LC297.LC325.LC322.LC319.LC306.LC324.LC310.LC301.LC307.LC323.LC302.LC299.LC309.LC317.LC300.LC320.LC308.LC303.LC318.LC304.LC305.LC312.LC311.LC313.LC321.LC315.LC314.LC298.LC316.LC331.LC326.LC327.LC328.LC329.LC330.LC332.LC333arm_hwcaps_GLOBAL_OFFSET_TABLE_vex_assert_failvpanicgetRRegUniverse_ARMRRegUniverse__initRRegUniverse__check_is_saneppHRegARMvex_printfppHRegshowARMCondCodeARMAMode1_RIprivate_LibVEX_alloc_currprivate_LibVEX_alloc_lastprivate_LibVEX_alloc_OOMARMAMode1_RRSppARMAMode1ARMAMode2_RIARMAMode2_RRppARMAMode2mkARMAModeVppARMAModeVmkARMAModeN_RRmkARMAModeN_RppARMAModeNARMRI84_I84ARMRI84_RppARMRI84ARMRI5_I5ARMRI5_RppARMRI5ARMNImm_TIARMNImm_to_Imm64Imm64_to_ARMNImmppARMNImmmkARMNRSppARMNRSshowARMAluOpshowARMShiftOpshowARMUnaryOpshowARMMulOpshowARMVfpOpshowARMVfpUnaryOpshowARMNeonBinOpshowARMNeonBinOpDataTypeshowARMNeonUnOpshowARMNeonUnOpDataTypeshowARMNeonUnOpSshowARMNeonUnOpSDataTypeshowARMNeonShiftOpshowARMNeonShiftOpDataTypeshowARMNeonDualOpshowARMNeonDualOpDataTypeARMInstr_AluARMInstr_ShiftARMInstr_UnaryARMInstr_CmpOrTstARMInstr_MovARMInstr_Imm32ARMInstr_LdSt32ARMInstr_LdSt16ARMInstr_LdSt8UARMInstr_Ld8SARMInstr_XDirectARMInstr_XIndirARMInstr_XAssistedARMInstr_CMovARMInstr_CallARMInstr_MulARMInstr_LdrEXARMInstr_StrEXARMInstr_VLdStDARMInstr_VLdStSARMInstr_VAluDARMInstr_VAluSARMInstr_VUnaryDARMInstr_VUnarySARMInstr_VCmpDARMInstr_VCMovDARMInstr_VCMovSARMInstr_VCvtSDARMInstr_VXferQARMInstr_VXferDARMInstr_VXferSARMInstr_VCvtIDARMInstr_VRIntRARMInstr_VMinMaxNumARMInstr_FPSCRARMInstr_MFenceARMInstr_CLREXARMInstr_NLdStQARMInstr_NLdStDARMInstr_NUnaryARMInstr_NUnarySARMInstr_NDualARMInstr_NBinaryARMInstr_NeonImmARMInstr_NCMovQARMInstr_NShiftARMInstr_NShl64ARMInstr_Add32ARMInstr_EvCheckARMInstr_ProfIncppARMInstrppRetLocgetRegUsage_ARMInstraddHRegUsemapRegs_ARMInstrlookupHRegRemapgenSpill_ARMppHRegClassgenReload_ARMgenMove_ARMemit_ARMInstrppIRJumpKindevCheckSzB_ARMunchainXDirect_ARMpatchProfInc_ARM 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H5H=H Q H5H=H H5H=H U H5H=H 6 H5H=H j H5H=H S H5H=H " H5H=H H5H=H=H=H H5H=H z H5H=H H5H=H H5H=ff.fDHuPI@ugHLI ]tuAy ?L\AA LHf.H H5H=H H5H=H H5H=H H5H=HuPI@ugHLI)\tuAy L[AA ?LHf.H H5H=H H5H=H H5H=H H5H=HupI@HfUUuUeLI>[Ay(@AyAy(LZHLH H5H=H H5H=H H5H=H H5H=H H5H=H H5H=nveqcsccmiplvsvchilsgeltgtlealneshowARM64CondCodepriv/host_arm64_defs.cf3 < (1<<1)f4 < (1<<6)f5 < (1<<6)f6 < (1<<5)f7 < (1<<5)f5 < (1<<5)f4 < (1<<12)f2 < (1<<8)f3 < (1<<5)f3 < (1<<8)priv/host_generic_regs.hhregClass(r) == HRcInt64!hregIsVirtual(r)n <= 30hregClass(r) == HRcFlt64n <= 31hregClass(r) == HRcVec128r >= 0 && r < 31x%dr >= 0 && r < 32d%dq%dppHRegARM64%d()%u((,0i < 4wD <= 30-256 <= simm9 && simm9 <= 255scale == 4do_load_or_store32xD <= 30scale == 8do_load_or_store64(S-reg)uimm12 >= 0 && uimm12 <= 4095imm12 < 4096shift == 0 || shift == 12bitN < 2immR < 64immS < 64imm6 > 0 && imm6 < 64hregClass(src) == HRcInt64hregClass(dst) == HRcInt64is_sane_RetLoc(rloc)-4096 < simm && simm < 40960 == (simm & 0xF)armRM <= 3amt >= minSh && amt <= maxShamtB >= 1 && amtB <= 15laneNo <= 1hregClass(src) == HRcVec128hregClass(dst) == HRcVec128hregClass(src) == HRcFlt64hregClass(dst) == HRcFlt64ARM64Instr_VMovaddsub (w)orreorandlsrasrlslnotclznegfastslow umulhsmulhmul b hs2dd2sh2ss2hh2dd2hrecpxneg sqrt rintiabs muldiv4sfrsqrts2dadd 8h16bsub mul fadd fsub fmul fdiv fmax fmin umax umin smax smin and orr eor cmeq cmhi cmgt fcmeq fcmge fcmgt tbl uzp1 uzp2 zip1 zip2 pmul 8hbbpmull 2dssumull 4shhsmull sqadd uqadd sqsub uqsub sqdmullsqdmulhsqrdmulhsqshl uqshl sqrshluqrshlsshl ushl srshl urshl frecpsusqaddsuqaddfsqrtfneg fabs allnot cls clz cnt rbit rev16rev32rev64urecpeursqrtefrecpefrsqrtesqxtn uqxtn xtn sqxtun??sqshluushr sshr shl 2sdsqshrn4hs8bhuqshrnsqshrunsqrshrnuqrshrnsqrshrun%s , #%ucmp%s showARM64LogicOp#nrs(%u,%u,%u)tst showARM64ShiftOpshowARM64UnaryOpmov imm64 , 0x%llxldr str ldruw strw ldruh strh ldrub strb (xDirect) if (%%pstate.%s) { imm64 x9,0x%llx; str x9,blr x9 }(xIndir) str ; imm64 x9,$disp_cp_xindir; br x9 }(xAssisted) imm64 x9,$disp_cp_xassisted; csel , %scall%s 0x%llx [nArgRegs=%d, ]%s xsp, xsp, #%d, xspshowARM64MulOp%s ldxr%s %c2, [x4]stxr%s w0, %c2, [x4]x1 = cas(%dbit)(x3, x5 -> x7)(mfence) dsb sy; dmb sy; isbclrex #15(H-reg), %u(), ld1.2d {st1.2d {}, [characteriseARM64CvtOp%ccvtf (%c-reg)(%c-reg), fcvt%s showARM64FpUnaryOpf%s showARM64FpBinOpf%s fcmp fcsel msr fpcr, mrs , fpcrmsr fpsr, , fpsrshowARM64VecBinOp%s .%s, .%sshowARM64VecModifyOpshowARM64VecUnaryOp8b4h2sshowARM64VecNarrowOpshowARM64VecShiftImmOp.%s, #%uext .16b, .16b, #%uqimm , Bits16toBytes16(0x%x)fmov .d[0], qFromXX .d[%u]mov(%c) (evCheck) ldr w9,; subs w9,w9,$1; str w9,; bpl nofail; ldr x9,; br x9; nofail:ppARM64Instr(1)fcvt%c%c npmzmode64 == TrueaddRegUsage_ARM64RIAaddRegUsage_ARM64RILaddRegUsage_ARM64RI6addRegUsage_ARM64AmodegetRegUsage_ARM64InstrmapRegs_ARM64RIAmapRegs_ARM64RILmapRegs_ARM64RI6mapRegs_ARM64AmodemapRegs_ARM64InstroffsetB >= 0!hregIsVirtual(rreg)0 == (offsetB & 7)offsetB < 40960 == (offsetB & 15)nbuf >= 320 == (((HWord)buf) & 3)opc != 0rM < 31rD < 31sh > 0 && sh < 64scale == 2xN <= 30do_load_or_store16scale == 1do_load_or_store8delta > 0 && delta <= 40(delta & 3) == 0notCond <= 13ptmp != NULLdelta > 0 && delta < 40dist >= 2 && dist <= 5f4 < (1<<4)ptmp == NULL0 == (simm12 & 0xF)hD < 32sD < 32dD < 32rQ < 32cond < 16dszBlg2 >= 0 && dszBlg2 <= 2imm4 >= 1 && imm4 <= 15xx < 31xhi < 31 && xlo < 31laneNo < 2dd < 31!(*is_profInc)emit_ARM64Instr((UChar*)p) - &buf[0] <= 40endness_host == VexEndnessLE0 == (3 & (HWord)p)p[4] == 0xD63F0120p[4] == 0xD61F0120p[4] == 0xF9400128p[5] == 0x91000508p[6] == 0xF9000128s???d???????q@ @ ?@ @ @ @ @ @ ???patchProfInc_ARM64unchainXDirect_ARM64chainXDirect_ARM64do_load_or_store64do_load_or_store32X_3_8_5_6_5_5dregEncqregEnciregEncX_2_6_2_12_5_5X_3_6_7_6_5_5X_3_5_8_6_5_5X_8_19_1_4X_3_6_2_16_5imm64_to_iregdo_load_or_store8X_2_6_3_9_2_5_5do_load_or_store16X_3_6_1_6_6_5_5emit_ARM64InstrgenReload_ARM64genSpill_ARM64mapRegs_ARM64InstrgetRegUsage_ARM64InstrppARM64AModeppARM64RI6ppARM64RILppARM64RIAppARM64InstrARM64Instr_VMovARM64Instr_VXfromQARM64Instr_VImmQARM64Instr_VExtVARM64Instr_VShiftImmVARM64Instr_VNarrowVARM64Instr_VCvtF2IARM64Instr_VLdStDARM64Instr_VLdStSARM64Instr_VLdStHARM64Instr_CASARM64Instr_StrEXARM64Instr_LdrEXARM64Instr_AddToSPARM64Instr_CallARM64Instr_MovIARM64RI6_I6ARM64RIL_I13ARM64RIA_I12ARM64AMode_RI12ARM64AMode_RI9hregClassppHRegARM64rc >= HRcInt32 && rc <= HrcLASTszB == 8 || szB == 4 || szB == 2 || szB == 1uimm12 < 8192 && 0 == (uimm12 & 1)uimm12 < 16384 && 0 == (uimm12 & 3)uimm12 < 32768 && 0 == (uimm12 & 7)dszBlg2 == 0 || dszBlg2 == 1 || dszBlg2 == 2; imm64-exactly4 x9,$disp_cp_chain_me_to_%sEP; ; movw x21,$IRJumpKind_to_TRCVAL(%d); (profInc) imm64-fixed4 x9,$NotKnownYet; ldr x8,[x9]; add x8,x8,#1, str x8,[x9]ppARM64Instr: unhandled case (tag %d)getRegUsage_ARM64:Call:regparmsoffsetB >= 0 && offsetB < 32768genSpill_ARM: unimplemented regclassgenReload_ARM: unimplemented regclassgenMove_ARM64: unimplemented regclassdisp_cp_chain_me_to_slowEP != NULLdisp_cp_chain_me_to_fastEP != NULLi->ARM64in.XDirect.cond != ARM64cc_NVemit_ARM64Instr.ARM64in_XAssisted: unexpected jump kinddd < 31 && nn < 31 && mm < 31 && cond < 16-4096 < simm12 && simm12 < 4096evCheckSzB_ARM64() == (UChar*)p - (UChar*)p0is_imm64_to_ireg_EXACTLY4( p, 9, (Addr)disp_cp_chain_me_EXPECTED)is_imm64_to_ireg_EXACTLY4( p, 9, (Addr)place_to_jump_to_EXPECTED)is_imm64_to_ireg_EXACTLY4(p, 9, 0x6555755585559566ULL)GNUzRx %4DP D PDU _ lD] _ Dm _ DZ b Fh B Fh B Fh B V([$<?RL J ^ J ^RdA_ H OD  A z E D F D A _Em F \lHy G 8Hl D T2mhH I /jHE C /jdHp H /j9t 6q 9t43nH9t\5ppHU C 3n7r7r7r7r:u6q9t,8s @HG A p A dH{ E /j8slHp H lHp H lHp H ,g,g$tH I @tH I \tH I x6q5pdHv B 6q6q6q5p 5p 8s48sH2m\2mp<w3n3n8s5p5pdHv B HZ F  lHy G <Hz F I A `2mt2m5pdHs E 5p`Hn J 4o,g'EAD`v CAL F AAH P CAL  AAK  CAI  AAK  AAK S AAK s AAK  CAJ   CAJ  AAH  AAF 2 AAE PGFAA e DBM W DBK [ IBJ q ABD P@ yFAA H ABE h ABE Z ABK  ABD ( SH H R F  E ( SH H R F  E dKL I N B  UCFBB B(A0A8DP 8A0A(B BBBE  8F0A(B BBBB  XP`PXAPT3XK`_XBPFXP`PXBP  HM K  HM K  ?Hm K %0#<0J` crP P( @p  H '8 @@H@ dVaP[ x  O    2 K^ w@_ P  % >WppP08`Q` *\ *g@    ! : S`l@0        + D ] v  *-  !$'0B Yeq"}(.4:@FLRX^dj7p?v|jYnH;b ku$*06< BPHxNTZ`f6lNrxZ~v      ; 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&AF1~fIFHH4HA9nEn$Ef In} A$;A$HHcH>HHfPjCD`DHƺH{0HŋG ;G HHcȃH,ʉG HC0S8PH[]A\A]A^A_DH=1HH=1DH=1H H5H=fDHH=1fLuA>D_{ II~1H;{(HDH=1HH=1DH=1H{0HŋG ;G#HHcȃH,ʉG HH=1HHdPuwyTD^{ Ht, HH=1HH H5H=H H5H=H H5H=HHHHcPwu\LH H5H=priv/host_generic_regs.hix <= 0xFFFFFenc == 0priv/host_arm64_isel.ctmp < env->n_vregmap off < (1 << 12)off < (4 << 12)(off & 3) == 0off < (8 << 12)(off & 7) == 0off < (2 << 12)(off & 1) == 0off < (1<<12)con->tag == Ico_U64ri->ARM64riL.I13.bitN < 2ri->ARM64riL.I13.immR < 64ri->ARM64riL.I13.immS < 64arg1con->tag == Ico_U32ehregClass(r) == HRcInt64hregIsVirtual(r)iselInt128Expr(arm64)hregClass(*rHi) == HRcInt64hregIsVirtual(*rHi)hregClass(*rLo) == HRcInt64hregIsVirtual(*rLo)cc != ARM64cc_NV0onety == e->Iex.CCall.rettyis_sane_RetLoc(rloc)rloc.pri == RLPri_IntaddToSp == 0ty == Ity_I64 || ty == Ity_I8ri->ARM64ri6.I6.imm6 < 64ri->ARM64ri6.I6.imm6 > 0ri->ARM64riA.I12.imm12 < 4096ril_one && ril_twoty == Ity_V128ril_onehregClass(r) == HRcVec128iselV128Expr_wrkty == Ity_V256iselV256Expr_wrkhregClass(*rHi) == HRcVec128hregClass(*rLo) == HRcVec128ty == Ity_I64sane_AMode(am)iselCondCode(arm64): CmpXX64iselCondCode(arm64): CmpXX32iselCondCode(arm64): CmpXX16iselCondCode(arm64): CmpXX8iselCondCodenGSPTRs == 0 || nGSPTRs == 1retTy != Ity_V256nVECRETs == 0!hregIsInvalid(r_vecRetAddr)!(hregIsInvalid(tmpregs[i]))*stackAdjustAfterCall == 0is_RetLoc_INVALID(*retloc)ty == Ity_F64e->Iex.Load.ty == Ity_F64hregClass(r) == HRcFlt64iselDblExpr_wrkty == Ity_F32e->Iex.Load.ty == Ity_F32iselFltExpr_wrkty == Ity_F16iselF16Expr_wrk -- d->tmp == IRTemp_INVALIDrloc.pri == RLPri_Nonerloc.pri == RLPri_V128SpRelrloc.spOff < 256addToSp >= 16addToSp < 256ty == Ity_I1cas->expdHi == NULLcas->dataHi == NULLiselStmtarch_host == VexArchARM64iselBB(arm64): IRTemp type -- PUT(%d) = ; exit-cdst->tag == Ico_U64n < 2 && imm_s < 64 && imm_r < 64ty == Ity_I64 || ty == Ity_I32 || ty == Ity_I16 || ty == Ity_I8ty == Ity_I64 || ty == Ity_I32e->Iex.Const.con->tag == Ico_U64e->Iex.Const.con->tag == Ico_U32rc >= HRcInt32 && rc <= HrcLASThregClass(ri->ARM64riL.R.reg) == HRcInt64hregIsVirtual(ri->ARM64riL.R.reg)iselIntExpr_RIL: unknown arm RIL tagtypeOfIRExpr(env->type_env,e) == Ity_I128iselIntExpr_R.Iex_Const(arm64)iselIntExpr_R: cannot reduce treehregClass(ri->ARM64ri6.R.reg) == HRcInt64hregIsVirtual(ri->ARM64ri6.R.reg)iselIntExpr_RI6: unknown arm RI6 tagiselIntExpr_RIA.Iex_Const(arm64)ri->ARM64riA.I12.shift == 0 || ri->ARM64riA.I12.shift == 12hregClass(ri->ARM64riA.R.reg) == HRcInt64hregIsVirtual(ri->ARM64riA.R.reg)iselIntExpr_RIA: unknown arm RIA tagtypeOfIRExpr(env->type_env,mode) == Ity_I32typeOfIRExpr(env->type_env, env->previous_rm) == Ity_I32e->Iex.Const.con->tag == Ico_V128! hregIsInvalid(env->vregmapHI[tmp])sane_AMode: unknown ARM64 AMode1 tagtypeOfIRExpr(env->type_env,e) == Ity_I1retTy == Ity_V128 || retTy == Ity_V256retTy != Ity_V128 && retTy != Ity_V256nVECRETs == ((retTy == Ity_V128 || retTy == Ity_V256) ? 1 : 0)isel_arm: Ist_Exit: dst is not a 64-bit valuearchinfo_host->endness == VexEndnessLE @ @ @ @ @ @/.-,3210iselNextiselInt128Expr_wrkiselInt128ExpriselIntExpr_RI6_wrkiselIntExpr_RI6iselIntExpr_RIL_wrkiselIntExpr_RILisZeroU64iselIntExpr_R_wrkiselIntExpr_Rmk_baseblock_64bit_access_amodeiselIntExpr_RIA_wrkiselIntExpr_RIAiselCondCode_wrkiselCondCodelookupIRTempmb_mkARM64RIL_IdoHelperCalllookupIRTempPairiselV256Expr_wrkiselV256ExpriselV128Expr_wrkiselV128ExpriselF16Expr_wrkiselF16ExpriselFltExpr_wrkiselFltExprset_FPCR_rounding_modeiselDblExpr_wrkiselDblExprmk_baseblock_128bit_access_addrmk_baseblock_8bit_access_amodemk_baseblock_16bit_access_amodemk_baseblock_32bit_access_amodehregClassiselIntExpr_AMode_wrkiselIntExpr_AModeiselStmtmkHRegiselSB_ARM64GNUzRx oD\ P 8%AA^ TWAe J R N pxCZEB B(A0A8DP 8C0A(B BBBC c 8C0A(B BBBI xCd;\;\(;\<oD^ N XoD^ N toD^ N LFBA C(K0 (D ABBF r (D ABBE 8BAA r ABG Z ABC 8BAA r ABG Z ABC 8XFAA r ABC Z ABC 4BAD0x DBK Z DBH BBB B(D0D8D` 8A0A(B BBBG r 8A0A(B BBBD  8D0A(B BBBJ .hYpFhA`XDb J (tBDG  ABE (GBDG  ABB dBBB B(A0D8GP 8A0A(B BBBC \ 8J0A(B BBBI d4BBB B(D0D8D` 8A0A(B BBBD / 8A0A(B BBBG Db J H:BBB B(A0A8D` 8A0A(B BBBF LrBBD D(F0D (A ABBD G (A ABBC LTBBB A(D@ (D BBBH  (D EBBG L BHE E(A0D8G  8D0A(B BBBA | BBB B(A0D8GP 8A0A(B BBBG  8A0A(B BBBK \ 8D0A(B BBBG tHb F | BBB B(A0D8GP 8A0A(B BBBG  8A0A(B BBBK f 8D0A(B BBBE Hb F 0,BAD G0  AABD `)BBB B(D0D8D` 8A0A(B BBBG  8A0A(B BBBG fhSpOhB`hVpJhA`LFBB B(A0A8DP 8A0A(B BBBA o!p%< UWeCuPC;; ;`o@ /oO  h@o  p@  ` /P)=WrOZ``c @O00wh)0!:+GJ` c|  P`@+0.B[P3l O: HH 8 @ -Fp_px n px   p!P:` S`)\Xg` r `  @ '0G\^n~ '$<*(06h<(BHWNpTZR`flrx~"Ux =P _}H0p X&,28>DJ2P#VC\`bhnt}z @Ih7Wt@& ^ P n ! $ s+ 2  9 @ G N U \ c Dj *q (x _ n v            # 4 A R _ p            : J Z l ~        & 1 A R c v          # 2 @ P c u        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A{@|$T$HL D$HI$L DT$I L H HAA_A@ANA0A=E1E12A@AQA0A@E1E15A@ATA0ACE1E18A@AWA0AFE1E1;A@AZA0AIE1E1>A@A]A0ALE1E1AA@A`A0AOE1E1DA@AcA0ARE1E1GA@AfA0AUE1E1JA@AiA0AXE1E1MA@AlA0A[E1E1PA@AoA0A^E1E1SA@ArA0AaE1E1VA@AuA0AdE1E1YA@AxA0AgE1E1\A@A{A0AjE1E1_A@A~A0AmE1E1bA@AA0ApE1E1eA@AA0AsE1E1hA@AA0AvE1E1kA@AA0AyE1E1nA@AA0A|E1E1qA@AA0AE1E1tA@AA0AE1E1wA@AA0AE1E1zA@AA0AE1E1}A@AA0AE1E1A@AA0AE1E1A@AA0AE1E1A@AA0AE1E1A@AA0AE1E1A@AA0AE1E1H=1H=f.EptEgLIEHbH I$L L H H1fCH8HC[]A\A]A^A_fP$<_H5HcH>A AD|$D\$Dt$ pt AG$D$Apt AC $D$Apt AF $D$ $T$ HHL DT$I$L DT$I L H HgAA^E1E1SA@ABA0A1P$u<OH5HcH>A AD|$D\$Dt$ pt AG$D$Apt AC $D$Apt AF $D$ $T$ HHL DT$I$L DT$I L H HeAA^E1E1SA@ABA0A1PL <D$EDt$D$r1҃pt EWApt AC$Apt AFD$D$D$EHI$H I H T$L HL H HdfDD$EE1҃pt EOApt AC$AptEVD$AEHH$I H IHL L @D$EE 1҃pt EOApt AC$AptEVD$AEHH$I H IH~L L @D$EE 1҃pt EOApt AC$AptEVD$AEHH$I H IH}L L @D$EE[ 1҃pt EOApt AC$AptEVD$AEHH$I H IH|L L @D$EE 1҃pt EOApt AC$AptEVD$AEHH$I H IHuL L @D$EE 1҃pt EOApt AC$AptEVD$AEHH$I H IHtL L @D$EE 1҃pt EOApt AC$AptEVD$AEHH$I H IHkL L @D$EEW 1҃pt EOApt AC$AptEVD$AEHH$I H IHhL L @D$EE/1҃pt EOApt AC$AptEVD$AEHH$I H IHmL L @D$EEn1҃pt EOApt AC$AptEVD$AEHH$I H IHjL L DEDH51LT$D\$ LT$D\$ LT$EDDjH5U1jD\$AXAYLT$D\$ DEDH51LT$D\$ LT$D\$ XDEDH51LT$D\$ LT$D\$ sDEDH51LT$D\$ LT$D\$ DEDH51LT$D\$ LT$D\$ LT$EDDjH5U1jD\$ZYLT$D\$ LT$HDEjDH51UD\$AZA[LT$D\$ ?DEDH51LT$D\$ LT$D\$ JLT$HEDjUD1H5D\$_AXLT$D\$ fHHH)IL9HHD[]A\A]A^A_DHHH)IDH$!H$T$DiH~HQAHD1IT$HD E$DB J11EAA E;A|$ IH$HD$H$$E1H$I~fEI$ID$1H)fA<$IAB=,&HD)@DDiAAc E0 EH}1DI1fA$AD$ID$H)I,@AA E- E1fEE A@HAEl$H DpA AA|$DA"#AAHcIHH H HHzH L H 1AHHD$8HfMU6fDHHH)IfQ DAIAD$AEL$A<W$$DEAfDHHH)IfA QIAAD$<AD$k''DEH}DH)I"f.Dq DiIAD$AAAA<QAD$EDH51+1AfMf.HAPJ*H 1H .IP ID$1H)fA4$If.Q IAD$2H51DHQqHH)IDHHH)IzfDiQ IAD$AA<N<H5+1AD$HIAAPAaAT$-DAAAEDAAAEDA q$cDE Ax'HEEDHdQDHH)IXZOHH%5H)I2f.Q DIHAAEAAf@ H ZDhAD$AAFA|$ $耹 $Dg$HAEDH0ATDHH)IXZsI1H IsA$IyHE1A 1j1LHP1E1E1Hǹ 1^_A}FH)AEI@HA&DpDh AAKEEEELm AEID$I}1Ҿ D@ HEAA EIiE1ID$fE$HH)IHH9H T+H5H=HADiH~AHDD@ H1At$EAA EaA|$ IƍV HHcH>fH$LDiHAH~AHD0D@ At$ 1ҋHEAA EH$HIeID$1H)fA $IAB=H *H5H=DAQ AAAAHAAJ9A|$DDHAS1,1DHDHA[H)]Iw<wuH=<uH|H)I?H5+"1?H5+1fH=@AVHH)B=hHH $D)@H $yH5+1afpDH$HHH H DHH qH5+"1YfDE A[HEEDHeQDRHD`H)ID$AADL$1Apt DbAptDYApt A@$Apt AAD$A@$EH$HI H HL H T$H H HH5+11HI1DH51f.A|$D$AADL$1Apt DbAptDYApt A@$Apt AAD$A@$EH$HI H HL H T$H H HDH5+1H5DH9AD$<+H51@DA DoIIcIE1HfD]LmHjL L H HHD$8HU 1l_%HzE1A$HD$8ID$fET$蔬<+H51D 9E1DDHHVH)I A|$DDHH)IH51fDH51H=fDiDEAA EE%HH}EDHAT1]AXAYHAEDHH)IDHtH)IA|$ $苢 $DoHAEDH!ATDA|$ $H $D HAEDH:ATDEEA AE HDLEH1AS1QY^HoDH$HAH H DHH e@DH$HIH H DHH $ DH$H@H H DHH gAEEDH5+1B5AEEDH5+11ɺ1(H H5H=H 9+H5H=H v+H5H=H 7)H5H=D$AEAVEH5j1AYAZD$H $H5H=H +H5H=H *H5H=H M*H5H=1H51+D1H511H51A E11H51uH $H5H=H *H5H=1H51E1D1ҿH51fE1H51mA E11H51$H51LL$LL$E1fEQ}A1ɺ1H5LL$SHD$A11H5LL$ H ,H5H=E1A 1D1H1DHH)IO2E1A 1HDDYH)I& 1K H51ATEE1DAVDH51DT$AZA[D$ 1wH w+H5H=H _H5H=H N*H5H=H $H5H=H *H5H=D1H5H5 1H h*H5H=H H5H=A1H51" 1{1ɺH51 1 HADEPE11H5{L$XZ $L1H51nHE1E11j 1H51AXAY[H 'H5H=EE1D1H51ED1EE11H5Lm E1H51MH 'H5H=H H5H=H *H5H=H H5H=1H51D$D$'AWDH51jq1DD$EDT$Y^DL$D$1H51DD$L$DD$L$EH5+1A̺1lL $L $1H51DD$L\$DT$D $DD$L\$DT$D $1H51DD$DT$D $DD$DT$D $AWED1j1H5qDL$ D\$DT$XZDL$D\$D$L$/H5]1DT$(jjDL$4DD$0L$,T$ ^_D\$/DT$(DL$$DD$ L$T$0H (,H5H=L$/H5]1DT$(jjL$,T$ DL$4DD$0AXAYD\$/DT$(DL$$DD$ L$T$VEEAVDH51L$_AX $H5 1L$/DT$(DL$$DD$ L$T$D\$/DT$(DL$$DD$ L$T$&ASA E11j1H5{1A^A_DDH裖H)IPH :!H5H=DDH51+sH H5H=H H5H=P1EjE1DH5{XZhDDH51QH5+1)ATDE1EAW1H51A]A_ATEE1DAWH51L$AYAZ $iAQDE1EAW1H51AZA[ATE1EAWDH51L$_AX $FATH5EE1AWD1L$Y^ $AWEDѿqj1H51DL$ D\$DT$_AXDL$D\$D$AT1EE1AWDH5L$A[X $bAWD1H5jq1DD$EAZA[D $H H5H=H H5H=H H5H=H H5H=WE1E1DAUH5+1L$AXAY $AWD1E1AUE1+H5L$XZ $"VE+EAVDH51L$_AX $ZARE1E1DAUH5+1L$A[A\ $3VE1+E1AUDH51L$_AX $ASD1EAVE+H5L$XZ $wH=H=LH=H1H=H=H=H=H=H=H=H=@%DATI1SLHHHH t5AD$A\$%LHH[A\H AD$ HfH(fAT$HHAD$ HAT$HH0HH8AD$AT$A\$@ATUSHIHHL'8t"H 6-H5H=xuHL)HH?HHHʚ;H=5wtvHIT$1H 1HfAD$A$fAD4H Ƀ9wHD)L[]A\@HL}HH[L]D)A\H ,-H5H=fHٺ1l1fATUH1>IHt6HL賟8H -H5H=~uċFHHH9HF҃ HTH9tcHxtH -H5H=f.x\1HLfAD$&H31HLfAT$Huc1fMHLD)]A\fDH -H5H=fH -H5H= 11ɺH51B1ɺH51size=%d lgrlghislllraebrsebrmeebrdebradbrsdbrmdbrddbraxbrsxbrmxbrdxbrs390_insn_bfp_binop_emitlpebrlpdbrlpxbrlnebrlndbrlnxbrlcebrlcdbrlcxbrsqebrsqdbrsqxbrs390_insn_bfp_unop_emitpriv/host_generic_regs.hpriv/host_s390_defs.cs390_host_has_dfpadtradtrasdtrsdtramdtrmdtraddtrddtraqadtraxtraxtrasxtrsxtramxtrmxtradxtrdxtraqaxtrs390_insn_dfp_binop_emits390_host_has_gieasicode[0] == 0xC0code[1] == (0x08 | regmask)code[6] == 0xC0code[7] == (0x09 | regmask)code[0] == 0xA5code[1] == (0x03 | regmask)code[2] == (hw >> 8)code[3] == (hw & 0xFF)code[4] == 0xA5code[5] == (0x02 | regmask)code[6] == (hw >> 8)code[7] == (hw & 0xFF)code[8] == 0xA5code[9] == (0x01 | regmask)code[10] == (hw >> 8)code[11] == (hw & 0xFF)code[12] == 0xA5code[13] == (0x00 | regmask)code[14] == (hw >> 8)code[15] == (hw & 0xFF)s390_host_has_fpextcfdtrcfxtrcgdtrcgxtrclfdtrclfxtrclgdtrclgxtrcdftrcxftrcdgtrcdgtracxgtrcdlftrcdlgtrcxlftrcxlgtrldetrlxdtrledtrldxtrs390_insn_dfp_convert_emitcfebrcfdbrcfxbrcgebrcgdbrcgxbrclfebrclfdbrclfxbrclgebrclgdbrclgxbrcefbrcefbracdfbrcxfbrcegbrcegbracdgbrcdgbracxgbrcelfbrcdlfbrcxlfbrcelgbrcdlgbrcxlgbrldebrlxebrlxdbrledbrledbralexbrlexbraldxbrldxbrafiebrfidbrfixbrs390_insn_bfp_convert_emitipmsrliihfs390_host_has_eimmiilfiilliilhiihliihhlhillilflgfillilhstglgsllgsrlglgdrstdyldgrldyxcmvimvhhimvhimvghisthsts390_insn_mimm_emits390_amode_get_reg_usages390_opnd_RMI_get_reg_usages390_amode_map_regss390_opnd_RMI_map_regs(r1 & 0x1) == 0r1p1 == r1 + 1s390_insn_clz_emitflogrltgrllillaghiiclhlvlicylhylys390_emit_load_memslfisrdrdlrs390_insn_div_emitdlgrddldlgltrltltgs390_insn_test_emitstesteystds390_insn_store_emitinsn->size == 16vststcstcysthystycrclrcgrclgrcclcyclycgclgcficlficgficlgfis390_insn_compare_emitmrmlrs390_insn_mul_emitmlgrmmlmfymlglocgrs390_host_has_lscloclocginsn->size == 8s390_insn_cond_move_emitlbrsrallcrnrlgbrsragllgcrngrlhrllhrlghrllghrlgfrllgfrlbllclgbllgcllhllghlghlgfllgfoills390_widen_emitlcrlcgrs390_negate_emitvgbmvrepinsn->size < 8vuphvuplhvlpvclzvctzvpopctvfpsovfsqs390_insn_unop_emitarmsrorxragrsgrmsgrogrxgrdst != 15ahshmhahyshymhyasmsnoxaysymsynyoyxyagsgmsgngogxgahimhinillafimsfinilfoilfxilfagfislgfimsgfinihfoihfxihfs390_insn_alu_emitix >= 0ix <= 0xFFFFFenc <= 0x7F%%vR%u%%vF%u%%vV%ur < 16r < 32s390_hreg_as_stringfits_unsigned_12bit(d)fits_signed_20bit(d)hregNumber(b) != 0hregNumber(x) != 0invalid guest state offsetinvalid stack pointer offset%d(%s)%d(%s,%s)s390_amode_as_stringalwaysnevergreater thannot low or equalless thannot high or equallow or highnot equalequalnot low or highgreater or equalnot lowless or equalnot highnot overflowoverflowSys_syscallBoringReturnClientReqYieldEmWarnEmFailNoDecodeMapFailInvalidateNoRedirSigTRAPSigFPESigSEGVSigBUSCall%s%-8sguest[%u]s390_cc_as_strings390_jump_kind_as_string, r%u%lld%llu0x%llxs390_printfs390_amode_is_sanegpr_index[i] >= 0vr_index[i] >= 0s390_insn_get_reg_usages390_insn_map_regsoffsetB >= 0!hregIsVirtual(rreg)src->tag == S390_AMODE_B12dst->tag == S390_AMODE_B12! hregIsVirtual(dst_hi)! hregIsVirtual(dst_lo)size == 4 || size == 8! hregIsVirtual(op1_hi)! hregIsVirtual(op1_lo)size == 8! hregIsVirtual(op1)! hregIsVirtual(rem)! hregIsVirtual(num_bits)! hregIsVirtual(clobber)hregNumber(op2->x) == 0hregNumber(scratch) == 1is_sane_RetLoc(rloc)size == 16hregIsInvalid(op_lo)size == 4v-rshav-addv-mulv-andv-orv-xorv-lshv-rshv-subv-mulsv-muluv-divsv-divuv-vfloatabsv-zeroxv-negv-vfillv-vdupv-vunpacksv-vunpackuv-vfloatnegv-vfloatsqrtv-signxv-cmpsv-cmpuv-fmaddv-fmsubv-faddv-fsubv-fmulv-fdivv-fabsv-fnabsv-fnegv-fsqrtv-f2fiv-i2fv-f2iv-f2uv-f2fv-u2fv-dquav-daddv-dmulv-ddivv-dsubv-d2expv-d2sigv-dshrv-diexpv-dshlv-dcmpv-dcmpexpv-d2uv-d2dv-u2dv-d2iv-i2dv-f2dv-d2ffastslowv-vgetelemv-veshlv-veshrav-veshrlv-vfloatcmplv-vpackv-vpacksaturuv-vcmpeqv-vorv-vxorv-vandv-vmergelv-vmergehv-vnorv-vintaddv-vintsubv-vmaxuv-vmaxsv-vminuv-vminsv-vavguv-vavgsv-vcmpgtsv-vcmpgtuv-vintmulhisv-vintmulhiuv-vintmullov-vintmulevensv-vintmulevenuv-velemshlv-vshravv-vshrlvv-vrollvv-vshlbitsv-vshrlbitsv-vshrabitsv-vshlbytesv-vshrlbytesv-vshrabytesv-vpwsumwv-vpwsumdwv-vpwsumqwv-vinitfromgprsv-vfloataddv-vfloatsubv-vfloatmulv-vfloatdivv-vfloatcmpeqv-vfloatcmplev-vpacksatursv-vfloatmaddv-vfloatmsubv-vpermv-load%M %R,%Av-storev-move%M %R,%Rv-memcpy%M %A,%A%M if (%C) %R,%Ov-loadi%M %R,%I%M %R,%Ov-divsiv-clzv-test%M %Ov-cc2b%M %R,%Cv-cas%M %R,%A,%R,%Rv-cdas%M %R,%R,%A,%R,%R,%R,%Rv-call%M if (%C) %s{%I}(%L)%M %R,%R,%Rv-fcmpv-drrndv-mfence%Mv-mimm%M %A,%Iv-madd%M %A += %I (= %I)v-set-fpc-bfprm%M %Rv-set-fpc-dfprmv-evcheckv-profincv-xdirect%M if (%C) %A = %I %sv-xindir%M if (%C) %A = %Rv-xassisted%M if (%C) %J %A = %R%M %R, %R, %Av-vsetelem%M %R, %A, %R%M %R, %R, %R%M %R, %R, %R, %R 1 -> 2 -> 4 -> 8 -> 16 -> %u bytess390_insn_as_stringvpkvpklsvpksvceqvovxvnvmrlvmrhvnovavsvmxlvmxvmnlvmnvavglvavgvchvchlvmhvmlhvmlvmevmleveslvvesravvesrlvverllvvslvsrlvsravslbvsrlbvsrab(size == 1) || (size == 2)vsum(size == 2) || (size == 4)vsumg(size == 4) || (size == 8)vsumqvlvgpvfavfsvfmvfdvfcevfchvfches390_insn_vec_binop_emitleleylds390_insn_load_emitldrvlrs390_insn_move_emitmvcvalue == 0lzerlzdrs390_insn_load_immediate_emitdsgrdsgs390_insn_divs_emitcscsycsgs390_insn_cas_emitscratch == 1cdscdsycdsgs390_insn_cdas_emitstfpcbasrlfpcmaebrmsebrmadbrmsdbrs390_insn_bfp_triop_emitcebrcdbrcxbrs390_insn_bfp_compare_emiteedtreextresdtresxtrs390_insn_dfp_unop_emitsldtsrdtiedtrslxtsrxtiextrs390_insn_dfp_intop_emitcdtrcedtrcxtrcextrs390_insn_dfp_compare_emitrrdtrrrxtrs390_insn_dfp_reround_emitrm < 2 || rm > 7s390_host_has_pfpopfpos390_insn_fp_convert_emitagsisfpc*is_profinc == Falseamode->tag == S390_AMODE_B12disp_cp_xindir != NULLfits_unsigned_12bit(op2->d)vlgvveslvesravesrls390_insn_vec_amodeop_emitvlvgvpermvfmavfmss390_insn_vec_triop_emitemit_S390Instrend - buf <= nbufendness_host == VexEndnessBEp[6+i] == 0x00s390_getM_from_size: unknown sizerc >= HRcInt32 && rc <= HrcLASTm4 == 0 || s390_host_has_fpext*(const UInt *)&code[2] == (value >> 32)*(const UInt *)&code[8] == (value & 0xFFFFFFFF)s390_host_has_fpext || m3 < 1 || m3 > 7m3 == 0 || s390_host_has_fpextbuf - begin == s390_tchain_load64_len()s390_insn_store_emit: unknown dst->tag for HRcVec128am->tag == S390_AMODE_B12 || am->tag == S390_AMODE_B20insn->size == 4 || insn->size == 8delta > 0 && delta < (1 << 16)insn->variant.unop.src.tag == S390_OPND_IMMEDIATEinsn->variant.unop.src.tag == S390_OPND_REGgenSpill_S390: unimplemented regclassgenReload_S390: unimplemented regclasssize == 1 || size == 2 || size == 4 || size == 8 || size ==16genMove_S390: unimplemented regclasssize == 1 || size == 2 || size == 4 || size == 8 || size == 16size == 1 || size == 2 || size == 4 || size == 8op2->tag == S390_AMODE_B12 || op2->tag == S390_AMODE_B20is_valid_fp128_regpair(dst_hi, dst_lo)is_valid_fp128_regpair(op2_hi, op2_lo)is_valid_fp128_regpair(op_hi, op_lo)is_valid_fp128_regpair(op1_hi, op1_lo)hregIsInvalid(op_lo) || is_valid_fp128_regpair(op_hi, op_lo)is_valid_fp128_regpair(op3_hi, op3_lo)dst->tag == S390_AMODE_B12 || dst->tag == S390_AMODE_B20guest_IA->tag == S390_AMODE_B12counter->tag == S390_AMODE_B12fail_addr->tag == S390_AMODE_B12%M counter = %A, fail-addr = %As390_insn_helper_call_emit: invalid conditional RetLoc.evCheckSzB_S390() == code_end - code_begindisp_cp_chain_me_to_slowEP != NULLdisp_cp_chain_me_to_fastEP != NULLs390_insn_xassisted_emit: unexpected jump kinds390_insn_is_BR(next, S390_REGNO_TCHAIN_SCRATCH)p + delta == place_to_jump_to_EXPECTED            unchainXDirect_S390chainXDirect_S390s390_tchain_verify_load64s390_insn_vec_triop_emits390_insn_vec_binop_emits390_insn_vec_amodeintop_emits390_insn_vec_amodeop_emits390_insn_xassisted_emits390_insn_xindir_emits390_insn_xdirect_emits390_insn_evcheck_emits390_tchain_load64s390_emit_AGSIs390_emit_ASIs390_emit_PFPOs390_insn_fp_convert_emits390_emit_RRXTRs390_emit_RRDTRs390_emit_LDXTRs390_emit_LEDTRs390_emit_LXDTRs390_emit_LDETRs390_emit_CXLGTRs390_emit_CXLFTRs390_emit_CDLGTRs390_emit_CDLFTRs390_emit_CXGTRs390_emit_CDGTRAs390_emit_CXFTRs390_emit_CDFTRs390_emit_CLGXTRs390_emit_CLGDTRs390_emit_CLFXTRs390_emit_CLFDTRs390_emit_CGXTRs390_emit_CGDTRs390_emit_CFXTRs390_emit_CFDTRs390_emit_CXTRs390_emit_CDTRs390_emit_SRXTs390_emit_SLXTs390_emit_SRDTs390_emit_SLDTs390_emit_QAXTRs390_emit_DXTRAs390_emit_MXTRAs390_emit_SXTRAs390_emit_AXTRAs390_emit_QADTRs390_emit_DDTRAs390_emit_MDTRAs390_emit_SDTRAs390_emit_ADTRAs390_emit_FIXBRAs390_emit_FIDBRAs390_emit_FIEBRAs390_emit_LDXBRAs390_emit_LEXBRAs390_emit_LEDBRAs390_emit_CXLGBRs390_emit_CDLGBRs390_emit_CELGBRs390_emit_CXLFBRs390_emit_CDLFBRs390_emit_CELFBRs390_emit_CDGBRAs390_emit_CEGBRAs390_emit_CEFBRAs390_emit_CLGXBRs390_emit_CLGDBRs390_emit_CLGEBRs390_emit_CLFXBRs390_emit_CLFDBRs390_emit_CLFEBRs390_insn_helper_call_emits390_insn_cdas_emits390_insn_cas_emits390_insn_unop_emits390_insn_clz_emits390_emit_XILFs390_emit_OILFs390_emit_NILFs390_insn_alu_emits390_insn_load_immediate_emits390_emit_IILFs390_emit_LOCGRs390_insn_cond_move_emits390_insn_store_emitemit_S390Instrs390_insn_vec_binops390_insn_vec_amodeintops390_insn_vec_amodeops390_insn_evchecks390_insn_xassisteds390_insn_xindirs390_insn_xdirects390_insn_set_fpc_dfprms390_insn_set_fpc_bfprms390_insn_madds390_insn_mimms390_insn_dfp128_rerounds390_insn_dfp128_converts390_insn_dfp128_compares390_insn_dfp128_intops390_insn_dfp128_unops390_insn_dfp128_binops390_insn_fp128_converts390_insn_fp_converts390_insn_dfp_rerounds390_insn_dfp_converts390_insn_dfp_compares390_insn_dfp_intops390_insn_dfp_unops390_insn_dfp_binops390_insn_bfp128_converts390_insn_bfp128_compares390_insn_bfp128_unops390_insn_bfp128_binops390_insn_bfp_converts390_insn_bfp_compares390_insn_bfp_unops390_insn_bfp_binops390_insn_bfp_triops390_insn_helper_calls390_insn_compares390_insn_cdass390_insn_cass390_insn_tests390_insn_clzs390_insn_divss390_insn_divs390_insn_muls390_insn_cond_moves390_insn_memcpys390_insn_moves390_insn_stores390_insn_loadgenReload_S390genSpill_S390getRRegUniverse_S390s390_amode_bx20s390_amode_bx12s390_amode_b20s390_amode_b12hregClass%v0%v1%v2%v3%v4%v5%v6%v7%v8%v9%v10%v11%v12%v13%v14%v15%v16%v17%v18%v19%v20%v21%v22%v23%v24%v25%v26%v27%v28%v29%v30%v31%f0%f1%f2%f3%f4%f5%f6%f7%f8%f9%f10%f11%f12%f13%f14%f15%r0%r1%r2%r3%r4%r5%r6%r7%r8%r9%r10%r11%r12%r13%r14%r15s390_hreg_as_strings390_hreg_vrs390_hreg_fprmkHRegs390_hreg_gprGNUzRx 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hJpYhA`NhJpZhB`NhJpZhB`NhMpVhA`ghIp[hA`NhIpZhA`p BBB B(A0D8D` 8E0A(B BBBF  8E0A(B BBBC  8A0A(B BBBG hMpUhB`NhMpThB`NhMpThB`NhJpWhA` BBB B(A0D8D`[ 8E0A(B BBBF j 8E0A(B BBBH c 8A0A(B BBBC hMpThB`hNpVhA`~hLpUhA`LhJpWhA`d BBA D(D@ (D ABBD T (D DBBH oHLPTHA@GHOPQHB@H< BBB B(A0D8D` 8A0A(B BBBG   8E0A(B BBBH / 8E0A(B BBBK  hMpWhB`NhNpVhA`ShKpZhB`NhKpZhA`khKpZhB`NhKpXhB`IhKpZhA`PhNpXhB`GhMpXhA`2hNpXhB`GhMpYhA`ChJp[hA`hJpXhA`FhJpUhA`QhQpQhA`FhMpRhB` BBB B(A0A8D`U 8G0A(B BBBM  8A0A(B BBBJ  8A0A(B BBBO K 8D0A(B BBBE AhMp[hB`BhNpYhA`<BBE B(A0D8D` 8A0A(B BBBA  8E0A(B BBBA  8E0A(B BBBG 4 8J0A(B BBBI / hMpUhB`GhOpShA`GhJpXhA`hLp_hB`GhKp_hA`GhNp\hB`GhJpYhA`GhKpWhB`GhKpXhB`hTpLhB`ahIpUhA`IhGpThA`FhLpRhB`GhJpUhB`FhLpRhB`GhJpUhB`hJpUhB`GhJpUhB`GhIpUhA`FhLpRhB`IhEpUhA`dhLpRhB`GhIpUhA`hhIpUhA`chLpQhB`GhIpUhA`FhLpRhB`@hHpRhA`GhNpRhB`<QZ U XQZ U tQZ U 8LS A n J u K H H X H ` H oHZ F oHZ F HR F  HV B <HJ F XHN J 4t@FAF  DBF  DBA 4@FAF  DBF  DBA 8FHH j HBF H HBA H GBBB B(A0A8D 8A0A(B BBBA $lHC E i G h H (FHH j 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ABB Hm K L C L C Hh H Lg E 4H D P0kddHw A HS E dHr F dHr F tH I lHy G  tH~ J (H} K D0kXHU A tHV A |HH H A|FBA A(D0s (H ABBB 8W@P8B08e@I8B068T@R8A0d8D@DHDPT0L8R@W8A08R@W8A0P"HPh 3BBB B(A0A8Dpa 8E0A(B BBBC  xPLxBpxPKxApXxH]xBpMxH\xBpXxH\xApaxNKxApxH\xApxH]xBpXxG^xAp0/FBB B(A0A8DS 8D0A(B BBBF eTRAURAOMlA UN  TJ U[At UH hUfD TH VIBf UH f UH fUHAONB(K]BK[AkJWBMNZAJcAlBXAZBYBcMVBZMWBJXA}LWBGKYBJLWBGMVBJOTAJM`BUJZAJNVBKYBJJYAIMVBJKYBIMVBJJYA(FFJ w DBM @nFAA D0  GABE O  DDED (`FAD - GBG uF#F2 D@pPNE[tu QLLk@%p% pE 0@Ipb`{P0XE_ zP`)B`[@t 0 #<pUnx 8QjpPp2PK0d0} ++:0@ .Mp/$ 323?4N`5] 6Mmp7M}8(<=@>AFyH7'@LJ;PPiWP^pc`Ph {  / H a z  `@ ' '  & &   %# &P3  &PC &\ `%u P% @% 0%  G  , L `P %# %< $U $n $ $ $ $ h$ X$ H$ 8$6 ($O $h $ # # # # p# P# 0#0 #I "b "{ " " p" P" 0" "!*!C!\!up!P!0!!    $ = Vp oP 0    3P8HD^xpp-PFh_Hx00 )B[t  VG=) Q.B!#&8,L238>DoJP{V\bhntuz(&<cXMBnhG+]6R 1 tH"I(.4:@ F'LhRX<^dSjpcv|3u {"a(.4;AHO;V]dIkryxre ~)B#PW/ ^5!(k/6=DKRY.`2gXn]ub|S6;Ngkqv|$+29@GRN3UC\kcpjvqex~{ 8* '.35.<8C&JQXs_Cf<mGt?{LNX[TQ_cmhp#*18n?F8M=T`[db2i-pw~$( iW\ NCJFS( &-4;BI~PW^ el s z    d h l : 8 5 3 1 <    z    "u )W 0a 7T >Q E^ L[ SH Z> aD hA o vK }N q  " ) %  -           , A T g   % , 3 :> A H O; V ]B dG kL rS y"   v       # ) 9 J R ` i        ! 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E11L%D$$K4= = H;=D$t3HD$DLH01DD$DH=1IE9w|$ r1|$T$$I4AA= o= HlJDPHAA9wH|$0HD$08 uH@8Ht$0HD$E1L=D9so}ADTPH{IƋW ;WHHcʃL4ȉW tLLH1D9rHD$@H0HD$8HL$(A t@H H5H=D$$HfDD$ 8HD$HD$=wr==/HD$(HHD$(|$DLH{W ;WH7HcʃHΉW Hx[]A\A]A^A_Á|$HD$(HHD$8f.|$E1E1H|$0D$HC$PS$= DP‰tPH{IƋW ;WHHcʃL4ȉW iLH=H1KfDC$PS$=5 DP=MED$DD$HH#D$HHHD$HH{IG ;G%HHcȃLʉG RBtPH{IƋG ;GHHcȃL4ʉG H H5H=H H5H=H H5H=H H5H=HD$(H?HHxH=[H]1A\A]A^A_H H5H=|$$)H H5H=D$LH=H1xD$VbH H5H=H H5H=HHD$HD$lH H5H=L$LLD$LD$H=H=HH=1|$H=1H H5H=AWAVAUATUSHhD*$D$D$D%D$ z/L=IH;HHEDAG$H IG1IDID@AƄHHuQ HcLH=AW HHI4H9IHH5MGH92HH$IwIG0IG8Eo(IGxE~LDj11H=E A RHcH>f.AɸAE HBI9Hf|AɸA뾁w`At[A A띁w?AɸA끁w#AtA A]H H5H=H H5H=H H5H=H H5H=1AO$DILHIHŋG ;Gr HHcȃH,ʉG 9 |$ k L5fDD$ HKL,ЃM3AE- H5HcH>b S|$T)|$\DHIHgt$TLjЃD$ t$ 9sCDk$Dc Hkt=DH=1HH=1DH=1D} IA$G  A$HHcH>H=1LH=1DH=HL蓥Pu M D LIHŋG ;G HHcȃH,ʉG  IGAW$PHh[]A\A]A^A_H=LH=@IuI?A}Aĉ|$d|$tIu> HAƄHA$ wHHcH>IuI?A}AeIuLHA$ EHHcH>EeI?Dō H HcH>IE8B A}IuLIAE=l -IcL>I}LHƾAMLIHdA}oMeD$T1HD$XAT$,~CH\$A|6Hc\A|7PAD0f-fH9H\$At$ I?ōv AT$Aw ID$cHt$XH|$TLIL$AI$At$ULHL@D$hT$lY^DT$3 H H5H=ImL}HuDHu(LHD$8EHu0LD$5HuLD$ %Hu LD$$Aw IWD$(E9DADD$4E9D ADL$0 AT$$DAIHbT$(DIHb D$T$t$D$IHobT$ t$IHQbuI?D$,T$,DL$0=DD$4LT$8HLDRDAPAQDL$8DD$0IH Hat$$DIHat$(DIHaT$t$IHaT$t$ D]IuEu= y =S LADDHDAHvHI HnHQ@Hi@AAƄt=H9t0tHH)HH9p HH H H9 HDUIuEK=  =U=(M DFDL$DD$L$DD$A9A9Iu@IuLAw IDA_ADDIuLxAIuLjAIuLpjIuLBH=@IuLDjAGIuLA3H=@IuLAIuLAIMHt$HH|$DLzE;g IGJ8]IW0B,T$DIH^T$HIH^IMHt$XH|$TLTuE;g IGJ8IW0B,T$TIHu^T$XIuL:IMHt$PH|$LLE;g IGJ8{IW0B,T$LIH ^T$PIuLTAw ID]IH]IHŋG ;GHHcȃH,ʉG CDk$Dc HkDHH=H1A|2[HAƄH {H5H=HU:AkHr1I;wxLIH\?HL肶ALHH=H1HH=H1H袶Hu0LIHu LAuAIGA;w ,I?DL$DL$AD=LDEЃAI}Hw1I;wxLHLDRDAPAQDL$8DD$0iH H5H=H H5H=LHLHQP#H=H(H H5H=IH~ZH H5H=H H5H=I$Ht$XH|$TLIL$At$hLHL@D$hT$lAXAYwGH H5H=0T$TDDwH H5H=HLBLIHRYH XH5H=~HvLEDHD$HT$:Aw$D$HT$FAG$9YL$HT$AIHXmH H5H=H H5H=DljT$T$HHIHJXeH|$THH H5H=H=~DILHFgH HcH>H H5H=H H5H=HFH HcH>HL$IHL$LHIHW:HIHVH H5H=H H5H=LchDHLIHVLhLhDhI?I?LhH=partial update of this guest state register is not allowed! hregIsInvalid(env->vregmap[tmp])ty == Ity_F32 || ty == Ity_F64s390_isel_float_expr: invalid constantcannot load immediate floating point constantirrm->Iex.Const.con->tag == Ico_U32s390_isel_float_expr: cannot reduce treerc >= HRcInt32 && rc <= HrcLAST! hregIsInvalid(env->vregmapHI[tmp])s390_isel_dfp128_expr_wrk: cannot reduce treehregClass(*dst_hi) == HRcFlt64hregClass(*dst_lo) == HRcFlt64ty == Ity_D64 || ty == Ity_D32s390_isel_dfp_expr: cannot reduce trees390_isel_float128_expr: cannot reduce treety == Ity_I8 || ty == Ity_I16 || ty == Ity_I32 || ty == Ity_I64s390_isel_int_expr: impossible Iop_GetElem types390_isel_int_expr: unhandled V128toSMTH operations390_isel_int_expr: invalid constanttypeOfIRExpr(env->type_env, cond_expr) == Ity_I1s390_isel_int_expr: cannot reduce treetypeOfIRExpr(env->type_env, expr) == Ity_I64s390_amode_is_sane(am) && (am->tag == S390_AMODE_B12 || am->tag == S390_AMODE_B20)typeOfIRExpr(env->type_env, irrm) == Ity_I32expr->Iex.Const.con->tag == Ico_V128s390_isel_vec_expr: cannot reduce treehregClass(*dst_hi) == HRcInt64hregClass(*dst_lo) == HRcInt64typeOfIRExpr(env->type_env, cond) == Ity_I1cond->Iex.Const.con->tag == Ico_U1cond->Iex.Const.con->Ico.U1 == True || cond->Iex.Const.con->Ico.U1 == Falses390_isel_cc: unexpected operatordoHelperCall: too many argumentscalling %s: argument #%u has type ; Ity_I64 or Ity_V128 is required cannot continue due to errors in argument passing; an integer type is required (VEX_HWCAPS_S390X(hwcaps_host) & ~(VEX_HWCAPS_S390X_ALL)) == 0archinfo_host->endness == VexEndnessBEIst_Store with 128-bit floating point dataIst_Put with 128-bit floating point datad->fxState[i].nRepeats == 0 && d->fxState[i].repeatLen == 0s390_isel_stmt: invalid return type from dirty helpers390_isel_stmt: Ist_Exit: dst is not a 64-bit value  iselNexts390_isel_int_expr_wrks390_isel_int_exprs390_isel_cclookupIRTemps390_isel_amode_b12_b20add_to_SPsub_from_SPdoHelperCalls390_isel_vec_expr_wrks390_isel_vec_exprlookupIRTemp128s390_isel_dfp128_expr_wrks390_isel_dfp128_exprs390_isel_dfp_expr_wrks390_isel_dfp_exprs390_isel_float128_expr_wrks390_isel_float128_exprset_bfp_rounding_mode_in_fpcget_bfp_rounding_modeset_dfp_rounding_mode_in_fpcget_dfp_rounding_modes390_isel_float_expr_wrks390_isel_float_exprhregClasss390_isel_int_expr_RMIs390_isel_int128_expr_wrks390_isel_int128_exprs390_isel_amodes390_isel_stmtmkHRegiselSB_S390s390_opnd_copypriv/host_s390_isel.ctmp < env->n_vregmap%s priv/host_generic_regs.hix <= 0xFFFFFn < 256 && (n%8) == 0get_bfp_rounding_modehregClass(dst) == HRcFlt64hregIsVirtual(dst)ty == Ity_D128Iex_Get with D128 dataIex_Qop with D128 datahregIsVirtual(*dst_hi)hregIsVirtual(*dst_lo)ty == Ity_F128Iex_Get with F128 dataIex_Qop with F128 datas390_expr_is_const_zerosize <= 8is_sane_RetLoc(rloc)rloc.pri == RLPri_IntaddToSp == 0hregClass(dst) == HRcInt64s390_amode_is_sane(am)ty == Ity_V128hregClass(dst) == HRcVec128get_dfp_rounding_modes390_isel_int_expr_RMIty == Ity_I128s390_isel_int128_exprnGSPTRs == 0 || nGSPTRs == 1nVECRETs == 1nVECRETs == 0*stackAdjustAfterCall == 0is_RetLoc_INVALID(*retloc)calling %s: return type is 0bb->tyenv->types_used >= 0iselSB_S390: IRTemp type -- get_const_value_as_ulongrloc.pri == RLPri_Nonerloc.pri == RLPri_V128SpReladdToSp == sizeof(V128)s390_isel_stmt -- PUT(%d) = ; exit-cdst->tag == Ico_U64iselNextGNUzRx wQ4ITLL_DU G hWAe J P P ;\8BAA ] ABD ] ABH 8BAA d ABE ] ABH 8BAA W ABB I HEJ HTBBB B(A0A8D@ 8D0A(B BBBJ d BBB B(D0D8D` 8D0A(B BBBK hWpxhA` hJp{ BEB B(G0D8G 8A0A(B BBBI LEEZ GsAR_ RU HmAd BBB B(D0D8D` 8D0A(B BBBJ vhJpohA`QhYpthA`| BBE B(G0D8G 8A0A(B BBBI nTnAWeA He BBB B(D0D8Dp 8A0A(B BBBG xNQxApxHcxDph xHZ MxKbxBpDb J ,0BDD ~ ABE ,`BDD s ABH L-BBA D(G0 (A ABBD l (H DDBJ kDj B K E HBBB B(D0D8DP 8D0A(B BBBJ LLBBA D(G0 (A ABBF  (H DDBJ kDj B K E LBDG  DBB H IBE x IBE L IBI H  BBB E(G0D8Gp 8A0A(B BBBF HXwBBE H(D0D8DP 8D0A(B BBBA diBBB B(A0A8G3 8A0A(B BBBA } 8H0D(D BBBE VFBB B(A0A8D/ 8A0A(B BBBA tAVALEBWh LEBO BEWBI_2 KPW[;no 0  @_-$= [P[]k& ~p{k 1 pbk@0`IwfP@{*w70iK`dbw@} [P )0B[`t  0   .x G``H y~%@:>Weh8{ X8#*)P/95p;AGhM8SY_ekgqw} xP4KZ8p (%`+17=CIO7U1[agmsyHRi9    0;J^m   + 9 Q g         # 7 M c w        ' : F \ u         ( 6 E X g           9 VE _ y         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H5H=H  H5H=H H5H=1hEL=LibL)H>H ) H5H=H * H5H=H 2 H5H=H H5H=H H5H=H H5H=H hH5H=t$A?A 1LUL)HBt$A<A 1LUL)HH 3 H5H=H H5H=t$A>A 1L)UL)HH H5H=H B H5H=y R}ARAH W H5H=H H5H=H H5H=H X H5H=t$AE1L!TL)HEL9L3]L)Ht$AE1LSL)HxEL1L\L)HZt$AE1LSL)H:t$AE1LSL)Ht$AE1LeSL)Ht$AE1LESL)HH H5H=H H5H=#+EL5L\L)HiEL=L[L)HJQ}UAH H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H jH5H=H H5H=H 1H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=Q1LE1jE11DM^_L)HAPE1E11jD1LMAYAZL)HASLE1Ej111^M]L)A\HAVE1E1j11L8MA_L)HXf.fDPXHw3uMAPH tVH5H=H H5H=H H5H=H5H=fPXHw4uNAHOH tVH5H=H H5H=H H5H= H5H=PXHwzt?@HUeUeUeUeKOH t7:H5H=H 1H5H=5H5H=H -H5H=H 4H5H=rs = %u priv/host_mips_defs.crs < 0x20rt < 0x20rd < 0x20sa < 0x20!hregIsVirtual(r)n <= 31addRegUsage_MIPSAModemapRegs_MIPSAModerRD < 0x20rRS < 0x20rRT < 0x20sa >= 0 && sa <= 0x3Fp == (UChar*)&expect[2]p == (UChar*)&expect[6]priv/host_generic_regs.hn <= 32r_dst < 0x200 == (am->Mam.IR.index & 3)am->Mam.IR.index < 0x100000am->tag == Mam_IRam->tag == Mam_RRr >= 0 && r < 32%sppHRegMIPSNVLEGELTMIPLVSVCHILSEQALGTNEQshowMIPSCondCodec.ngt.dadd.dmul.ddiv.dmadd.dmsub.dmadd.smsub.sadd.ssub.smul.sdiv.ssqrt.ssqrt.dabs.sabs.dneg.sneg.dmov.smov.dround.w.sround.w.dround.l.dfloor.w.sfloor.w.dcvt.d.wcvt.d.lcvt.d.scvt.s.dcvt.s.wcvt.w.srint.srint.dcvt.w.dcvt.l.dcvt.l.strunc.w.dtrunc.w.strunc.l.dtrunc.l.sceil.w.sceil.w.dceil.l.sceil.l.dc.un.dc.eq.dc.lt.dsub.dUnknown op: %dshowMIPSFpOpmfc1dmfc1mtc1dmtc1showMIPSFpGpMoveOpsel.dmovn.smovnseleqzselnezsel.smovn.dshowMIPSFpMoveCondOpdopyMIPSAModenextMIPSAModeFloatnextMIPSAModeInt0(%d(), ppMIPSAModeimm16 != 0x8000%d%uppMIPSRHdclzclonopdcloclzshowMIPSUnaryOpsubusltiadduandorinorxordadddsubdsubidaddiuxoriorandiaddiusltimmR == FalseshowMIPSAluOpdsrasrlvdsrldsllvsrlsllvsllsradsravsravdslldsrlvshowMIPSShftOpmsubmaddumaddmsubushowMIPSAccOpldstshowMsaMI10opmove.vcfcmsacopy_ucopy_ssldiinsveinsertctcmsashowMsaElmOpfillpcntnlocnlzcshowMsa2ROprotx32rotx64showRotxOpflog2ftrunc_sffint_sffint_ufsqrtfrsqrtfrcpfexuprftint_uftint_sftrunc_ushowMsa2RFOpvshfmax_uaver_uclt_usubs_sadd_amax_sadds_uilvlsplatsubs_uceqclt_silvoddivsmin_silvevmin_uaddvaver_silvrdivusldsubvmulvadds_sshowMsa3ROpnor.vor.vand.vxor.vshowMsaVecOpsrlisraisat_ssllisrarishowMsaBitOpfexdofmulfmsubfmaddfcltfmaxfcunfdivfaddfclemul_qftqfmin_afceqfsubfminfexp2mulr_qshowMsa3RFOp0 == (argiregs & ~mask)is_sane_RetLoc(rloc)mode64sz == 4 || sz == 8udmultmultsfastslowxscscdmtlrmflrli ,0x%016llx%s ,rotx word_compare = %s ( )mul %s%s i->Min.Ext.pos < 32i->Min.Ext.size > 0i->Min.Ext.size <= 32dext , %u, %umulmuhu dmuldmuhmthi mtlo mfhi mflo ddivmoddmodddivcall: if (%s) { addiu $29, $29, -16 ; jarl $31, $25; # args [$%d] nop; addiu $29, $29, 16; ](xDirect) if (guest_COND.%s) { move $9, 0x%x,; sw $9, (xIndir) if (guest_COND.%s) { sw (xAssisted) sw l%c%s s%c%s ll cas: , 0() movn end:sc lwc1 swc1 ldc1 sdc1 ctc1 , $31cfc1 (evCheck) lw $9, ; addiu $9, $9, -1; bgez $t9, nofail; jalr *; nofail:%s.%c , (%d)move.v [%u][%u], [0]cfcmsa , $1ctcmsa $1, , %d ppMIPSInstrllbne , end nop , 1 lldaddRegUsage_MIPSRHgetRegUsage_MIPSInstrmapRegs_MIPSRHmapRegs_MIPSInstroffsetB >= 0!hregIsVirtual(rreg)!mode64nbuf >= 32srcR->Mrh.Imm.synedsrcR->Mrh.Imm.imm16 != 0x8000!srcR->Mrh.Imm.syned!immRrDF < 0x04opc < 0x10rWD < 0x20s10 < 0x400ws < 0x20wd < 0x20op < 0x3800040df < 0x40wt < 0x20op < 0x20op < 0x3C0001Dsz32n >= 0 && n <= 32n >= 0 && n < 32delta >= 20 && delta <= 32delta > 0 && delta < 40disp_cp_xindir != NULLr_src < 0x20!(*is_profInc) => emit_MIPSInstrp - &buf[0] <= 1280 == (3 & (HWord)p)sizeof(ULong*) == 4$w0$w1$w2$w3$w4$w5$w6$w7$w8$w9$w10$w11$w12$w13$w14$w15$w16$w17$w18$w19$w20$w21$w22$w23$w24$w26$w27$w28$w29$w30$w31$d0$d1$d2$d3$d4$d5$d6$d7$d8$d9$d10$d11$d12$d13$d14$d15$f0$f1$f2$f3$f4$f5$f6$f7$f8$f9$f10$f11$f12$f13$f14$f15$f16$f17$f18$f19$f20$f21$f22$f23$f24$f25$f26$f27$f28$f29f30$f31$0$1$2$3$4$5$6$7$8$9$10$11$12$13$14$15$16$17$18$19$20$21$22$23$24$25$26$27$28$29$30$31%32%33%34rc >= HRcInt32 && rc <= HrcLASThregClass(r) == (mode64 ? HRcInt64 : HRcInt32)hregClass(reg) == HRcInt32 || hregClass(reg) == HRcInt64 || hregClass(reg) == HRcFlt32 || hregClass(reg) == HRcFlt64 || hregClass(reg) == HRcVec128syned == True || syned == Falsesz == 1 || sz == 2 || sz == 4 || sz == 8; move $9, $disp_cp_chain_me_to_%sEP; jalr $9; nop}; move $9, $disp_indir; jalr $9; nop}; move $9, $IRJumpKind_to_TRCVAL(%d); move $9, $disp_assisted; jalr $9; nop; }(profInc) move $9, ($NotKnownYet); ld $8, 0($9); daddiu $8, $8, 1; sd $8, 0($9); (profInc) move $9, ($NotKnownYet); lw $8, 0($9); addiu $8, $8, 1; sw $8, 0($9); sltiu $1, $8, 1; lw $8, 4($9); addu $8, $8, $1; sw $8, 4($9); 0 == (argir & ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11)))genSpill_MIPS: unimplemented regclassgenReload_MIPS: unimplemented regclassgenMove_MIPS: unimplemented regclass(n >= 0 && n < 32) || (n > 31 && n < 64)disp_cp_chain_me_to_slowEP != NULLdisp_cp_chain_me_to_fastEP != NULLi->Min.XDirect.cond != MIPScc_NVi->Min.XIndir.cond != MIPScc_NVi->Min.XAssisted.cond != MIPScc_NVemit_MIPSInstr.Min_XAssisted: unexpected jump kind0 == (am_addr->Mam.IR.index & 3)evCheckSzB_MIPS() == (UChar*)p - (UChar*)p0endness_host == VexEndnessLE || endness_host == VexEndnessBEisLoadImm_EXACTLY2or6(p, 9, (UInt)(Addr)disp_cp_chain_me_EXPECTED, mode64)fetch32(p + (mode64 ? 24 : 8) + 0) == 0x120F809isLoadImm_EXACTLY2or6(p, 9, (Addr)place_to_jump_to_EXPECTED, mode64)isLoadImm_EXACTLY2or6((UChar *)p, 9, mode64 ? 0x6555655565556555ULL : 0x65556555, mode64)fetch32(p + 24 + 0) == 0xDD280000 bhwdpatchProfInc_MIPSunchainXDirect_MIPSisLoadImm_EXACTLY2or6chainXDirect_MIPSmkFormImkFormRdo_load_or_store_machine_worddo_load_or_store_word32fregNoiregNodregNomkFormSdoAMode_RRdoAMode_IRmkMoveRegmkLoadImmmkForm3RFqregEncmkFormBITmkFormVECmkForm3RmkFormELMmkFormMI10emit_MIPSInstrgenReload_MIPSgenSpill_MIPSgetRegUsage_MIPSInstrppMIPSInstrMIPSInstr_FpLdStMIPSInstr_StoreCMIPSInstr_CasMIPSInstr_LoadLMIPSInstr_StoreMIPSInstr_LoadMIPSInstr_CallAlwaysMIPSInstr_CallshowMIPSAluOpMIPSRH_ImmhregClassppHRegMIPS1GNUzRx FP J 8_DU G T_DU G poDj B 4WADG \ DCI G FAE 4^ADG h AAJ O AAA DG E (AAG@b AAA D_DU G ` tFr H DBAC d ABC  ABE k ABB D A  A ,D A $B VAwB @BBB B(A0A8D@HKPKHA@fH_PUHB@[ 8A0A(B BBBI DHKPKHA@HJPOHA@` HbPJ HKPTHG@zHBPWHB@]HBP<pD A K E G L B VAOB H$(FBB B(A0A8FPX 8H0A(B BBBC pNzEk E 5Ey2m2mHx H m A 4THz A PTHz A 4lEAG n CAI g JAF H I /j$NRqk E  E uiDVHy G Y G K E Y G Y G Q G Y G Y A \TLtKa5iyeY-a eY8EyLuid|3n9t=x5pB}5p6q8sB}0=xD=xX:ulB} HY G p H HS E p H :u6q9tHZ F  HZ F <HN J XH_ I tHN J /j/j/j/j3ntH I  5p$ 8s8 <wL 5p` 8st 8s /j /j 5p 8s 4o ,g <w 8s( 8s< <wP 8sd <wx <w 8s @{ FBB A(A0g (A BBBE 9 (C BBBO m (C BBBJ  (H BBBN 2 (C BBBE  (A BBBH  (A BBBD |h FBB B(D0A8F`c 8D0A(B BBBI  8A0A(B BBBE  8D0A(B BBBO t FAD X ABJ h ABE f ABG Z ABC v ABG k ABA _ ABO 4` zE A s A s A x A z D 4 /E A o A o A Q D s A  Kp E t @FBB B(A0A8DP 8A0A(B BBBG >XN``XAPXH`UXGPXH`nXAPVXH`UXBPXH`WXBPXG`rXAP XG`uXEPmXF`QXAPXG`vXEPmXH`PXBP]XH`YXBP%XK`RXBPYXG`QXAP_XH`SXBP[XH`XXBPFXK`QXAPzXH`TXAPXJ`OXBP]XN`JXBP`XH`PXBP^XH`UXAPHXG`qXBPNXG`PXAPhXJ`JXAPFXJ`LXAPnXK`HXBP}XM`LXAPXK`QXAPOXK`PXBPOXK`QXBPOXI`NXAPOXK`TXBPiXH`VXBPyXH`QXGPsXH`VXAPsXG`QXAPpXH`UXBPpXH`VXBPlXH`UXEP|XH`VXBPiXH`[XAPcXH`UXAPiXH`UXAPiXH`UXBPiXH`VXBPiXH`VXAPiXH`YXBP[XH`UXBP^XG`WXAP^XH`YXBP[XG`WXBP^XG`\XAPXXH`UXBP^XG`WXBP^XG`VXAPOXJ`hXBPOXJ`RXBPLXJ`gXBPOXJ`OXAPOXJ`kXBPOXJ`mXAPXG`xXAPmXH`PXBPXM`GXAP\XG`WXBPfXM`GXBPfXL`FXAPfXL`FXAPfXL`FXAPfXM`GXBP\XG`WXGPbXJ`LXAPUXH`YXBPeXL`OXGPbXJ`LXAPbXJ`LXAP`XL`FXAPfXM`GXBP[XH`YXBPXXH`YXBPXXH`YXBPYXG`WXGPbXJ`LXAP`XM`GXBPeXM`GXBPfXM`GXBP\XG`WXGPbXJ`LXAP`XL`FXAPCXH`UXBPXH`TXEPuXH`WXAP[XK`LXBPYXK`HXBPcXM`QXBPWXK`OXBPhXK`OXAPSXK`OXBPYXJ`OXAPYXK`NXBPXG`wXBPXH`fXAPRXJ`TXAP[XJ`LXAPWXK`KXBPTXK`KXEPTXK`LXBP|XK`QXAPNXK`QXAPNXK`KXBPUXK`LXBPMXK`LXBPXG`NXAPmXJ`JXBPOXK`OXBPLXK`LXBPOXJ`JXBPOXJ`IXAPfXG`ZXAPqXH`ZXAPIXK`QXAPIXJ`IXAPOXK`LXAPfXH`ZXBPe XJ`NXAPMXJ`OXBPMXK`LXEPJXJ`NXGP zRx P( EAJEAJEAJ p"_*( CP_Jcokh W^0`_'@ SZ s P   &1 J@ph P      2 KVx o` P @ 0     7 P i   ` p P 0 @ # < U iP  )3=GYaw   "(U.:4:W@iFL{RXP^djpv|81*j!` V~t$*06<BHNTZ`PfJlDr>x8~2+$ ?ETafqlw %,3:AHOV]dk ry&),G>:B5K`e[jnr   v ! z( / 6 = D K R Y ` g n u |         % 6 3 9 n U G u N h c \ |   $ + 2 9 @ G N U \ c j q x       8 ? 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0mkFormR__PRETTY_FUNCTION__.6036qregEnc__PRETTY_FUNCTION__.6008dregNo__PRETTY_FUNCTION__.6003mkFormI__PRETTY_FUNCTION__.6025addRegUsage_MIPSAModemapRegs_MIPSAModemkFormS.constprop.0__PRETTY_FUNCTION__.6047isLoadImm_EXACTLY2or6.constprop.0__PRETTY_FUNCTION__.6180fregNo.constprop.0__PRETTY_FUNCTION__.5998mkHReg.constprop.0iregNo__PRETTY_FUNCTION__.3585__PRETTY_FUNCTION__.5992mkLoadImm_EXACTLY2or6mkLoadImm__PRETTY_FUNCTION__.6160do_load_or_store_word32.constprop.0__PRETTY_FUNCTION__.6213__PRETTY_FUNCTION__.6142doAMode_IRdoAMode_RR__PRETTY_FUNCTION__.6153do_load_or_store_machine_word__PRETTY_FUNCTION__.6197rRegUniverse_MIPS_initted.4968rRegUniverse_MIPS.4967fvec128_names.4979ireg32_names.4976__PRETTY_FUNCTION__.4980freg32_names.4977freg64_names.4978__PRETTY_FUNCTION__.5146__PRETTY_FUNCTION__.5195CSWTCH.388__PRETTY_FUNCTION__.5473__PRETTY_FUNCTION__.5482__PRETTY_FUNCTION__.5510__PRETTY_FUNCTION__.5518__PRETTY_FUNCTION__.5526__PRETTY_FUNCTION__.5536__PRETTY_FUNCTION__.5544__PRETTY_FUNCTION__.5573__PRETTY_FUNCTION__.5743__PRETTY_FUNCTION__.5866__PRETTY_FUNCTION__.5955__PRETTY_FUNCTION__.5971__PRETTY_FUNCTION__.6241CSWTCH.476__PRETTY_FUNCTION__.6069__PRETTY_FUNCTION__.6058__PRETTY_FUNCTION__.6089__PRETTY_FUNCTION__.6109__PRETTY_FUNCTION__.6098__PRETTY_FUNCTION__.6122__PRETTY_FUNCTION__.6226emit_MIPSInstr.cold__PRETTY_FUNCTION__.6665__PRETTY_FUNCTION__.6676__PRETTY_FUNCTION__.6686.LC0.LC1.LC2.LC3.LC4.LC5.LC6.LC7.LC8.LC9.LC10.LC11.LC12.LC13.LC14.LC15.LC16.LC17.LC18.LC19.LC20.LC23.LC22.LC21.LC24.LC25.LC28.LC27.LC29.LC26.LC33.LC32.LC43.LC35.LC36.LC37.LC38.LC34.LC30.LC40.LC39.LC42.LC31.LC41.LC44.LC45.LC91.LC90.LC89.LC77.LC76.LC67.LC72.LC88.LC87.LC86.LC85.LC70.LC66.LC65.LC69.LC68.LC81.LC82.LC83.LC84.LC79.LC80.LC71.LC75.LC78.LC74.LC73.LC64.LC63.LC62.LC61.LC60.LC59.LC58.LC57.LC56.LC55.LC54.LC53.LC48.LC46.LC52.LC51.LC50.LC49.LC47.LC92.LC93.LC94.LC95.LC96.LC98.LC97.LC99.LC102.LC106.LC103.LC104.LC101.LC105.LC100.LC107.LC108.LC109.LC110.LC114.LC111.LC113.LC112.LC115.LC117.LC116.LC118.LC119.LC120.LC125.LC123.LC122.LC124.LC121.LC126.LC128.LC142.LC141.LC129.LC127.LC140.LC130.LC131.LC139.LC132.LC143.LC138.LC133.LC137.LC134.LC136.LC135.LC144.LC157.LC149.LC147.LC151.LC155.LC152.LC145.LC154.LC153.LC150.LC148.LC146.LC156.LC161.LC158.LC159.LC160.LC162.LC164.LC163.LC165.LC172.LC168.LC166.LC173.LC167.LC171.LC170.LC169.LC174.LC176.LC178.LC175.LC177.LC179.LC181.LC180.LC182.LC184.LC187.LC188.LC189.LC183.LC190.LC192.LC191.LC186.LC185.LC193.LC194.LC199.LC200.LC204.LC211.LC220.LC201.LC208.LC218.LC214.LC203.LC216.LC210.LC202.LC196.LC197.LC198.LC209.LC215.LC205.LC212.LC207.LC195.LC217.LC219.LC206.LC213.LC221.LC224.LC223.LC225.LC222.LC226.LC229.LC231.LC230.LC227.LC228.LC232.LC243.LC238.LC237.LC246.LC250.LC244.LC239.LC249.LC240.LC242.LC241.LC245.LC233.LC247.LC236.LC248.LC234.LC235.LC251.LC253.LC252.LC255.LC254.LC256.LC271.LC272.LC351.LC341.LC269.LC270.LC273.LC282.LC283.LC350.LC344.LC342.LC334.LC333.LC292.LC291.LC290.LC268.LC267.LC339.LC340.LC335.LC336.LC310.LC337.LC338.LC315.LC308.LC316.LC317.LC318.LC312.LC313.LC314.LC307.LC309.LC262.LC263.LC311.LC299.LC300.LC301.LC303.LC304.LC296.LC286.LC295.LC261.LC258.LC284.LC327.LC277.LC274.LC275.LC276.LC257.LC260.LC259.LC278.LC332.LC264.LC320.LC319.LC293.LC321.LC322.LC352.LC323.LC324.LC353.LC354.LC355.LC356.LC265.LC325.LC326.LC343.LC349.LC305.LC306.LC287.LC288.LC297.LC302.LC357.LC266.LC328.LC329.LC294.LC285.LC289.LC298.LC330.LC331.LC345.LC346.LC347.LC348.LC279.LC280.LC281.LC360.LC359.LC358.LC362.LC361.LC363.LC364.LC366.LC365.LC367.LC368.LC402.LC403.LC369.LC404.LC400.LC397.LC373.LC378.LC374.LC390.LC401.LC380.LC394.LC381.LC375.LC391.LC382.LC379.LC376.LC396.LC395.LC393.LC383.LC377.LC392.LC389.LC385.LC384.LC399.LC388.LC386.LC371.LC370.LC387.LC398.LC372.LC409.LC406.LC407.LC408.LC410.LC413.LC411.LC412_GLOBAL_OFFSET_TABLE_vex_printfvex_assert_failaddHRegUsevpaniclookupHRegRemapgetRRegUniverse_MIPSRRegUniverse__initRRegUniverse__check_is_saneppHRegMIPSppHRegshowMIPSCondCodeshowMIPSFpOpshowMIPSFpGpMoveOpshowMIPSMoveCondOpMIPSAMode_IRprivate_LibVEX_alloc_currprivate_LibVEX_alloc_lastprivate_LibVEX_alloc_OOMMIPSAMode_RRdopyMIPSAModenextMIPSAModeFloatnextMIPSAModeIntppMIPSAModeMIPSRH_ImmMIPSRH_RegppMIPSRHshowMIPSUnaryOpshowMIPSAluOpshowMIPSShftOpshowMIPSMaccOpshowMsaDFshowMsaDFFshowMsaMI10opshowMsaElmOpshowMsa2ROpshowRotxOpshowMsa2RFOpshowMsa3ROpshowMsaVecOpshowMsaBitOpshowMsa3RFOpMIPSInstr_LIMIPSInstr_AluMIPSInstr_ShftMIPSInstr_UnaryMIPSInstr_CmpMIPSInstr_MulMIPSInstr_MultMIPSInstr_ExtMIPSInstr_Mulr6MIPSInstr_MsubMIPSInstr_MaddMIPSInstr_DivMIPSInstr_Divr6MIPSInstr_CallMIPSInstr_CallAlwaysMIPSInstr_XDirectMIPSInstr_XIndirMIPSInstr_XAssistedMIPSInstr_LoadMIPSInstr_StoreMIPSInstr_LoadLMIPSInstr_CasMIPSInstr_StoreCMIPSInstr_MthiMIPSInstr_MtloMIPSInstr_MfhiMIPSInstr_MfloMIPSInstr_RdWrLRMIPSInstr_FpLdStMIPSInstr_FpUnaryMIPSInstr_FpBinaryMIPSInstr_FpTernaryMIPSInstr_FpConvertMIPSInstr_FpCompareMIPSInstr_FpMinMaxMIPSInstr_MtFCSRMIPSInstr_MfFCSRMIPSInstr_FpGpMoveMIPSInstr_MoveCondMIPSInstr_EvCheckMIPSInstr_ProfIncMIPSInstr_MsaMi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hregIsInvalid(env->vregmapHI[tmp])e->Iex.Const.con->tag == Ico_U64typeOfIRExpr(env->type_env, e->Iex.ITE.cond) == Ity_I1iselInt64Expr(mips): No such tag(%u) doHelperCall(MIPS): cannot currently handle > 4 or 8 argsnVECRETs == ((retTy == Ity_V128 || retTy == Ity_V256) ? 1 : 0)ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32 || ty == Ity_I1 || ty == Ity_F32 || (ty == Ity_I64 && mode64) || (ty == Ity_I128 && mode64)ri->Mrh.Imm.imm16 >= 1 && ri->Mrh.Imm.imm16 <= 31hregClass(ri->Mrh.Reg.reg) == HRcInt32hregIsVirtual(ri->Mrh.Reg.reg)iselIntExpr_RH5u: unknown mips RH tagiselCondCode(mips): CmpXX32 or CmpXX64iselWordExpr_R(mips): cannot reduce treehregClass(r) == HRcGPR(env->mode64)ri->Mrh.Imm.imm16 >= 1 && ri->Mrh.Imm.imm16 <= 63hregClass(ri->Mrh.Reg.reg) == HRcGPR(env->mode64)iselIntExpr_RH6u: unknown RI tagty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32 || ((ty == Ity_I64) && env->mode64)iselIntExpr_RH.Iex_Const(mips)iselIntExpr_RH: unknown mips RH tagtypeOfIRExpr(env->type_env, e) == Ity_I128iselInt128Expr(mips64): No such tag(%u) hregClass(*rHi) == HRcGPR(env->mode64)hregClass(*rLo) == HRcGPR(env->mode64)ri->Mrh.Imm.imm16 >= 1 && ri->Mrh.Imm.imm16 <= 127iselIntExpr_RH7u: unknown RI tagsane_AMode: unknown mips amode tagiselDblExpr(mips): No such tag(%u) ty == Ity_F32 || (ty == Ity_F64 && fp_mode64)e->Iex.Load.ty == Ity_F32 || (e->Iex.Load.ty == Ity_F64 && fp_mode64)iselFltExpr(mips): No such tag(0x%x) iselV128Expr_wrk: Unsupported unop: %u e->Iex.Binop.arg2->tag == Iex_Conste->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U8e->Iex.Binop.arg2->Iex.Const.con->Ico.U8 <= 63iselV128Expr_wrk: unsupported binop: %x iselV128Expr_wrk: unsupported triop: %x iselV128Expr_wrk: Unsupported tag: %x typeOfIRExpr(env->type_env, e) == Ity_I1iselCondCode(mips): No such tag(%u) (rloc.spOff < 512) && (rloc.spOff > -512)iselStmt(mips32): Ist_Exit: dst is not a 32-bit valueiselStmt(mips64): Ist_Exit: dst is not a 64-bit valuearch_host == VexArchMIPS32 || arch_host == VexArchMIPS64VEX_PRID_COMP_MIPS == VEX_MIPS_COMP_ID(hwcaps_host) || VEX_PRID_COMP_CAVIUM == VEX_MIPS_COMP_ID(hwcaps_host) || VEX_PRID_COMP_BROADCOM == VEX_MIPS_COMP_ID(hwcaps_host) || VEX_PRID_COMP_NETLOGIC == VEX_MIPS_COMP_ID(hwcaps_host) || VEX_PRID_COMP_INGENIC_E1 == VEX_MIPS_COMP_ID(hwcaps_host) || VEX_PRID_COMP_LEGACY == VEX_MIPS_COMP_ID(hwcaps_host)archinfo_host->endness == VexEndnessLE || archinfo_host->endness == VexEndnessBEcdst->tag == (env->mode64 ? Ico_U64 :Ico_U32)iselNextiselWordExpr_RiselWordExpr_RH5u_wrkiselWordExpr_RH5uiselWordExpr_R_wrkiselCondCode_wrkiselCondCodelookupIRTempmk_iMOVds_RRiselWordExpr_AMode_wrkiselWordExpr_AModeadd_to_splookupIRTemp64doHelperCalliselWordExpr_RH7u_wrkiselWordExpr_RH7uiselV128Expr_wrkiselV128ExpriselDblExpriselDblExpr_wrkmk_LoadRR32toFPRiselFltExpr_wrkiselFltExprlookupIRTempPairiselInt128Expr_wrkiselInt128ExprhregClassiselWordExpr_RH_wrkiselWordExpr_RHiselWordExpr_RH6u_wrkiselWordExpr_RH6uiselInt64Expr_wrkiselInt64ExpriselStmtmkHRegiselSB_MIPSGNUzRx oD\ P 8%AA^ TWAe J Y G (xDDJ n IGH ;\;\StSt(AG S AD s JK @ BED G0  AABA   JABH 4dAAD  AAI k JAJ 4gAEG0 AAK { JAJ @BBI A(C0I@ 0D(A BBBB 47AEG0 AAK S JAJ \Pt<BBB B(A0A8D 8A0A(B BBBK  ZNBL BEB B(A0A8J 8A0A(B BBBA tZ3BBE B(A0D8DDRAM 8A0A(B BBBF + 8A0A(B BBBC xAm B (ADG  AAC XBBB A(A0K@. 0A(A BBBG  0J(A BBBL ,BDD  ABC XLmBBB A(A0K@ 0A(A BBBG S 0J(A BBBL HBBB B(A0A8DP 8A0A(B BBBG (ADG  AAC 8 BBD D(F0  (A ABBK `\BBB B(D0D8D` 8A0A(B BBBA Z 8A0A(B BBBD Db J |BBE B(A0D8D` 8A0A(B BBBJ  8A0A(B BBBA 8 8A0A(B BBBF H\QBBB B(A0A8D` 8A0A(B BBBG HBBB B(A0A8DP2 8D0A(B BBBC 4BBB B(D0D8DpPxTOxBp 8A0A(B BBBA V 8A0A(B BBBH xWJxApHxFHB B(A0A8D@ 8A0A(B BBBA o!p%<x UW er(  ;;@SS 4gR c| 7 t<PQ`m`-`H M_0k` h TZ30@!0Ibnp`@6H0azx  *h CP\Pu@!4~   '0F[ H]u % +17=C'I;OWU [HagmskyOe 6(`w8 P!'x-39?HEKQxW]ciou{(P[B :{xqh@( P%-,3: A2HNO~Vg]dkryH  @       " / > O _ p            . = M \ j q z          1 ? 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