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1750 ` libvex_x86_linux_a-main_globals.o/ libvex_x86_linux_a-main_main.o/ libvex_x86_linux_a-main_util.o/ libvex_x86_linux_a-ir_defs.o/ libvex_x86_linux_a-ir_inject.o/ libvex_x86_linux_a-ir_match.o/ libvex_x86_linux_a-ir_opt.o/ libvex_x86_linux_a-guest_generic_bb_to_IR.o/ libvex_x86_linux_a-guest_generic_x87.o/ libvex_x86_linux_a-guest_x86_helpers.o/ libvex_x86_linux_a-guest_x86_toIR.o/ libvex_x86_linux_a-guest_amd64_helpers.o/ libvex_x86_linux_a-guest_amd64_toIR.o/ libvex_x86_linux_a-guest_ppc_helpers.o/ libvex_x86_linux_a-guest_ppc_toIR.o/ libvex_x86_linux_a-guest_arm_helpers.o/ libvex_x86_linux_a-guest_arm_toIR.o/ libvex_x86_linux_a-guest_arm64_helpers.o/ libvex_x86_linux_a-guest_arm64_toIR.o/ libvex_x86_linux_a-guest_s390_helpers.o/ libvex_x86_linux_a-guest_s390_toIR.o/ libvex_x86_linux_a-guest_mips_helpers.o/ libvex_x86_linux_a-guest_mipsdsp_toIR.o/ libvex_x86_linux_a-guest_mips_toIR.o/ libvex_x86_linux_a-host_generic_regs.o/ libvex_x86_linux_a-host_generic_simd64.o/ libvex_x86_linux_a-host_generic_simd128.o/ libvex_x86_linux_a-host_generic_simd256.o/ libvex_x86_linux_a-host_generic_maddf.o/ libvex_x86_linux_a-host_generic_reg_alloc2.o/ libvex_x86_linux_a-host_generic_reg_alloc3.o/ libvex_x86_linux_a-host_x86_defs.o/ libvex_x86_linux_a-host_x86_isel.o/ libvex_x86_linux_a-host_amd64_defs.o/ libvex_x86_linux_a-host_amd64_isel.o/ libvex_x86_linux_a-host_ppc_defs.o/ libvex_x86_linux_a-host_ppc_isel.o/ libvex_x86_linux_a-host_arm_defs.o/ libvex_x86_linux_a-host_arm_isel.o/ libvex_x86_linux_a-host_arm64_defs.o/ libvex_x86_linux_a-host_arm64_isel.o/ libvex_x86_linux_a-host_s390_defs.o/ libvex_x86_linux_a-host_s390_isel.o/ libvex_x86_linux_a-s390_disasm.o/ libvex_x86_linux_a-host_mips_defs.o/ libvex_x86_linux_a-host_mips_isel.o/ /0 0 0 0 644 812 ` ELF4(  GNU  $+(9,J0vex_controlvex_traceflagsvex_debuglevelvex_log_bytesvex_failure_exitvex_initdone.symtab.strtab.shstrtab.text.data.bss.note.GNU-stack.note.gnu.property4!4'@1 ,@<@\ WsO/35 0 0 0 644 41228 ` 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NEON instructions are not supported for ARMv6. NEON and VFP3 are required for ARMv8. ARM architecture level is not supported. Unsupported hardware capabilities. Host does not have long displacement facility. Fatal: unknown arch in arch_word_size vcon->iropt_unroll_thresh >= 0vcon->iropt_unroll_thresh <= 400vcon->guest_chase_thresh < vcon->guest_max_insnsvcon->guest_chase_cond == True || vcon->guest_chase_cond == Falsevcon->regalloc_version == 2 || vcon->regalloc_version == 3vta->disp_cp_xassisted != NULLvta->disp_cp_chain_me_to_fastEP != NULLvta->disp_cp_chain_me_to_fastEP == NULLvta->archinfo_guest.endness == VexEndnessLEvta->archinfo_guest.endness == VexEndnessBE0 == sizeof(VexGuestPPC32State) % LibVEX_GUEST_STATE_ALIGNvta->archinfo_guest.endness == VexEndnessBE || vta->archinfo_guest.endness == VexEndnessLE0 == sizeof(VexGuestPPC64State) % LibVEX_GUEST_STATE_ALIGN0 == sizeof(VexGuestARM64State) % LibVEX_GUEST_STATE_ALIGNvta->archinfo_guest.endness == VexEndnessLE || vta->archinfo_guest.endness == VexEndnessBELibVEX_Translate: unsupported guest insn setvta->archinfo_guest.hwcaps == vta->archinfo_host.hwcapsvta->archinfo_guest.endness == vta->archinfo_host.endness ------------------------ Front end ------------------------ *pxControl >= VexRegUpdSpAtMemAccess && *pxControl <= VexRegUpdAllregsAtEachInsnvta->guest_extents->n_used >= 1 && vta->guest_extents->n_used <= 3vta->guest_extents->base[0] == vta->guest_bytes_addrvta->guest_extents->len[i] < 10000can't show code due to extents > 1 ------------------------ After pre-instr IR optimisation ------------------------ ------------------------ After instrumentation ------------------------ after post-instrumentation cleanup ------------------------ After post-instr IR optimisation ------------------------ LibVEX_Codegen: unsupported guest insn setvta->archinfo_host.endness == VexEndnessLEvta->archinfo_host.endness == VexEndnessBEvta->archinfo_host.endness == VexEndnessBE || vta->archinfo_host.endness == VexEndnessLEvta->archinfo_host.endness == VexEndnessLE || vta->archinfo_host.endness == VexEndnessBELibVEX_Translate: unsupported host insn set ------------------------ After tree-building ------------------------ ------------------------ Instruction selection ------------------------ ------------------------ Register-allocated code ------------------------ ------------------------ Assembly ------------------------ VexExpansionRatio %d %d %d :10 Encountered an instruction that requires the vector facility. That facility is not available on this hostSelection of non-80-bit x87 FP precisionSetting %mxcsr.fz (SSE flush-underflows-to-zero mode)Setting %mxcsr.daz (SSE treat-denormals-as-zero mode)Setting %eflags.ac (setting noted but ignored)Unmasking PPC32/64 FP exceptionsPPC64 function redirection stack overflowPPC64 function redirection stack underflowThe specified rounding mode cannot be supported. That feature requires the floating point extension facility which is not available on this host. Continuing using the rounding mode from FPC. Results may differ!The specified rounding mode is invalid. Continuing using 'round to nearest'. Results may differ!Instruction stfle is not supported on this hostInstruction stckf is not supported on this hostInstruction ecag is not supported on this hostInstruction pfpo is not supported on this hostDFP instructions are not supported on this hostEncountered an instruction that requires the floating point extension facility. That facility is not available on this hostThe rounding mode in GPR 0 for the PFPO instruction is invalidThe function code in GPR 0 for the PFPO instruction is invalidLibVEX_EmNote_string: unknown warning$Ë $Ë$ GNUzR| 0vAF CAN$ (A,A0E (G,G0A4H$c(G,A0H$L(G,M0H$D(D,A0H$Z(G,M0L$o(D,A0H$^(G,A0H$R(G,A0H$I(D,A0H$T(G,A0H$Z(G,A0H$G(D,A0H$K(D,A0H$](G,A0H$L(G,A0P$N(G,A0H$zR| $$\dLF AAC AA AAA  AA AAC Q E $p 7AR LKAG , VEA QAzA AA\0 EA AyFA  AAG G KAG F G KAG F G KAG F G KAG F G KAG F G KAG F G KAG F G KAG F G KAG F G KAG F G KAG F G KAG F G KAG F G KAG F G KAG F G KAG F G KAG F G KAG F G KAG F GKAG 0Z EA AANHG LKPATGXH LDPDTDXF\F`DdAhDlBpHtFxF|FFDCGADFHHc LKPATGXJ p LKPATGXE T LKPATGXI T LKPATGXI w LKPATGXF GLFHR LKPATGXN G LKPATGXF rLFHILBPATAXL\F`FdDhDlApHHeLDPATFXD\A`CdGHVLDPATFXD\A`CdGHXLFPFTQXB\A`AdHHU CA AAG G LKPATGXF WLFPLTHHVLFPLTHHVLFPLTHHV LKPATGXF G LKPATGXF GLEPGTGXFHG LKPATGXF G LKPATGXF G LKPATGXF G LKPATGXF QLHPATLHtLFPFLAHWLAPFLAHV LEPE GLEPGTGXEHGLEPGTGXEHG LEPB GLEPGTGXEHG LEPB G LEPB A LEPB A LEPE A LKPATGXE LLD EA AAQtEAH KAGO DAHMEeHFGDADCAIAJAFFFCDAEDDIEGGHT EG T EG TEGGI KAGL TEGGIG KAGN NAJAYFxDICMHPJQFpDFAWFW CA AAD DAJHDFpDHCMHPFLFRFLLR KAGN G KAGF cAAAHa KAGN G KAGF G KAGF G KAGF G KAGF G KAGF V EE G EE G EE G E G KAGE G8 p%EA vDDDA EE A AC GEGGE G EB G EB G EB G EB G EB G EB G EB GE `&EA vDDDA EE A AC GEGGE G EB G EB G EB G EB G EB G EB G EB GEtX P'EV E j A G EGGEG  EB G  EB G  EB G  EB G  EB G  EB G  EB G E 0(EA vDDAEE A AC GEGGE G EB G EB G EB G EB G EB G EB G EB GE\ )Er I G I G I G I G I G I G I G I G I G I G I G I G I G I G I G I G I G I G I G I G A G  * +G(0 +EA AAN  AA AAG \$G(A,H K$D(A,H k$G(G,A0H b$G(A,H \ AA AAH `$G(A,H O$D(A,H l$G(A,H R$D(A,H g AA AAF M$G(A,H Q$D(A,H M$G(M,H v$D(A,H `$G(A,H h$G(A,H `$G(A,H zR|  $, 1oEA QASA AA, 2?EA QAcA AA  v -!`W+|5S?EI [SP `8 r @x 0   `H  <   `  !. ;p 7Q k ~0    t d  T  @ ', A Y^ ciouzew0T@< 4    l d     8 R !  '0 - 3 9 ? E` K< QgWx]cziou{Nd  0    cxD  $  | 4  h B0 \ # )M/ 5T ; AGt M S  Y _ e k3q9w }4  `  l  0   b i`  < Or    D ' . 5 < CT J Q X _ f mh t0 {  ` D (!:,D3D"V'k+/@370=CIpOU@[agmPspy`P h`@hpP0 h 0 !'%--&3&9&?&E%K%Q%W;&]&c'i'o'u&{&&&+'''(('''''h(((((((((*p* `*P*@*0*# *)*/*5);)A)G)M)S)Y)_)ep)k`)qP)w*}**+@+P+`+p+ +0++,--. ..P/,p,   " . D U \ g w V         0Z  , @ O X h u           ) = K V ` k |       p%  `&  P'" 1 0(E V )k *|  +G + 1o 2? sdiv32invalid_hwcapsbuf.13838buf.13852buf.13894buf.13866buf.13880buf.13912prefix.13889hwcaps_list.13893prefix.13847hwcaps_list.13851prefix.13907hwcaps_list.13911prefix.13875hwcaps_list.13879prefix.13833hwcaps_list.13837prefix.13861hwcaps_list.13865invalid_hwcaps.coldcheck_hwcapsextras.13948arch_word_size.part.0__PRETTY_FUNCTION__.13829udiv32.constprop.0__PRETTY_FUNCTION__.13510__PRETTY_FUNCTION__.13536__PRETTY_FUNCTION__.13636__PRETTY_FUNCTION__.13700__PRETTY_FUNCTION__.13718cached.13730__PRETTY_FUNCTION__.13734__PRETTY_FUNCTION__.13751LibVEX_ppVexHwCaps.cold.LC2.LC1.LC13.LC20.LC11.LC0.LC6.LC18.LC16.LC14.LC19.LC7.LC3.LC15.LC17.LC12.LC8.LC10.LC5.LC4.LC9.LC42.LC26.LC36.LC33.LC41.LC31.LC37.LC38.LC22.LC32.LC34.LC30.LC43.LC39.LC29.LC24.LC23.LC40.LC28.LC27.LC25.LC44.LC45.LC46.LC53.LC47.LC48.LC49.LC50.LC51.LC52.LC62.LC54.LC55.LC56.LC57.LC58.LC59.LC60.LC61.LC63.LC64.LC65.LC66.LC73.LC88.LC78.LC76.LC79.LC70.LC84.LC67.LC68.LC89.LC93.LC97.LC69.LC96.LC95.LC94.LC98.LC72.LC71.LC85.LC86.LC87.LC82.LC83.LC90.LC91.LC92.LC75.LC80.LC74.LC77.LC81.LC112.LC103.LC100.LC102.LC101.LC109.LC108.LC110.LC111.LC106.LC105.LC116.LC107.LC113.LC114.LC115.LC104.LC99.LC136.LC135.LC134.LC133.LC132.LC131.LC130.LC129.LC128.LC127.LC126.LC125.LC124.LC123.LC122.LC121.LC120.LC119.LC137.LC118.LC117.LC138.LC149.LC140.LC148.LC141.LC146.LC147.LC142.LC143.LC144.LC145.LC139.LC151.LC150.LC152.L14.L13.L12.L11.L10.L9.L8.L7.L5.L110.L109.L108.L107.L106.L105.L104.L103.L101.L359.L309.L360.L312.L333.L332.L331.L330.L329.L328.L327.L326.L324.L442.L441.L440.L439.L495.L437.L436.L435.L433.L453.L452.L451.L450.L449.L448.L447.L446.L444.L585.L584.L583.L582.L581.L580.L579.L578.L576.L600.L599.L598.L597.L596.L595.L594.L593.L591.L616.L615.L614.L613.L612.L611.L610.L609.L607.L631.L630.L629.L628.L627.L626.L625.L624.L622.L658.L657.L659.L655.L654.L653.L652.L651.L650.L649.L648.L647.L646.L645.L644.L643.L642.L641.L640.L639.L637.L674.L672.L671.L670.L669.L668.L667.L666.L665.L663.L692.L691.L690.L689.L688.L687.L686.L685.L683__x86.get_pc_thunk.bx_GLOBAL_OFFSET_TABLE_vfatalvex_sprintf__x86.get_pc_thunk.cxs390_host_hwcapsvpanicvex_printfvex_assert_failLibVEX_default_VexControlvex_bzeroLibVEX_Initvex_failure_exitvex_initdonevex_log_bytesvex_debuglevelvex_controlvexSetAllocModeLibVEX_FrontEndvexSetAllocModeTEMP_and_clearvexAllocSanityCheckvex_traceflagsbb_to_IRx86guest_layoutdisInstr_X86guest_x86_state_requires_precise_mem_exnsguest_x86_spechelpersanityCheckIRSBdo_iropt_BBdo_deadcode_BBcprop_BBppIRSBLibVEX_Translateado_treebuild_BBdoRegisterAllocation_v2getRRegUniverse_X86emit_X86InstriselSB_X86ppHRegX86ppX86InstrdirectReload_X86genMove_X86genReload_X86genSpill_X86mapRegs_X86InstrgetRegUsage_X86InstrdoRegisterAllocation_v3LibVEX_ChainLibVEX_UnChainunchainXDirect_X86LibVEX_evCheckSzBevCheckSzB_X86LibVEX_PatchProfIncpatchProfInc_X86LibVEX_EmNote_stringLibVEX_ppVexArch__x86.get_pc_thunk.dxLibVEX_ppVexEndnessLibVEX_ppVexHwCapsLibVEX_default_VexArchInfoLibVEX_default_VexAbiInfos390x_vec_op_tH" I7  + , + -    .J % 5 > F /P 0X e m z    1   2K  3K  4 "K7 3= sK   4 K 3K  5 3K% + 2 49KJ d 3K   4K  3    4K. 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= DIRTY -mem(,%d) ::: -gst(%u,%u,reps%u,step%u = CAS%s(::->PUTI,%d] = if () { ST%s() = }ILGop_INVALIDIdentV128Ident64Ident32ppIRLoadGOp = if-strict () (LD%s()) else BoringCallReturnClientReqYieldEmWarnEmFailNoDecodeMapFailInvalICacheFlushDCacheNoRedirSigILLSigTRAPSigSEGVSigBUSSigFPESigFPE_IntDivSigFPE_IntOvfSys_syscallSys_int32Sys_int128Sys_int129Sys_int130Sys_int145Sys_int210Sys_sysenterppIRJumpKindFenceCancelReservationppIRMBusEvent!!! IRStmt* which is NULL !!!IR-NoOp====== AbiHint(, %d, ) ======PUT(%d) = ST%s( = LD%s-Linked( = ( ST%s-Cond( )IR-) { PUT(%d) = ; exit- } ppIRStmt :IRSB { PUT(%d) = } IR SANITY CHECK FAILURE IN STATEMENT: ERROR = %s out of range Temp in IRExpruseBeforeDef_Exprpriv/ir_defs.cbit == False || bit == Truename != NULLaddr != 0!(arr->elemTy == Ity_I1)deepCopyIRConstdeepCopyIRExprdeepCopyIRStmttypeOfPrimopenvenv->types_used >= 0env->types_size >= 0tmp < env->types_usedtypeOfIRConsttypeOfIRLoadGOptypeOfIRExpr op name: op type is () -> arg tys are () Iex.Unop: wrong arity opIex.CCall.cee: bad IRCalleeIex.CCall: > 32 argsIex.CCall.arg: arg :: Ity_I1Iex.Const.con: invalid constIex.ITE.cond: cond :: Ity_I1tcExprisFlatIRStmt(e)isFlatIRStmt(st)IRStmt: is NULLIRStmt: is not flatbb->next is not an atomuseBeforeDef_StmtIRStmt.IMark.len: implausibleIRStmt.CAS: ill-formedIst.LLSC(LL).result :: bogusIRStmt.Dirty.dst :: Ity_I1IRStmt.Dirty: > 32 argsIRStmt.Dirty.arg[i] :: Ity_I1IRStmt.Dirty: ill-formedIRStmt.MBE.event: unknownIRStmt.Exit.dst: bad dstIRStmt.Exit.offsIP: too lowtcStmtbb->next field has wrong typebb->offsIP: too loweqIRConstsizeofIRTypeintegerIRTypeOfSizeisIRAtom(a1)isIRAtom(a2)   eqIRAtomsanityCheckIRSBtypeOfIRTempnewIRTempaddStmtToIRSBIRStmt_StoreGIRStmt_StoreIRExpr_LoadmkIRRegArraymkIRCalleeIRConst_U1------ IMark(0x%lx, %u, %u) ------sanityCheckFail: exiting due to bad IRIRTemp use before def in IRExprIRExprP__* value in CCall arg listregparms >= 0 && regparms <= 3!(arr->base < 0 || arr->base > 10000 )!(arr->nElems <= 0 || arr->nElems > 500 )end == Iend_LE || end == Iend_BEbb->stmts_used < bb->stmts_sizeenv->types_used <= env->types_sizetypeOfIRExpr: Binder is not a valid expressiontypeOfIRExpr: VECRET is not a valid expressiontypeOfIRExpr: GSPTR is not a valid expressionIRExpr.GetI.ix: not :: Ity_I32IRExpr.GetI.descr: invalid descrIex.Qop: wrong arity op ... name of op precedes BB printout Iex.Qop: arg tys don't match op tys ... additional details precede BB printout Iex.Triop: wrong arity op ... name of op precedes BB printout Iex.Triop: arg tys don't match op tys ... additional details precede BB printout Iex.Binop: wrong arity op ... name of op precedes BB printout Iex.Binop: arg tys don't match op tys ... additional details precede BB printout Iex.Unop: arg ty doesn't match op tyIex.Load.addr: not :: guest word typeIex.Load.end: bogus endiannessIex.CCall.cee: #regparms > #argsIex.CCall.args: is VECRET/GSPTRIex.CCall.retty: cannot return :: Ity_I1Iex.ITE: iftrue/iffalse mismatchguest_word_size == Ity_I32 || guest_word_size == Ity_I64sanityCheckIRSB: stmts array limits weirdTemp t%d declared with implausible type 0x%x Temp declared with implausible typeIRStmt.Tmp: destination tmp is out of rangeIRStmt.Tmp: destination tmp is assigned more than onceIRStmt.LoadG: destination tmp is out of rangeIRStmt.LoadG: destination tmp is assigned more than onceIRStmt.Dirty: destination tmp is out of rangeIRStmt.Dirty: destination tmp is assigned more than onceIRStmt.CAS: destination tmpHi is out of rangeIRStmt.CAS: destination tmpHi is assigned more than onceIRStmt.CAS: destination tmpLo is out of rangeIRStmt.CAS: destination tmpLo is assigned more than onceIRStmt.LLSC: destination tmp is out of rangeIRStmt.LLSC: destination tmp is assigned more than onceIRStmt.IMark.delta: implausibleIRStmt.AbiHint.base: not :: guest word typeIRStmt.AbiHint.nia: not :: guest word typeIRStmt.Put.data: cannot Put :: Ity_I1IRStmt.PutI.data: cannot PutI :: Ity_I1IRStmt.PutI.data: data ty != elem tyIRStmt.PutI.ix: not :: Ity_I32IRStmt.PutI.descr: invalid descrIRStmt.Put.Tmp: tmp and expr do not matchIRStmt.Store.addr: not :: guest word typeIRStmt.Store.data: cannot Store :: Ity_I1Ist.Store.end: bogus endiannessIRStmtG...addr: not :: guest word typeIRStmtG...data: cannot Store :: Ity_I1IRStmtG...guard: not :: Ity_I1IRStmtG...end: bogus endiannessIRStmt.LoadG.guard: not :: Ity_I1IRStmt.LoadG.addr: not :: guest word typeIRStmt.LoadG: dst/alt type mismatchIRStmt.LoadG: dst/loaded type mismatchIRStmt.LLSC.addr: not :: guest word typeIst.LLSC.end: bogus endiannessIst.LLSC(SC).result: not :: Ity_I1Ist.LLSC(SC).result :: storedata bogusIRStmt.Dirty.guard not :: Ity_I1IRStmt.Dirty.args: > 1 GSPTR argIRStmt.Dirty.args: VECRET present, but fn does not return V128 or V256IRStmt.Dirty.args: VECRET not present, but fn returns V128 or V256IRStmt.Dirty.args: > 1 VECRET presentIRStmt.Dirty.args: GSPTR requested, but no fxState declaredIRStmt.Exit.guard: not :: Ity_I1IRStmt.Exit.dst: not :: guest word type$Ë$Ë$Ë4$Ë<$Ë,$ GNUzR| HEr FA B G FA B G FA B G FA B G FA B G FA B G FA B G FA B G FA B G FA B G FA B G FA B G FA B G FA B G FA B G FA A G AL4 PH GuCu|Luxy AAC D TDqEA RGHA EGFA PAFA A AK AGFA `EA RBGK kF GF A AD GF JF JF JF JF JF JF RF RF RF RF RF RF RF RF LAL0@ ?EU GF AA G G FA4t`>E[ ALHA A   E G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G 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FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G FA A G 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" # $ % & ' ($ )( *, +0 ,4 -8 .< /@ 0D 1H 2L 3P 4T 5X 6\ 7` 8d 9h :l ;p <t =x >| ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h$ i( j, k0 l4 m8 n< o@ pD qH rL sP tT uX v\ w` xd yh zl {p |t }x ~|                                            $ ( , 0 4 8 < @ D H L P T X \ ` d h l p t x |                                            $ ( , 0 4 8 < @ D H L P T X \ ` d h l p t x |                                                             !  "  #  $  %  &  '  ( $ ) ( * , + 0 , 4 8 < @ D - H . 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uv蛆VXD$ ~VXuP@T$D$4$L$ T$YHFqǃ@VD$XP@T$$D$ PhPPPhPPT$ L$$PT$HL$D$QAuPh@뛍Ph>PPPh=PPPh:kPh7PPPh4PP<$VL$QVPPhTPPpriv/ir_opt.ch->used < h->size addUses_ExpraoccCount_ExprdeltaIRExprisIRAtom(ex->Iex.GetI.ix)isIRAtom(qop->arg1)isIRAtom(qop->arg2)isIRAtom(qop->arg3)isIRAtom(qop->arg4)isIRAtom(triop->arg1)isIRAtom(triop->arg2)isIRAtom(triop->arg3)isIRAtom(ex->Iex.Binop.arg1)isIRAtom(ex->Iex.Binop.arg2)isIRAtom(ex->Iex.Unop.arg)isIRAtom(ex->Iex.Load.addr)isIRAtom(args2[i])isIRAtom(ex->Iex.ITE.cond)isIRAtom(ex->Iex.ITE.iftrue)isIRAtom(ex->Iex.ITE.iffalse) subst_ExpratbSubst_Exprflatten_Exprd2->mAddr == NULLflatten_Stmtk_lo <= k_hie_lo <= e_hicollapseChainlow <= highsetHints_Expr(*minoff & ~0xFFFF) == 0(*maxoff & ~0xFFFF) == 0*minoff <= *maxoffisIRAtom(ix1)isIRAtom(ix2)descr1->base == descr2->basegetAliasingRelation: itersc1->tag == c2->tag(minoff & ~0xFFFF) == 0(maxoff & ~0xFFFF) == 0isIRAtom(st->Ist.Put.data)isIRAtom(st->Ist.AbiHint.nia)isIRAtom(st->Ist.Store.addr)isIRAtom(st->Ist.Store.data)isIRAtom(sg->addr)isIRAtom(sg->data)isIRAtom(sg->guard)isIRAtom(lg->addr)isIRAtom(lg->alt)isIRAtom(lg->guard)isIRAtom(st->Ist.Exit.guard)handle_gets_Stmt0do_cse_BB(1)do_cse_BB(2)irExpr_to_TmpOrConstsubst_AvailExpreqTmpOrConsteq_AvailExprn >= 0tmpOrConst_to_IRExpravailExpr_to_IRExprnotBoolisOnesUisZeroUisIRAtom(puti->ix)isIRAtom(puti->data)isIRAtom(cas->addr)isIRAtom(cas->expdLo)isIRAtom(cas->dataLo)isIRAtom(st->Ist.LLSC.addr)isIRAtom(d2->mAddr)isIRAtom(d2->guard)isIRAtom(arg)subst_and_fold_Stmtnop->tag == Ist_NoOplgu->tag == Ist_LoadGcprop_BB: unhandled ILGOpaddUses_Stmtrelation != ExactAliasrelation == ExactAliaspi->tag == Ist_PutIisIRAtom(s2->Ist.Put.data)isIRAtom(p2->ix)isIRAtom(p2->data)isIRAtom(s2->Ist.Store.addr)isIRAtom(s2->Ist.Store.data)aoccCount_Stmtj <= ienv[A_NENV-1].bindee == NULLatbSubst_Stmtj <= i+1isIRAtom(d->guard)isIRAtom(d->mAddr)considerExpensivesst->tag == Ist_Exitudst->tag == Iex_ConstdeltaIRStmti >= 0mkZeroOfPrimopResultType: bad primopmkOnesOfPrimopResultType: bad primopvex iropt: 8 x unrolling (%d sts -> %d sts) vex iropt: 4 x unrolling (%d sts -> %d sts) vex iropt: 2 x unrolling (%d sts -> %d sts) vex iropt: not unrolling (%d sts) descr1->nElems == descr2->nElemsdescr1->elemTy == descr2->elemTybias1 >= 0 && bias1 < descr1->nElemsbias2 >= 0 && bias2 < descr1->nElemspxControl < VexRegUpdAllregsAtEachInsnisIRAtom(st->Ist.PutI.details->ix)isIRAtom(st->Ist.PutI.details->data)isIRAtom(st->Ist.AbiHint.base)cee1->regparms == cee2->regparmscee1->mcx_mask == cee2->mcx_maska1->u.CCall.retty == a2->u.CCall.rettye->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U8e->Iex.ITE.cond->Iex.Const.con->tag == Ico_U1vex iropt: fold_Expr: no ident rule for: vex iropt: fold_Expr: no const rule for: fguard->Iex.Const.con->tag == Ico_U1fguard->Iex.Const.con->Ico.U1 == Truecas->expdHi == NULL || isIRAtom(cas->expdHi)cas->dataHi == NULL || isIRAtom(cas->dataHi)isIRAtom(st->Ist.LLSC.storedata)fcond->Iex.Const.con->tag == Ico_U1fcond->Iex.Const.con->Ico.U1 == Truevex iropt: IRStmt_Exit became unconditional env[(Int)(st2->Ist.WrTmp.tmp)] == NULLguard->Iex.Const.con->tag == Ico_U1guard->Iex.Const.con->Ico.U1 == Truen_fixups >= 0 && n_fixups <= N_FIXUPSix >= 0 && ix+1 < out->stmts_usedi_unconditional_exit >= 0 && i_unconditional_exit < bb->stmts_usedguestAccessWhichMightOverlapPutIcon->tag == Ico_U32 || con->tag == Ico_U64con->tag == udst->Iex.Const.con->tagudst->Iex.Const.con->tag == Ico_U32 || udst->Iex.Const.con->tag == Ico_U64unroll_factor == 2 || unroll_factor == 4 || unroll_factor == 8yw}availExpr_to_IRExpreqIRCalleeeq_AvailExprredundant_get_removal_BBguestAccessWhichMightOverlapPutIidenticalPutIsgetAliasingRelation_IIfindPutImaybe_loop_unroll_BBconsiderExpensivesinvalidateOverlapshandle_gets_StmtaddToHHWgetArrayBoundsmk_key_GetPutredundant_put_removal_BBflatten_Stmtupdate_intervaladdToEnvFrontado_treebuild_BBdo_deadcode_BBsubst_ExprsameIRExprs_aux2fold_Clz64fold_Clz32fold_Exprsubst_and_fold_Stmtcprop_BB1&$Ë<$Ë,$ GNUzR| dAA LAE0n AA AAJ  AA AAA K 4K8A  W  b  {    F   !  z(X A Z s  +CzpH xR &"+A0&,%3+31C7rK>QEpcLNSZqa$hÈov7}@P  "/>( gxJz0K d$*06 <%BH NP T Z `2f@lLrZxs~t  ( L   6J 9Qo  &,28{>fDJPLVY\bx hT n0 t, z   x  U)  D    ? q ", )X /P 6 <CJh QX _ fm$t;{Oj{ %8  $ _Kv p  \ H m ~ 7 % * 8/ 4 9 > pC H M R W `\ Pa (f 0k p Pu @{  x b l X       H (   h  0       @     X ! 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НaddToHHW__PRETTY_FUNCTION__.3219mkZeroOfPrimopResultTypeaddUses_ExpraoccCount_ExprdeltaIRExprmkOnesOfPrimopResultTypesubst_Expr__PRETTY_FUNCTION__.3819atbSubst_Exprflatten_Exprflatten_Stmt__PRETTY_FUNCTION__.3276invalidateOverlaps__PRETTY_FUNCTION__.3322calc_unroll_factor.isra.0collapseChain.isra.0setHints_Expr__PRETTY_FUNCTION__.4536getAliasingRelation_IC.isra.0__PRETTY_FUNCTION__.3300mk_key_GetIPutIgetAliasingRelation_II__PRETTY_FUNCTION__.4043spec_helpers_BBsameIRExprs_aux2num_nodes_visited__PRETTY_FUNCTION__.3464sameIRExprs_aux2.coldredundant_put_removal_BB__PRETTY_FUNCTION__.3378__PRETTY_FUNCTION__.3426__PRETTY_FUNCTION__.3307do_cse_BB.constprop.0__PRETTY_FUNCTION__.4219__PRETTY_FUNCTION__.4196__PRETTY_FUNCTION__.4069fold_Expr__PRETTY_FUNCTION__.3720__PRETTY_FUNCTION__.3568__PRETTY_FUNCTION__.3560CSWTCH.417__PRETTY_FUNCTION__.3840__PRETTY_FUNCTION__.3892__PRETTY_FUNCTION__.3995expensive_transformations__PRETTY_FUNCTION__.4365__PRETTY_FUNCTION__.4385__PRETTY_FUNCTION__.4374cheap_transformations__PRETTY_FUNCTION__.3342__PRETTY_FUNCTION__.4817__PRETTY_FUNCTION__.4583n_total.5029n_expensive.5030__PRETTY_FUNCTION__.4971__PRETTY_FUNCTION__.4509.L27.L47.L69.L90.L115.L118.L161.L204.L271.L286.L315.L412.L435.L526.L602.L603.L606.L686.L700.L715.L1394.L1171.L1191.L1014.L1758.L1766.L1932.L1870.L1939.L2014.L2043.L2215.L2279.LC0.LC1.LC2.LC3.LC4.LC5.LC6.LC7.LC20.LC10.LC14.LC17.LC22.LC11.LC23.LC15.LC12.LC8.LC21.LC18.LC19.LC16.LC13.LC9.LC24.LC25.LC26.LC27.LC28.LC29.LC31.LC30.LC35.LC32.LC34.LC33.LC36.LC37.LC38.LC39.LC40.LC41.LC47.LC49.LC42.LC43.LC44.LC45.LC46.LC48.LC50.LC68.LC64.LC67.LC56.LC57.LC55.LC53.LC70.LC54.LC52.LC69.LC59.LC65.LC60.LC58.LC62.LC66.LC63.LC61.LC82.LC80.LC74.LC73.LC79.LC81.LC71.LC72.LC77.LC78.LC76.LC75.LC89.LC88.LC86.LC87.LC84.LC85.LC83.LC106.LC103.LC108.LC102.LC94.LC90.LC99.LC96.LC91.LC97.LC111.LC112.LC109.LC95.LC110.LC98.LC113.LC101.LC100.LC114.LC104.LC92.LC105.LC93.LC107.LC115.LC117.LC116.LC118.LC126.LC125.LC119.LC120.LC121.LC124.LC122.LC123.LC131.LC128.LC130.LC129.LC127.LC133.LC134.LC132.LC136.LC135.LC139.LC138.LC137.LC142.LC141.LC140.L31.L30.L33.L32.L28.L55.L59.L58.L57.L56.L68.L52.L50.L82.L81.L80.L79.L78.L76.L74.L72.L98.L102.L101.L100.L112.L111.L95.L93.L121.L120.L119.L116.L140.L139.L138.L137.L136.L135.L134.L132.L130.L191.L190.L189.L188.L187.L186.L185.L183.L181.L217.L216.L215.L214.L213.L212.L211.L210.L209.L208.L207.L205.L299.L298.L296.L295.L294.L293.L292.L291.L290.L288.L325.L324.L323.L322.L321.L320.L319.L318.L317.L316.L313.L425.L424.L423.L422.L421.L419.L417.L415.L533.L532.L531.L530.L529.L527.L548.L547.L546.L545.L543.L611.L610.L609.L608.L607.L604.L871.L688.L707.L706.L705.L704.L703.L701.L733.L738.L746.L751.L867.L756.L775.L767.L783.L788.L793.L801.L822.L817.L815.L819.L818.L816.L814.L813.L891.L810.L737.L745.L750.L755.L766.L782.L774.L787.L792.L831.L803.L1178.L1177.L1176.L1168.L1175.L1174.L1172.L1173.L1170.L1335.L1334.L1330.L1332.L1064.L1063.L1062.L1061.L1060.L1059.L1058.L1057.L1056.L1055.L1054.L1053.L1052.L1051.L1050.L1049.L1048.L1047.L1046.L1045.L1044.L1043.L1042.L1041.L1040.L1039.L1038.L1037.L1036.L1035.L1034.L1033.L1032.L1031.L1030.L1029.L1028.L1027.L1026.L1025.L1024.L1022.L1144.L1143.L1142.L1141.L1140.L1139.L1138.L1137.L1136.L1135.L1134.L1133.L1132.L1131.L1130.L1129.L1128.L1127.L1126.L1125.L1124.L1123.L1122.L1121.L1120.L1119.L1118.L1117.L1116.L1115.L1114.L1113.L1112.L1111.L1110.L1109.L1108.L1107.L1106.L1105.L1104.L1103.L1102.L1391.L1021.L1020.L1019.L1018.L1017.L1015.L1277.L1276.L1272.L1274.L1223.L1222.L1218.L1220.L1257.L1256.L1252.L1254.L1214.L1213.L1209.L1211.L1197.L1196.L1192.L1194.L1266.L1265.L1261.L1263.L1233.L1232.L1231.L1230.L1229.L1227.L1302.L1301.L1297.L1299.L1311.L1310.L1306.L1308.L1344.L1343.L1339.L1341.L1593.L1592.L1591.L1590.L1589.L1588.L1587.L1586.L1585.L1584.L1583.L1582.L1580.L1776.L1775.L1774.L1817.L1772.L1771.L1770.L1769.L1767.L1877.L1876.L1875.L1874.L1873.L2028.L2027.L2026.L2183.L2023.L2022.L2021.L2020.L2019.L2017.L2057.L2056.L2055.L2054.L2053.L2052.L2051.L2050.L2049.L2048.L2047.L2046.L2044.L2225.L2224.L2223.L2222.L2221.L2220.L2219.L2218.L2217.L2216.L2213.L2289.L2288.L2287.L2286.L2388.L2284.L2283.L2282.L2281.L2280.L2277__x86.get_pc_thunk.di_GLOBAL_OFFSET_TABLE_private_LibVEX_alloc_currprivate_LibVEX_alloc_lastvex_assert_failprivate_LibVEX_alloc_OOM__x86.get_pc_thunk.bxIRConst_V256IRExpr_ConstvpanicIRConst_U1IRConst_U64IRConst_U32IRConst_U8IRConst_U16IRConst_V128vex_printfppIRExprppIROpshallowCopyIRExprVecIRExpr_GetIIRExpr_LoadIRExpr_UnopIRExpr_BinopIRExpr_ITEIRExpr_TriopIRExpr_QopIRExpr_CCalltypeOfIRExprnewIRTempIRStmt_WrTmpaddStmtToIRSBIRExpr_RdTmpIRStmt_AbiHintIRStmt_PutmkIRPutIIRStmt_PutIIRStmt_StoreIRStmt_LoadGIRStmt_StoreGmkIRCASIRStmt_CASIRStmt_LLSCemptyIRDirtyIRStmt_DirtyIRStmt_ExitppIRStmtvex_controlsizeofIRTypeeqIRRegArrayeqIRAtom__x86.get_pc_thunk.bpemptyIRSBdeepCopyIRTypeEnvIRStmt_NoOpeqIRConstIRConst_F64icprop_BBIRStmt_MBEtypeOfIRLoadGOpIRStmt_IMarkdo_deadcode_BBado_treebuild_BBdo_iropt_BBtypeOfIRTempdeepCopyIRSBdeepCopyIRExprj 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" # $ % Y & ' ( ' ) * + , - Z Y . ] ] [ / 0 1 2 \ \$ [( \, 30 [4 48 5< 6@ 5D 7H 8L 9P :T ;X <\ ^` =d >h ?l @p At Bx _| C D E F G H I J ` ` K L M N O P Q R S T ` U a a V W X Y Z [ \ ] ^ _ a ` (pD`0   0  $    p  $T@< H!$>$?0$@.symtab.strtab.shstrtab.group.rel.text.data.bss.rodata.str1.1.rodata.str1.4.rel.rodata.rel.text.unlikely.text.__x86.get_pc_thunk.bx.text.__x86.get_pc_thunk.di.text.__x86.get_pc_thunk.bp.note.GNU-stack.note.gnu.property.rel.eh_frame4p<jD&Pˬ" @0,,2 72F2Y`) U @d] ea @|y t<$ @y*j z/221 0 0 0 644 16568 ` ELF=4( 1Í&fUWVS$v{T$11&iq1Q113A1؃wыt$V$t4 119u[^_]Ð11Ս&1ÐSXЍ 1[11ÍvWVSxpȍ911ȍ311[^_1ÍvWVSËxs[ : 111[^_1Í&t&UWVS@iy q11 3111[^_]1ÐUWVShxX 4*1$ʉ1p3$\$ 3ʋX3t$1փ1[1^_]1Ít&UWVShxX *ʋp1<$x3$\$3T$1L$3t$\$ ;1t$ X11[1^_]11Í&UWVS hxX 4*ʋH1|$x3T$\$4$p3T$Xʍ>34$1$ 111[^_]1ÐUWVShxp *1|$xˋHt$ 3T$p $H3T$ \$L$ʍ >3t$1 $L$ًX 13$13T$[^1_]1Ít&UWVShxp *t$ 1ˉ|$Hpx3T$\$4$p3T$ L$t$ʍ43|$4$1t$3T$X$ʋp 3$3T$L$3t$1֍1[1^_]1Í&t&UWVS$hXp *1\$Xωt$H3T$p\$3T$<$L$ x34$1|$x  $3T$ 3T$L$3T$|$\$ x$ʋX(t$3t$1t$ 1111у$[^1_]fUWVS$hpX *T$Pt$pϋH\$ ߋXT$L$ى|$3t$щ\$X$x P( $H,T$ ЋT$$13T$3T$ 13T$3T$4$3T$1113\$ ˃$1[^_]1ÐUWVSp$D$h$d$@9$-$D$$D$$v $ $1fP$fH $1҉D$$$RPD$<^_l$NjD$H ʼnL$8t&WUXZu$l$tt$$$ZYD$t$D$D$%D$ D$DD$,D$l$<D$0$L$9HZD$,D$CD$(b F |$$$D$jjP$$ $1fP$fH $D$$$D$8^{t&jjWPVD$(~ |$0F T$D$\R1҅$$$$Wt$$t$$$$Rt$TVP$$$D$TB4 |$  D$lJL$HD$Lt uOD$d >D$9F  FL$ 8 H L$hL$PL$ HD$$F ~ N F ;D$ ~D 8 $9x $$@P$D$D$1T$|$,t$ ֋T$>119ut$|$,T$먋 $11L8' pp$D$鍳D$1 v4PhPP4PhPPf4Ph&PP4PhPP4Ph<PP4PhPPT$X|$l$TUF4t$$ 9~ ۋl$TT$X4PhlPP4Ph{PP4PhPP4PhPP4PhPP4PhPP4PhPP4Ph"4PhPP4PhPP4PhPP4PhPP4PhPP4PhPP|$= 1vex_control.guest_max_insns <= 100vex_control.guest_chase_thresh >= 0vex_control.guest_chase_thresh < vex_control.guest_max_insnsguest_word_type == Ity_I32 || guest_word_type == Ity_I64n_instrs < guest_max_insns_reallyn_cond_resteers_allowed >= 0 && n_cond_resteers_allowed <= 2dres.whatNext == Dis_StopHere || dres.whatNext == Dis_Continue || dres.whatNext == Dis_ResteerU || dres.whatNext == Dis_ResteerCdres.len >= 0 && dres.len <= 24first_stmt_idx >= 0 && first_stmt_idx < irsb->stmts_usedfirst_stmt_idx < irsb->stmts_usedst->Ist.Put.offset == offB_GUEST_IPvge->len[vge->n_used-1] < 5000dres.jk_StopHere == Ijk_INVALIDdres.jk_StopHere != Ijk_INVALIDresteerOKfn(callback_opaque,dres.continueAt)vge->n_used >= 1 && vge->n_used <= 3(extents_needing_check >> vge->n_used) == 0len2check >= 0 && len2check < 2000hWs_to_check > 0 && hWs_to_check < 2004 / host_word_szBexpectedhW == fn_spec( first_hW )priv/guest_generic_bb_to_IR.cszB_GUEST_IP == 4(offB_GUEST_IP % 4) == 0szB_GUEST_IP == 8(offB_GUEST_IP % 8) == 0 irsb->next == NULLdres.continueAt == 0dres.whatNext != Dis_ResteerCdres.hint == Dis_HintVerboseimarkimark->tag == Ist_IMarkimark->Ist.IMark.len == 0 irsb->jumpkind == Ijk_Boringirsb->offsIP == 0stst->tag == Ist_PutresteerOKvge->n_used <= 3first_hW <= last_hWnm_spec!nm_specirsb->next != NULLPUT(%d) = ; exit-genericg_compute_checksum_4albb_to_IR$ GNUzR| <0EA ACC{ CA AAB pEO(-EA A] AC(4EA Ad AC4P?EC AAkA CA80[EA AAC|HC AC8lsEA AAC$NJC AC8poEA AAC OKA CA8EA AAC(qCA CA8 pEA AAC0HE AC8\ EA AAC8CA CA8EA AAC8CA CAxbEA AANAJAbAFAXGHA EAK eJKBAFALdNGGGADDGGADAAGXWJIAFFPFLXAPAHJUDPYDOYGLFYGLfFFAABEHFFFAEWDEEHP AA AAB G KAGF G KAGF G KAGE G KAGE G KAGE G KAGE h KAGE BEGGEYG`AGGGU KAGE G KAGG G KAGE G KAGE G KAGE G KAGE UKLHYEGGEG KAGE G KAGE G KAGE G KAGE G KAGE G KAGE G EE G KAGE G KAGE G KAGE G KAGE G KAGE G KAGE MIHAFADBEHN KAGE DMHAW KAGE G KAGE G KAGE G KAGE G KAGE G KAGE G KAGE G KAGE N KAGE G KAGE G KAGE G EE G KAGE G KAGE KGWApRAHLHLFHL KAGE P +Kk-4P?[s po+Kpl 4  t,8 |$)L/l5 : ?DDhINSX]ceitoIu{[v\0 =ORo`@  @#)/5;)AG9MS(Y _ekqw}   b '1>KXcrconst_Falsegenericg_compute_checksum_4algenericg_compute_checksum_4al_1genericg_compute_checksum_4al_2genericg_compute_checksum_4al_3genericg_compute_checksum_4al_4genericg_compute_checksum_4al_5genericg_compute_checksum_4al_6genericg_compute_checksum_4al_7genericg_compute_checksum_4al_8genericg_compute_checksum_4al_9genericg_compute_checksum_4al_10genericg_compute_checksum_4al_11genericg_compute_checksum_4al_12n_resteers.3313__PRETTY_FUNCTION__.3323.L104.LC24.LC9.LC12.LC13.LC14.LC15.LC16.LC17.LC31.LC18.LC28.LC59.LC7.LC10.LC11.LC8.LC1.LC2.LC3.LC4.LC5.LC6.LC0.LC29.LC45.LC22.LC20.LC23.LC21.LC35.LC25.LC26.LC27.LC19.LC32.LC33.LC34.LC36.LC37.LC38.LC39.LC40.LC41.LC42.LC55.LC52.LC50.LC30.LC47.LC46.LC48.LC44.LC51.LC49.LC43.LC54.LC53.LC57.LC58.LC56.L117.L116.L142.L114.L143.L112.L111.L110.L109.L108.L107.L105bb_to_IR__x86.get_pc_thunk.bx_GLOBAL_OFFSET_TABLE_vex_controlvex_traceflagsemptyIRSBIRConst_U64IRStmt_NoOpaddStmtToIRSBIRConst_U32IRStmt_IMarkvex_printfnewIRTempIRExpr_ConstIRStmt_WrTmpIRExpr_RdTmpIRStmt_PutmkIRExpr_HWordmkIRExprVec_1mkIRExprCCallIRExpr_BinopIRStmt_Exitvex_assert_failIRExpr_GetppIRStmtmkIRExprVec_2ppIRExprppIRJumpKindf g+h +itjklm) 3 jn.o5mt  p   q q k k r s) rF sU tu u t u  v w x n r y3 z    {    {    {    {  # ){/ 6 B H{o v  {   {|u ! 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*"&(jmp_litdisAModedis_MMX_shiftE_immdis_MMX_shiftG_byEdis_SHLRD_Gv_EvgetIRegmkU8integerGuestRegOffsetputIRegnewTempdis_push_segregdis_pop_segregpositiveIse_X86Condcodejcc_01dis_bt_G_Emath_BSWAPdis_bs_E_Gdis_Grp8_Immdis_Grp5setFlags_DEP1_DEP2_shiftdis_Grp2dis_Grp1codegen_xchg_eAX_RegcasLEdis_retdis_REP_opset_EFLAGS_from_valuedis_op2_G_Edis_op2_E_Ghelper_SBBhelper_ADCdis_op_imm_Adis_mov_Sw_Ewdis_imul_I_E_GmkAnd1mkSizedOpput_ST_TAGput_ST_UNCHECKEDdis_FPUjmp_tregputSRegmkU16putXMMRegLane32FputXMMRegLane64FputXMMRegputMMXRegput_ftopdis_PABS_helperdis_PSIGN_helperbreakup128to32sdis_MMXop_regmem_to_regdis_SSE_shiftG_byEdis_SSE_shiftE_immbreakup64to16sputXMMRegLane64xmmGuestRegLane64offsetxmmGuestRegLane16offsetputXMMRegLane16xmmGuestRegLane32offsetputXMMRegLane32dis_SSEcmp_E_to_Gput_emwarnput_sse_roundingmodedisInstr_X86_WRKdisInstr_X86priv/guest_x86_toIR.cfindSSECmpOp(x86,guest)%es:%ss:%ds%fs:%gs:sorbTxt(x86,guest)nameIReg(X86)ALWAYSobnbznzbenbesnspnplnllenlenoname_X86Condcodex86g_calculate_eflags_allx86g_calculate_conditiondres->len == 0dres->continueAt == 0ty == Ity_I8ty == Ity_I16ty == Ity_I32putIReg(x86)archreg < 8host_endness == VexEndnessLEisPlausibleIRType(ty) src, dst tys are: , narrowTo(x86)widenUto32i < 256sz == 1 || sz == 2 || sz == 4szToITy(x86)fucomi%s %%st(0),%%st(%u) f%s%c %s getUDisp(x86)nameISize(x86)%s%c %gs%es%ss%fs%cssz == 2 || sz == 4push%c %s pop%c %s tyE == tyN0handleSegOverride(x86,guest)x86g_use_seg_selectorx86g_calculate_eflags_csetFlags_DEP1_DEP2(x86)setFlags_DEP1(x86)i < 65536codegen_div(x86)guardsetFlags_DEP1_DEP2_shift(x86)t0 && *t0 == IRTemp_INVALIDt1 && *t1 == IRTemp_INVALIDt2 && *t2 == IRTemp_INVALIDt3 && *t3 == IRTemp_INVALIDrestart_point == 0%ax%eax%al!carryingdis_op_imm_A(x86,guest)%s%c $0x%x, %s epartIsReg(rm)%s $%d,%s imulmul%s%c %s %s(%s)%s%d(%s)%s0x%x(%s)disAMode(x86): not an addr!%s(0x%x)%s(%s,%s,%d)%s0x%x(,%s,%d)%s(%s,,)%s0x%x(,,)%s%d(%s,,)%s%d(%s,%s,%d)%s %s,%s sz == 4 || sz == 8%s $%d,%s,%s qdwx86g_calculate_mmx_pmaddwdx86g_calculate_mmx_psadbw 0x%x dis_MMXop_regmem_to_reghName == NULLhAddr == NULLhName != NULLhAddr != NULL%s%s %s, %s getSDisp(x86)imul %d, %s, %s mov%c %s,%s mkWidenOp(x86,guest)mov%c%c%c %s,%s sz == 4 || sz == 2bs%c%c %s, %s sh%cd%c %s, %s, %s xadd%c %s, %s keep%s%c %s,%s am_sz == 1x86g_calculate_RCRx86g_calculate_RCLwidenSto32%s%c %s, %s rcbt%s%c %s, %s cmpxchg%c %s,%s test%c $0x%x, %s not%c %s neg%c %s div%c %s idiv%c %s movd %s, %s movq %s, %s mov(nt)q %s, %s paddpaddspadduspsubpsubspsubuspmulhwpmullwpmaddwdpcmpeqpcmpgtpackssdwpacksswbpackuswbpunpckhpunpcklpandpandnporpxorpsllwpslldpsllqpsrlwpsrldpsrlqpsrawpsradmaskmovq %s,%s tt0t1ntat2hmapdupddqaaddsubsubdsubwaddswadddsubswaddwaam aad cdqq cwdq fsinfcosneex86g_dirtyhelper_CPUID_sse3x86g_dirtyhelper_CPUID_sse2x86g_dirtyhelper_CPUID_sse1x86g_dirtyhelper_CPUID_mmxextx86g_dirtyhelper_CPUID_sse0(assumed not taken)(assumed taken) 0x%x: dres.whatNext == Dis_StopHere%%eax = guest_NRADDR call-noredir *%%eax IR injection %%es:%%cs:%%fs:%%gs:nop nopw %%cs:0x0(%%eax,%%eax,1) nop%c nop%c %s lock !epartIsReg(modrm)fxsave %s x86g_dirtyhelper_FXSAVEfxrstor %s x86g_dirtyhelper_FXRSTORaddpssz == 4addssandnpsandpscmppscmpss[u]comiss %s,%s cvtpi2ps %s,%s cvtsi2ss %s,%s cvt%sps2pi %s,%s cvt%sss2si %s,%s divpsdivssldmxcsr %s x86g_check_ldmxcsrmovntq %s,%s pavgbpavgwpextrw $%d,%s,%s pinsrw $%d,%s,%s pmaxswpmaxubpminswpminubpmovmskb %s,%s pmuluhprefetch%s %s psadbwpshufw $%d,%s,%s sfence maxpsmaxssminpsminssmov[ua]ps %s,%s movhps %s,%s movhlps %s, %s movlps %s, %s movmskps %s,%s movntp%s %s,%s movss %s,%s mulpsmulssorpsrcppsrcpssrsqrtpsrsqrtssshufps $%d,%s,%s sqrtpssqrtssstmxcsr %s x86g_create_mxcsrsubpssubssunpck%sps %s,%s xorpsaddpdaddsdandnpdandpdcmppdcmpsd[u]comisd %s,%s cvtdq2pd %s,%s cvtdq2ps %s,%s cvtpd2dq %s,%s cvt%spd2pi %s,%s cvt%spf2pi %s,%s cvtpd2ps %s,%s cvtpi2pd %s,%s cvtps2dq %s,%s cvtps2pd %s,%s cvt%ssd2si %s,%s cvtsd2ss %s,%s cvtsi2sd %s,%s cvtss2sd %s,%s cvttpd2dq %s,%s cvttps2dq %s,%s divpddivsd%sfence maxpdmaxsdminpdminsdmov%s %s,%s movdqa %s, %s movdqu %s,%s movdqu %s, %s movdq2q %s,%s movhpd %s,%s movlpd %s, %s movmskpd %s,%s maskmovdqu %s,%s movntdq %s,%s movnti %s,%s movq %s,%s movq2dq %s,%s movsd %s,%s mulpdmulsdorpdshufpd $%d,%s,%s sqrtpdsqrtsdsubpdsubsdxorpdpaddbpadddpaddqpaddwpaddsbpaddswpaddusbpadduswpcmpeqbpcmpeqdpcmpeqwpcmpgtbpcmpgtdpcmpgtwpmaddwd %s,%s pmulhuwpmuludq %s,%s psadbw %s,%s pshufd $%d,%s,%s pshufhw $%d,%s,%s pshuflw $%d,%s,%s pslldq $%d,%s psrldq $%d,%s psubbpsubdpsubqpsubwpsubsbpsubswpsubusbpsubuswpunpckhbwpunpckhdqpunpckhqdqpunpckhwdpunpcklbwpunpckldqpunpcklqdqpunpcklwdclflush %s movs%cdup %s,%s movddup %s,%s addsubps %s,%s addsubpd %s,%s h%sps %s,%s h%spd %s,%s lddqu %s,%s pmaddubsw %s,%s ph%s %s,%s pmulhrsw %s,%s psign%s %s,%s pabs%s %s,%s palignr $%u,%s,%s palignr $%u%s,%s pshufb %s,%s movbe %s,%s rounds%c $%d,%s,%s roundsd $%d,%s,%s lzcnt%c %s, %s jcxz 0x%x ret %u ret iret (very kludgey) call 0x%x ; popl %s call 0x%x leave daa das aaa aas x86g_calculate_aad_aamcwde sz == 2cbw sahf lahf fwait fcoms %s fcomps %s subrdivdivrf%s%s st(%u), st(%u) fcom %%st(0),%%st(%u) fcomp %%st(0),%%st(%u) flds %s fsts %s fstps %s x86g_dirtyhelper_FLDENVfldenv %s fldcw %s x86g_check_fldcwx86g_dirtyhelper_FSTENVfnstenv %s fnstcw %s x86g_create_fpucwunhandled opc_aux = 0x%2x first_opcode == 0xD9 fld %%st(%u) fxch %%st(%u) fchs fabs ftst x86g_calculate_FXAMfxam fld1 fldl2t fldl2e fldpi fldlg2 fldln2 fldz f2xm1 fyl2x fptan fpatan fxtract x86amd64g_calculate_FXTRACTfprem1 fprem fyl2xp1 fsqrt fsincos frndint fscale %s fiaddl %s fimull %s ficoml %s ficompl %s fisubl %s fisubrl %s fidivl %s fidivrl %s fcmovb %%st(%u), %%st(0) fcmovz %%st(%u), %%st(0) fcmovbe %%st(%u), %%st(0) fcmovu %%st(%u), %%st(0) fucompp %%st(0),%%st(1) fildl %s fisttpl %s fistl %s fistpl %s x86g_dirtyhelper_loadF80lefldt %s x86g_dirtyhelper_storeF80lefstpt %sfirst_opcode == 0xDB fcmovnb %%st(%u), %%st(0) fcmovnz %%st(%u), %%st(0) fcmovnbe %%st(%u), %%st(0) fcmovnu %%st(%u), %%st(0) fnclex x86g_dirtyhelper_FINITfninit fcoml %s fcompl %s fldl %s fistppll %s fstl %s fstpl %s x86g_dirtyhelper_FRSTORfrstor %s x86g_dirtyhelper_FSAVEfnsave %s fnstsw %s first_opcode == 0xDD ffree %%st(%u) fst %%st(0),%%st(%u) fstp %%st(0),%%st(%u) fucom %%st(0),%%st(%u) fucomp %%st(0),%%st(%u) fiaddw %s fimulw %s ficomw %s ficompw %s fisubw %s fisubrw %s fidivrw %s fuompp %%st(0),%%st(1) fildw %s fisttps %s fistp %s fistps %s fildll %s fistpll %s first_opcode == 0xDF ffreep %%st(%d) fnstsw %%ax inc%c %s dec%c %s int $0x3 int $0x%x jmp-8 0x%x jmp 0x%x j%s-8 0x%x %s jecxz 0x%x loop%s 0x%x lea%c %s, %s segmentGuestRegOffset(x86)nameSReg(x86)mov %s,%s movw %s,%s mov%c %s0x%x, %s mov%c %s, %s0x%x movb $0x%x,%s mov%c $0x%x,%s mov%c $0x%x, %s oradcsbbandxorcmptestpopf%c popa%c push%c $0x%x pushf%c pusha%c movscmpsstoslodsscascld std clc stc cmc disInstr(x86)(clc/stc/cmc)salc repne movsrepne cmpsrepne stosrepne scasrep movsrepe cmpsrep stosrep lodsrepe scasrep nop (P4 pause) rep ret xchg%c %s, %s nop xlat%c [ebx] in%c $%d,%s %dxin%c %s,%s x86g_dirtyhelper_INout%c %s,$%d out%c %s,%s x86g_dirtyhelper_OUT%clnameGrp4(x86)%sb %s nameGrp5(x86)nameGrp8(x86)bswapl %s cmov%c%s %s,%s cmpxchg8b %s disInstr(x86)(cpuid)cpuid imul%c %s, %s j%s-32 0x%x %s x86g_dirtyhelper_RDTSCrdtsc set%s %s $%dsysenter{f}emms sgdt %s sidt %s x86g_dirtyhelper_SxDTsyscall ud2 guest_arch == VexArchX86x2 >= x1 %dl%bl%ah{sp}%ch{bp}%dh{si}%bh{di}%cx%bx%sp%bp%si%di%ecx%edx%ebx%esp%ebp%esi%edi???btbtsbtrbtcincdeccall*jmp*pushrolrorrclrcrshlshrsar%xmm0%xmm1%xmm2%xmm3%xmm4%xmm5%xmm6%xmm7%mm0%mm1%mm2%mm3%mm4%mm5%mm6%mm7ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32op8 == Iop_Add8 || op8 == Iop_Sub8 || op8 == Iop_Mul8 || op8 == Iop_Or8 || op8 == Iop_And8 || op8 == Iop_Xor8 || op8 == Iop_Shl8 || op8 == Iop_Shr8 || op8 == Iop_Sar8 || op8 == Iop_CmpEQ8 || op8 == Iop_CmpNE8 || op8 == Iop_CasCmpNE8 || op8 == Iop_ExpCmpNE8 || op8 == Iop_Not8typeOfIRExpr(irsb->tyenv,x) == Ity_I1typeOfIRExpr(irsb->tyenv,y) == Ity_I1dres->whatNext == Dis_Continuedres->jk_StopHere == Ijk_INVALIDcond >= X86CondO && cond <= X86CondNLEarchreg >= 4 && archreg < 8 && sz == 1typeOfIRExpr(irsb->tyenv,e) == Ity_I64typeOfIRExpr(irsb->tyenv,e) == Ity_V128typeOfIRExpr(irsb->tyenv, value) == Ity_I8typeOfIRExpr(irsb->tyenv, e) == Ity_I32typeOfIRExpr(irsb->tyenv, value) == Ity_F64typeOfIRExpr(irsb->tyenv,e) == Ity_I32typeOfIRExpr(irsb->tyenv,e) == Ity_F32typeOfIRExpr(irsb->tyenv,e) == Ity_F64dres->whatNext == Dis_StopHeretypeOfIRExpr(irsb->tyenv,e) == Ity_I16tyE == Ity_I32 || tyE == Ity_I16 || tyE == Ity_I8typeOfIRTemp(irsb->tyenv,t1) == Ity_I32typeOfIRTemp(irsb->tyenv, tres) == tytypeOfIRTemp(irsb->tyenv, texpVal) == tygregOfRM(rm) == 2 || gregOfRM(rm) == 4 || gregOfRM(rm) == 6size == 1 || size == 2 || size == 4op8 == Iop_Add8 || op8 == Iop_Sub8dis_Grp2(Reg): unhandled case(x86)vbi->guest_stack_redzone_size == 0guest_EIP_bbstart + delta == guest_EIP_curr_instr%%edx = client_request ( %%eax ) typeOfIRExpr(irsb->tyenv, sseround) == Ity_I32opc == 0x27 || opc == 0x2F || opc == 0x37 || opc == 0x3Fx86g_calculate_daa_das_aaa_aastypeOfIRExpr(irsb->tyenv, sw) == Ity_I16vex x86->IR: unhandled instruction bytes: 0x%x 0x%x 0x%x 0x%x disInstr_X86: inconsistency in LOCK prefix handlingU !&+05:????CFJNRVZZ``e?RV??????jnrvz~z" $Ë$Ë4$ GNUzR| PLA y AI F AI F AY F AI F AI @pGA  AH \ KAGI GKAGx`AA ALY A AAE J A GAE Q A GAF Q A GAF \ L @0@tA` A K C O A G I G I G A G ,tYAf  I H H H H H 4An A G I G I G I G I G I G I G I G I G I G I G I G I G I G I G I G A G $4`#AX AF AAl\}AA AAPBJ B$L(B,L0B4JAAA A$F(L,A0B4E8HKA AA8=AA MFJEH A$E(H AA|PAC CLHFANBFAHEFE H$A(E,F0E4HA  AAK G KAG F GKAG AA AANI B$J(B,L0B4L8B  R pBc u `!       H! `  "  ; T hm  t!    p) + m Cp @~  ? 2   & # T  Y06&|-S4;ěB^I N0 S X ]3 b< gB l= q. v8 {G Z  h o  q s v x { ~          D l      # )- / 5 ; A: GF M Sc Yy _ e k q w }( P x           H p    6 M * : & 2 . X  b  m % +o 1 7 = C I O U [ a\ g$ m@ sx y  <         h      - "  I   R w _ #n * 1 8 ?Y F M T! [ b  i p w/ ~= K  f  t            J P S  ,  ? &[ -] 4Y ; Bl I P W ^ e} l s z | F $ N      V [ + = p       4 e  "v ) 0a 7j > E L S Z_ a h op vf } D 6 4 F 1  S  Y E      `   &    ] % , 3 : A HH O V ] d k r y f    % O 6   A k         /    ! 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MhP‹4P1҉oPF@44P44PUWVS\D$D$pT$$D$0$L$,D$ D$LD$HD$XD$TD$P  D$43D$x(T$ ‰D$(>$D$t gL$ȉ ʃʃ T$ ʃ@ D$ t$xt$xL$ȃ҃  ED$ T$ <L?>t&<RЃ88t̓&뿋$D$G= ==(D$GUWt$L$$^ D$T$ |$GXD$<JB<D<6R%S<L$ D9$1@D$ 1 D$81D$len == 0dres->continueAt == 0amd64g_dirtyhelper_FINITepartIsReg(mod_reg_rm) szToITy(%d) szToITy(amd64)getIRegRAX(amd64)widenUto640setFlags_DEP1_DEP2(amd64)setFlags_DEP1(amd64)setFlags_MUL(amd64)isPlausibleIRType(ty)i < 256i < 0x100000000ULLszB >= 0szB == 128amd64 %fs segment overrideamd64 %gs segment overridef%s%c %s fucomi%s %%st(0),%%st(%u) laneno >= 0 && laneno < 4amd64g_calculate_rflags_claneno >= 0 && laneno < 2IS_VALID_PFX(pfx)laneno >= 0 && laneno < 8getSDisp(amd64)t0 && *t0 == IRTemp_INVALIDt1 && *t1 == IRTemp_INVALIDlo3bits < 8amd64g_calculate_mmx_psadbwi < 0x10000ULLmkU(amd64)amd64g_calculate_mmx_pmaddwdtyE == tyNamd64g_calculate_pclmult2 && *t2 == IRTemp_INVALIDt3 && *t3 == IRTemp_INVALIDguardvepartIsReg(modrm)%spmovmskb %s,%s amd64g_calc_mpsadbwrestart_point == 0mkSzMask(amd64)!carryingdis_op_imm_A(amd64,guest)%s%c $%lld, %s amd64g_calculate_rflags_allepartIsReg(rm)%s $%d,%s %s $%d,%s,%s %smovmskpd %s,%s pfx == clearSegBits(pfx)%s%c %smaskmovdqu %s,%s %smovmskps %s,%s %spextrw $%u,%s,%s imulmul%s%c %s codegen_div(amd64)%cs:%ds:%es:%fs:%gs:%ss:%s%lld(,%s)%s%lld(,%s,%d)%s(%s,%s)%s(%s,%s,%d)%s%lld(%s,%s)%s%lld(%s,%s,%d)%s %s,%s,%s %s(%s)%s%lld(%s)disAMode(amd64): not an addr!%s%lld(%%rip)%s%lld%spshufd $%d,%s,%s %spshuf%cw $%u,%s,%s %smovddup %s,%s %spmovsxbq %s,%s %spmovsxwq %s,%s %spmov%cxbw %s,%s %spmov%cxbd %s,%s %spmovzxbq %s,%s %spmov%cxwd %s,%s %spmovzxwq %s,%s %spmov%cxdq %s,%s vcvtph2ps %s,%s !epartIsReg(modrm)gregOfRexRM(pfx,modrm) == 3%sstmxcsr %s amd64g_create_mxcsr1==getRexW(pfx)%spextrq $%d, %s,%s imul%c $%lld, %s, %s keepflag == WithFlagNone%s%c %s,%s mov%c %s,%s mov%c%c%c %s,%s am_sz == 1sz == 2 || sz == 4 || sz == 8sh%cd%c %s, %s, %s sz == 8amd64g_calculate_RCRamd64g_calculate_RCLwidenSto64%s%c %s, %s topc == 0x2D || opc == 0x2C%scvt%sss2si %s,%s %scvt%ssd2si %s,%s 0==getRexW(pfx)%spextrw $%d, %s,%s %spextrd $%d, %s,%s %sextractps $%d, %s,%s cmpxchg%c %s,%s rcbt%s%c %s, %s sz == 8 || sz == 4 || sz == 2bs%c%c %s, %s %smovs%cdup %s,%s addswadddsubdaddwsubswsubw%sph%s %s,%s %sphminposuw %s,%s qdw 0x%x dis_MMXop_regmem_to_reghName == NULLhAddr == NULLhName != NULLhAddr != NULL%s%s %s, %s %s %s,%s uopc == 0x2F || opc == 0x2E%s%scomisd %s,%s %s%scomiss %s,%s sz == 4 || sz == 8%s $%u,%s,%s,%s opFn == NULLopFn != NULLvcvtps2ph $%u,%s,%s %s %s,%s,%s,%s %scvt%spd2dq %s,%s %scvt%spd2dqx %s,%s vmovs%cdup %s,%s vcvt%spd2dq %s,%s vcvt%spd2dqy %s,%s %scvtps2pd %s,%s %scvtdq2pd %s,%s %scvtpd2ps %s,%s gregOfRexRM(pfx,modrm) == 2%sldmxcsr %s amd64g_check_ldmxcsr%scvt%sps2dq %s,%s %scvtdq2ps %s,%s !preZero!preSwap%s $%u,%s,%s pspd%s%stest%s %s,%s v%stest%s %s,%s declastencdecenclast,imcamd64g_dirtyhelper_AES%saes%s %s,%s%s%s %spcmp%cstr%c $%x,%s,%s (opc & 0x03) == 0x03amd64g_dirtyhelper_PCMPxSTRx%saeskeygenassist $%x,%s,%s vcvt%sps2dq %s,%s vpshuf%cw $%u,%s,%s vph%s %s,%s vpmov%cxbw %s,%s vpmov%cxbd %s,%s vpmov%cxwd %s,%s vpmov%cxdq %s,%s !isLoad && !isYMM%spextrb $%d, %s,%s %spextrb $%d,%s,%s palignr $%lld,%s,%s palignr $%lld%s,%s subaddh%sps %s,%s h%spd %s,%s addsubpd %s,%s addsubps %s,%s lddqu %s,%s xadd%c %s, %s test%c $%lld, %s not%c %s neg%c %s div%c %s idiv%c %s popcnt%c %s, %s tzcnt%c %s, %s lzcnt%c %s, %s pshufb %s,%s ph%s %s,%s pmaddubsw %s,%s psign%s %s,%s pmulhrsw %s,%s pabs%s %s,%s blendvpdblendvpspblendvbpminsbpmaxsbpmaxsdpminsdpmaxuwpminuwpminudpmaxudamd64g_calc_crc32lamd64g_calc_crc32bamd64g_calc_crc32wamd64g_calc_crc32qnmpmuldq %s,%s pcmpeqqmovntdqa %s,%s packusdw %s,%s pcmpgtqpmulld %s,%s crc32b %s,%s nm && fnmovbe %s,%s adcxadoxmovd %s, %s movd{64} %s, %s movq %s, %s mov(nt)q %s, %s paddpaddspadduspsubpsubspsubuspmulhwpmullwsz == 4pmaddwdpcmpeqpcmpgtpackssdwpacksswbpackuswbpunpckhpunpcklpandpandnporpxorpsllwpslldpsllqpsrlwpsrldpsrlqpsrawpsradmaskmovq %s,%s roundps $%d,%s,%s roundpd $%d,%s,%s rounds%c $%d,%s,%s blendps $%d, %s,%s blendpd $%d, %s,%s pblendw $%d, %s,%s pinsrb $%d,%s,%s insertps $%u, %s,%s pinsrd $%d, %s,%s pinsrq $%d, %s,%s dpps $%d, %s,%s dppd $%d, %s,%s mpsadbw $%d, %s,%s pclmulqdq $%d, %s,%s fsinfcosfcoms %s fcomps %s subrdivdivrf%s%s st(%u), st(%u) fcom %%st(0),%%st(%u) fcomp %%st(0),%%st(%u) flds %s fsts %s fstps %s amd64g_dirtyhelper_FLDENVfldenv %s fldcw %s amd64g_check_fldcwamd64g_dirtyhelper_FSTENVfnstenv %s fnstcw %s amd64g_create_fpucwunhandled opc_aux = 0x%2x first_opcode == 0xD9 fld %%st(%u) fxch %%st(%u) fchs fabs amd64g_calculate_FXAMfxam fld1 fldl2t fldl2e fldpi fldlg2 fldln2 fldz f2xm1 fyl2x fptan fpatan fxtract x86amd64g_calculate_FXTRACTfprem1 fincstp fprem fyl2xp1 fsqrt fsincos frndint fscale %s fiaddl %s fimull %s fisubl %s fisubrl %s fidivrl %s first_opcode == 0xDA fcmovb %%st(%u), %%st(0) fcmovz %%st(%u), %%st(0) fcmovbe %%st(%u), %%st(0) fcmovu %%st(%u), %%st(0) fucompp %%st(0),%%st(1) fildl %s fisttpl %s fistl %s fistpl %s amd64g_dirtyhelper_loadF80lefldt %s amd64g_dirtyhelper_storeF80lefstpt %sfirst_opcode == 0xDB fcmovnb %%st(%u), %%st(0) fcmovnz %%st(%u), %%st(0) fcmovnbe %%st(%u), %%st(0) fcmovnu %%st(%u), %%st(0) fnclex fninit fcoml %s fcompl %s fldl %s fistppll %s fstl %s fstpl %s amd64g_dirtyhelper_FRSTORSamd64g_dirtyhelper_FRSTORfrstors %s frstor %s amd64g_dirtyhelper_FNSAVESamd64g_dirtyhelper_FNSAVEfnsaves %s fnsave %s fnstsw %s first_opcode == 0xDD ffree %%st(%u) fst %%st(0),%%st(%u) fstp %%st(0),%%st(%u) fucom %%st(0),%%st(%u) fucomp %%st(0),%%st(%u) fiaddw %s fimulw %s fisubw %s fisubrw %s fidivrw %s first_opcode == 0xDE fcompp %%st(0),%%st(1) fildw %s fisttps %s fists %s fistps %s fildll %s fistpll %s first_opcode == 0xDF ffreep %%st(%d) fnstsw %%ax (assumed taken)(assumed not taken)%gs%es%ss%ds%fs%cscwd cltd cqo rep ; ret ret oradcsbbandxorcmppush%c %s pop%c %s movslq %s,%s push%c $%lld bnd ; j%s-8 0x%llx %s testxchg%c %s, %s nameSReg(amd64)mov %s,%s lea%c %s, %s popl %s rep nop (P4 pause) nop regLo3 < 8cltqcwtl cbw fwait pushf%c sz == 2 || sz == 4popf%c sahf lahf mov%c %s0x%llx, %s mov%c %s, %s0x%llx rep movsmovsrepe cmpsrep stosstoslodsrepne scasrepe scasscasmovb $%lld,%s movabsq $%lld,%s mov%c $%lld,%s ret $%lld mov%c $%lld, %s xbeginq 0x%llx xabort $%denter $%u, $0 leave int $0x3 int $0xD2 %clloop%s%s 0x%llx jecxz 0x%llx jrcxz 0x%llx in%c $%d,%s %dxin%c %s,%s sz == 1 || sz == 2 || sz == 4amd64g_dirtyhelper_INout%c %s,$%d out%c %s,%s amd64g_dirtyhelper_OUTcall 0x%llx jmp 0x%llx jmp-8 0x%llx cmc clc stc disInstr(x64)(cmc/clc/stc)cld std nameGrp4(amd64)%sb %s nameGrp5(amd64)vpermqvpermpdvpblendd $%u,%s,%s,%s vpermilps $%u,%s,%s vpermilpd $%u,%s,%s vperm2f128 $%u,%s,%s,%s vroundps $%d,%s,%s vroundpd $%d,%s,%s vrounds%c $%d,%s,%s,%s vblendps $%u,%s,%s,%s vblendpd $%u,%s,%s,%s vpblendw $%u,%s,%s,%s vpalignr $%u,%s,%s,%s vinsertf128 $%u,%s,%s,%s vextractf128 $%u,%s,%s vpinsrb $%d,%s,%s,%s vpinsrd $%d,%s,%s,%s vpinsrq $%d,%s,%s,%s vinserti128 $%u,%s,%s,%s vextracti128 $%u,%s,%s vdpps $%d,%s,%s,%s vdppd $%d,%s,%s,%s vmpsadbw $%d, %s,%s,%s vpclmulqdq $%d, %s,%s,%s vperm2i128 $%u,%s,%s,%s vblendvpsvblendvpdvpblendvbvfm%s%c %s,%s,%s,%srorx %d,%s,%s naddsubsubadd231213132sdssvpshufbvpmaddubswvpsign%c %s,%s,%s vpmulhrsw %s,%s,%s vpermilps %s,%s,%s vpermilpd %s,%s,%s vpermpsvbroadcastss %s,%s vbroadcastsd %s,%s vbroadcastf128 %s,%s vpabsbvpabswvpabsdvpmovsxbq %s,%s vpmovsxwq %s,%s vpmuldqvpcmpeqqvmovntdqa %s,%s vpackusdwvmaskmovpsvmaskmovpdvpmovzxbq %s,%s vpmovzxwq %s,%s vpermdvpcmpgtqvpminsbvpminsdvpminuwvpminudvpmaxsbvpmaxsdvpmaxuwvpmaxudvpmulldvpsrlvdvpsrlvqvpsravdvpsllvdvpsllvqvpbroadcastd %s,%s vpbroadcastq %s,%s vbroadcasti128 %s,%s vpbroadcastb %s,%s vpbroadcastw %s,%s vpmaskmovdvpmaskmovqvpgatherddvpgatherdqvpgatherqdvpgatherqqvgatherdpsvgatherdpdvgatherqpsvgatherqpddis_FMA(amd64)vf%sm%s%s%s %s,%s,%s andn %s,%s,%s blsi %s,%s blsmsk %s,%s blsr %s,%s bzhi %s,%s,%s pdep %s,%s,%s amd64g_calculate_pdeppext %s,%s,%s amd64g_calculate_pextmulx %s,%s,%s sarxshlxshrxbextr %s,%s,%s ht1t2ntat0mrex64/movupd %s,%s movsd %s,%s movss %s,%s movups %s,%s movlpd %s, %s movhlps %s, %s movlps %s, %s unpck%sps %s,%s movhpd %s,%s movhps %s,%s prefetch%s %s movapd %s,%s movaps %s,%s cvtpi2ps %s,%s cvtsi2ss %s,%s cvtsi2ssq %s,%s cvtsi2sdl %s,%s cvtsi2sdq %s,%s cvtpi2pd %s,%s movntp%s %s,%s cvt%sps2pi %s,%s cvt%spd2pi %s,%s cvt%spf2pi %s,%s sqrtsssqrtpssqrtsdsqrtpdrsqrtssrsqrtpsrcpssrcppsandpsandpdandnpsandnpdorpsorpdxorpdxorpsaddpsaddssaddsdaddpdmulsdmulssmulpsmulpdcvtss2sd %s,%s cvtsd2ss %s,%s subsssubsdsubpssubpdminpsminssminsdminpddivsddivpsdivssdivpdmaxpsmaxssmaxsdmaxpdpunpcklbwpunpcklwdpunpckldqpcmpgtbpcmpgtwpcmpgtdpunpckhbwpunpckhwdpunpckhdqpunpcklqdqpunpckhqdqsz == 2 || sz == 8mov%c %s, %s movdqa %s,%s movdqu %s,%s pshufw $%d,%s,%s psrldq $%d,%s pslldq $%d,%s pcmpeqbpcmpeqwpcmpeqdmovdqu %s, %s movdqa %s, %s sfence %sfence clflush %s %sfxsave %s %sfxrstor %s %sxsave %s %sxrstor %s cmppscmpsscmpsdcmppdmovnti %s,%s pinsrw $%d,%s,%s pextrw $%d,%s,%s shufps $%d,%s,%s shufpd $%d,%s,%s paddqmovq2dq %s,%s movq %s,%s movdq2q %s,%s pmovmskb %s,%s psubusbpsubuswpminubpaddusbpadduswpmaxubpavgbpavgwpmuluhpmulhuwmovntq %s,%s movntdq %s,%s psubsbpsubswpminswpaddsbpaddswpmaxswpmuludq %s,%s pmaddwd %s,%s psadbwpsadbw %s,%s psubbpsubwpsubdpsubqpaddbpaddwpadddamd64g_dirtyhelper_CPUID_avx2sgdt %s sidt %s amd64g_dirtyhelper_SxDTxgetbv xend xtest amd64g_dirtyhelper_RDTSCPrdtscp syscall ud2 prefetch %s prefetchw %s nop%c nop%c %s amd64g_dirtyhelper_RDTSCrdtsc cmov%s %s,%s j%s-32 0x%llx %s set%s %s bndmk %s, %%bnd%d bndcl %s, %%bnd%d bndcu %s, %%bnd%d bndcn %s, %%bnd%d bndmov %s, %%bnd%d bndmov %%bnd%d, %s bndldx %s, %%bnd%d bndstx %%bnd%d, %s cpuid $%dimul%c %s, %s nameGrp8(amd64)%s%c $0x%llx, %s cmpxchg8b %s amd64g_dirtyhelper_RDRANDrdrand %sbswapl %s bswapq %s {f}emms vmovsd %s,%s vmovsd %s,%s,%s vmovss %s,%s vmovss %s,%s,%s vmovupd %s,%s vmovups %s,%s vmovddup %s,%s vmovhlps %s,%s,%s vmovlpd %s,%s,%s vmovlpd %s,%s vunpck%sps %s,%s vunpck%spd %s,%s vmovlhps %s,%s,%s vmovhp%c %s,%s,%s vmovhp%c %s,%s vmovapd %s,%s vmovaps %s,%s vcvtsi2sdl %s,%s,%s vcvtsi2sdq %s,%s,%s vcvtsi2ssq %s,%s,%s vcvtsi2ssl %s,%s,%s vmovntp%c %s,%s vmovmskps %s,%s vsqrtssvsqrtpsvsqrtsdvsqrtpdvrsqrtssvrsqrtpsvrcpssvrcppsvandpdvandpsvorpdvorpsvxorpdvxorpsvaddsdvaddssvaddpsvaddpdvmulsdvmulssvmulpsvmulpdvcvtps2pd %s,%s vcvtpd2psy %s,%s vcvtsd2ss %s,%s,%s vcvtss2sd %s,%s,%s vcvtdq2ps %s,%s vsubsdvsubssvsubpsvsubpdvminsdvminssvminpsvminpdvdivsdvdivssvdivpsvdivpdvmaxsdvmaxssvmaxpsvmaxpdvpunpcklbwvpunpcklwdvpunpckldqvpacksswbvpcmpgtbvpcmpgtwvpcmpgtdvpackuswbvpunpckhbwvpunpckhwdvpunpckhdqvpackssdwvpunpcklqdqvpunpckhqdqsz == 2vmovd %s, %s vmovq %s, %s vmovdq%c %s,%s vpshufd $%d,%s,%s vpsrlwvpsrawvpsllwvpsrldvpsradvpslldvpsrldq $%d,%s,%s vpslldq $%d,%s,%s vpsrlqvpsllqvpcmpeqbvpcmpeqwvpcmpeqdvzeroupper vzeroall vh%spd %s,%s,%s vmovq %s,%s vmovd %s,%s vcmpsdvcmpssvcmppdvcmppsvpinsrw $%d,%s,%s vshufps $%d,%s,%s,%s vshufpd $%d,%s,%s,%s vaddsubpdvaddsubpsvpaddqvpmullwvpmovmskb %s,%s vpsubusbvpsubuswvpminubvpandvpaddusbvpadduswvpmaxubvpandnvpavgbvpavgwvpmulhuwvpmulhwvcvtdq2pd %s,%s vmovntdq %s,%s vpsubsbvpsubswvpminswvporvpaddsbvpaddswvpmaxswvpxorvlddqu %s,%s vpmuludqvpmaddwdvpsadbwvpsubbvpsubwvpsubdvpsubqvpaddbvpaddwvpadddNONE0F380F0F3Aguest_RIP_next_assumed == 0 0x%llx: dres.whatNext == Dis_StopHere%%rax = guest_NRADDR call-noredir *%%rax IR injection lock esc == ESC_NONEguest_arch == VexArchAMD64x2 >= x1assumed next %%rip = 0x%llx actual next %%rip = 0x%llx %ymm0%ymm1%ymm2%ymm3%ymm4%ymm5%ymm6%ymm7%ymm8%ymm9%ymm10%ymm11%ymm12%ymm13%ymm14%ymm15%xmm0%xmm1%xmm2%xmm3%xmm4%xmm5%xmm6%xmm7%xmm8%xmm9%xmm10%xmm11%xmm12%xmm13%xmm14%xmm15%mm0%mm1%mm2%mm3%mm4%mm5%mm6%mm7???btbtsbtrbtcinccall*jmp*pushrolrorrclrcrshlshrsar%dl%bl%spl%bpl%sil%dil%r8b%r9b%r10b%r11b%r12b%r13b%r14b%r15b%ah%ch%dh%bh%cx%bx%sp%bp%si%di%r8w%r9w%r10w%r11w%r12w%r13w%r14w%r15w%ecx%edx%ebx%esp%ebp%esi%edi%r8d%r9d%r10d%r11d%r12d%r13d%r14d%r15d%rcx%rdx%rbx%rsp%rbp%rsi%rdi%r8%r9%r10%r11%r12%r13%r14%r15bwdbwd @ @  @ @  $ CDEBCDEBDCBBDCBBCDEBCDEBDCBBDCBjmp_litputIRegVputYMMRegLane32Fdis_FMAdis_VMASKMOVputYMMRegLane32dis_AVX_var_shiftV_byEdis_PHADD_256dis_AVX256_shiftV_byEdis_AVX128_shiftV_byEputYMMRegdis_VEX_NDS_256_AnySimdPfx_0F_WIGdis_VEX_NDS_128_AnySimdPfx_0F_WIGdis_PMOVMSKB_256dis_AVX256_cmp_V_E_to_Gdis_AVX128_cmp_V_E_to_GbreakupV256toV128sdis_AVX256_shiftE_to_V_immdis_AVX128_shiftE_to_V_immputYMMRegLane64FymmGuestRegLane32offsetputYMMRegLane64ymmGuestRegLane64offsetbreakupV256to64sdis_ESC_0F__VEXdis_PCMPISTRI_3Adis_PEXTRQdis_PEXTRDdis_PEXTRWdis_AESxxmmGuestRegLane16offsetdis_ESC_0F38__SSE4math_PABS_MMXdis_PSIGN_helperdis_PHADD_128dis_ESC_0F38__SupSSE3putXMMRegbreakupV128to64sdis_SSE_shiftG_byEdis_PMOVMSKB_128breakup64to16sfindSSECmpOpdis_SSE_cmp_E_to_Gdis_XRSTORdis_XSAVEdis_FXRSTORdis_FXSAVEput_sse_roundingmodedis_LDMXCSRdis_STMXCSRputXMMRegLane64dis_SSE_shiftE_immputXMMRegLane32FxmmGuestRegLane64offsetputXMMRegLane64FymmGuestRegLane128offsetputYMMRegLane128dis_COMISSdis_COMISDdis_CVTxSD2SIdis_CVTxSS2SIbreakupV128to32sxmmGuestRegOffsetxmmGuestRegLane32offsetputXMMRegLane32dis_ESC_0F__SSE2dis_MMX_shiftE_immdis_MMX_shiftG_byEdis_MMXop_regmem_to_regputMMXRegdis_MMXmath_BSWAPdis_bs_E_Gdis_bt_G_Edis_Grp8_Immdis_SHLRD_Gv_Evdis_ESC_0Fdis_Grp5setFlags_INC_DECputIRegAHmake_redzone_AbiHintgetIRegRDXgetIReg32mkAnd1putIReg32mkU32put_ST_TAGput_C3210put_ST_UNCHECKEDput_emwarnput_ftopput_fprounddis_FPUsetFlags_DEP1_DEP2_shiftdis_Grp2getIRegCLmkU8getIReg64rexXnameIReg64rexXdisAModeputIRegEdis_retnameIRegRexBputIRegRexBdis_string_opdis_REP_opdis_op_imm_AputIRegRDXmkSizedOpputIReg16getIReg16codegen_xchg_rAX_RegnameIRegputIRegGmkU16casLEhelper_ADCX_ADOXdis_op2_E_Gdis_Grp1positiveIse_AMD64Condcodejcc_01dis_imul_I_E_GgetIRegRexBsetFlags_DEP1helper_SBBhelper_ADCeregOfRexRMoffsetIRegEoffsetIRegoffsetIRegGdis_op2_G_EsetFlags_DEP1_DEP2dis_ESC_NONEjmp_tregputIReg64newTempgetIRegRAXputIRegRAXdisInstr_AMD64_WRKdisInstr_AMD64op8 == Iop_Add8 || op8 == Iop_Sub8 || op8 == Iop_Mul8 || op8 == Iop_Or8 || op8 == Iop_And8 || op8 == Iop_Xor8 || op8 == Iop_Shl8 || op8 == Iop_Shr8 || op8 == Iop_Sar8 || op8 == Iop_CmpEQ8 || op8 == Iop_CmpNE8 || op8 == Iop_CasCmpNE8 || op8 == Iop_Not8integerGuestReg64Offset(amd64)typeOfIRExpr(irsb->tyenv,x) == Ity_I1typeOfIRExpr(irsb->tyenv,y) == Ity_I1dres->whatNext == Dis_Continuedres->jk_StopHere == Ijk_INVALIDcond >= AMD64CondO && cond <= AMD64CondNLEtypeOfIRExpr(irsb->tyenv,e) == Ity_I64typeOfIRExpr(irsb->tyenv, value) == Ity_I8typeOfIRExpr(irsb->tyenv, value) == Ity_F64typeOfIRExpr(irsb->tyenv,e) == Ity_I32typeOfIRTemp(irsb->tyenv, new_rsp) == Ity_I64typeOfIRTemp(irsb->tyenv, nia) == Ity_I64typeOfIRExpr(irsb->tyenv,e) == Ity_V256amd64toIR: unimplemented feature typeOfIRExpr(irsb->tyenv, e) == Ity_I32typeOfIRExpr(irsb->tyenv,e) == Ity_F64typeOfIRExpr(irsb->tyenv,e) == Ity_V128typeOfIRExpr(irsb->tyenv, e) == Ity_I64typeOfIRExpr(irsb->tyenv,e) == Ity_F32typeOfIRExpr(irsb->tyenv,e) == szToITy(sz)sz == 8 || sz == 4 || sz == 2 || sz == 1typeOfIRExpr(irsb->tyenv, e) == szToITy(sz)dres->whatNext == Dis_StopHeretyE == Ity_I64 || tyE == Ity_I32 || tyE == Ity_I16 || tyE == Ity_I8setFlags_DEP1_DEP2_shift(amd64)typeOfIRTemp(irsb->tyenv, tres) == tytypeOfIRTemp(irsb->tyenv, texpVal) == tyamd64g_dirtyhelper_XSAVE_COMPONENT_0amd64g_dirtyhelper_XSAVE_COMPONENT_1_EXCLUDING_XMMREGSgregLO3ofRM(rm) == 2 || gregLO3ofRM(rm) == 4 || gregLO3ofRM(rm) == 6amd64g_dirtyhelper_XRSTOR_COMPONENT_0amd64g_dirtyhelper_XRSTOR_COMPONENT_1_EXCLUDING_XMMREGStypeOfIRExpr(irsb->tyenv, e) == Ity_I8extra_bytes >= 0 && extra_bytes < 10size == 2 || size == 4 || size == 8flag == WithFlagNone || flag == WithFlagCarrysz == 1 || sz == 2 || sz == 4 || sz == 8dis_Grp2(Reg): unhandled case(amd64)vbi->guest_stack_redzone_size == 128amd64g_calculate_sse_phminposuw0==getVexL(pfx) && 0==getRexW(pfx)typeOfIRExpr(irsb->tyenv, sseround) == Ity_I32amd64g_dirtyhelper_AESKEYGENASSIST1==getVexL(pfx) && 0==getRexW(pfx)typeOfIRExpr(irsb->tyenv, sw) == Ity_I16typeOfIRExpr(irsb->tyenv,e) == Ity_I16count == 1 || count == 2 || count == 4 || count == 8amd64g_dirtyhelper_CPUID_avx_and_cx16amd64g_dirtyhelper_CPUID_sse42_and_cx16amd64g_dirtyhelper_CPUID_baselineguest_RIP_next_mustcheck == False%%rdx = client_request ( %%rax ) delta - delta_at_primary_opcode >= 0delta - delta_at_primary_opcode < 16vex amd64->IR: unhandled instruction bytes: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x vex amd64->IR: REX=%d REX.W=%d REX.R=%d REX.X=%d REX.B=%d vex amd64->IR: VEX=%d VEX.L=%d VEX.nVVVV=0x%x ESC=%s vex amd64->IR: PFX.66=%d PFX.F2=%d PFX.F3=%d disInstr_AMD64: disInstr miscalculated next %ripdisInstr_AMD64: inconsistency in LOCK prefix handling2#2)2/252;2A2G2M2S2Y2`2g2n2u2|222222222222222222222233 33333333 3$3I (3(3.3.3333$3I 33333383<3@3D3H3L3H3P3T3X3\3a3f3k3p3u3z333333T3X3333336333333333333333344 4444!4'4-43494?4E4J4O4T4Y4^4c4h4l4p4u4z4444$Ë$Ë4$ GNUzR| (LB CAAA LHAd K a G G  KAGN G  KAGF G KAG4An A G I G I G I G I G I G I G I G I G I G I G I G I G I G I G I G A G h(Au J Q G H H V B H H G  KAGF G  KAGF G  KAGE G lGC A~  AAE K  AAC s KAG J C  AAK D  AAA G4TAc D L D G A G A G 4<SAb E K E F B F A G tpAAA AAN  $K(A,G0J \ AA AAH O $K(A,G0F G $K(A,G0F G $K(A,G0F G $K(A,G0F $.E\ A G (.E\ A G (H 3A\ AF AA A G (t` <E\ FF AA A G  $AC AOICFAA A AAE zGFAZGFAA A AAD DGFAIGFAN|, AC CLHFANBFAHEFE H$A(E,F0E4HA  AAK G KAG F GKAG d mAC CANGL F$A(E,F0H4H8ADD CjFJE H$A(E,F0A4HAFFAA  AAH EEFA F$F(HA AA#?AA AdDFARBFF HA  AAC S KAG J HEFB F$F(HA  AAD G KAG E X$@EA AAN,]0F,S0B4X8H,S0B4F8KpEA AAvFOBJ JSBO A$F(F,HPBF A$F(F,F0F4JAAE F$F(I,F0H4A8E9AB BD AAA C `L1AC AAN<@ADFHXLAPETLXR\J\C W+jK  %KP[H [G OJ  `"$/L  HP_RHI  kv@K @hK 0 @OL OI ?hI 4 o>K  WbpI  {0 I  w\I  `!/$I "oH  #*D  C#^$e@%w0&% ''I  P(() *PE P++,k"@-3I L.\@E u/E 0{H @1{\G 1 HF  $2O3J L2](E vp344055|I  6C  7 pC , 8F 9_Y D r 9  G : J  K  < = `> ? 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t$,uUQRSPPiuUT$,$u&RQPXZ4멅,PXPYGt$,u9QRSPPƴP[ōPYܱD$,L$ȃPP^]]D$,XL$ȃPPY[.RQt$ PD$,D$PPt$VPh/PƋ0 =$VPP0D$,tD$PPt$VPh0Pt$LV PVPƋ0=fRPhPPD$D<D$,DjPPƋ0=V$t.PP T$D$RPP¸h@h$P¸ijP¸PD$ T$RPP¸ )RQt$ PxRQt$8t$,P:UPhpPPL$ȃPPY[RQt$ PRQt$ PaD$ PD$ PUt$ PD$ PD$ PUt$ Pg|$HD$;!̰|$OD$;馰D$;鋰;ѭD$;Qf|$HD$;]@RQt$ PwRQt$ PRRQt$ Pt$t$P ίT$$։ ՉщL$F}D$jjP ‰T$jPËD$)SPh+t$$T$0RP ‹$菎D$,t$UVt$ PD$?.ٮjP[XZj|LRQt$ PRQt$8t$,Ppriv/guest_ppc_toIR.carchreg < 32archreg < 64set_XER_CA: op = %u set_XER_CA(ppc64)set_XER_CA(ppc)isPlausibleIRType(ty)cr < 8!mode64is_BCDstring128_helperaddr_align: align = %u addr_align(ppc)getGST_masked(ppc): reg = %ugetGST_masked(ppc)szB >= 0t0 && *t0 == IRTemp_INVALIDt1 && *t1 == IRTemp_INVALIDt2 && *t2 == IRTemp_INVALIDt3 && *t3 == IRTemp_INVALIDfmrgew fr%u,fr%u,fr%u fmrgow fr%u,fr%u,fr%u dis_fp_merge(ppc)(opc2) .dscliq%s fr%u,fr%u,%u dscriq%s fr%u,fr%u,%u dscli%s fr%u,fr%u,%u dscri%s fr%u,fr%u,%u drintxq/drintnq%s fr%u,fr%u dis_dfp_roundq(ppc)(opc2) drintx/drintn%s fr%u,fr%u dis_dfp_round(ppc)(opc2) dadd%s fr%u,fr%u,fr%u dsub%s fr%u,fr%u,fr%u dmul%s fr%u,fr%u,fr%u ddiv%s fr%u,fr%u,fr%u daddq%s fr%u,fr%u,fr%u dsubq%s fr%u,fr%u,fr%u dmulq%s fr%u,fr%u,fr%u ddivq%s fr%u,fr%u,fr%u dxex%s fr%u,fr%u,fr%u diex%s fr%u,fr%u,fr%u dxexq%s fr%u,fr%u diexq%s fr%u,fr%u,fr%u generate_store_C_FPCC_helperxsrqpi %d,v%d,v%d,%d xsrqpix %d,v%d,v%d,%d xsrqpxp %d,v%d,v%d,%d vextublx %d,%d,v%dvextuhlx %d,%d,v%dvextuwlx %d,%d,v%dvextubrx %d,%d,v%dvextuhrx %d,%d,v%dvextuwrx %d,%d,v%ddis_abs_diff(ppc)(instr) vabsdub v%d,v%d,v%d vabsduh v%d,v%d,v%d vabsduw v%d,v%d,v%d dquai%s fr%u,fr%u,fr%u dqua%s fr%u,fr%u,fr%u drrnd%s fr%u,fr%u,fr%u dquaiq%s fr%u,fr%u,fr%u drrndq%s fr%u,fr%u,fr%u mode64dctqpq%s fr%u,fr%u dctfixq%s fr%u,fr%u drdpq%s fr%u,fr%u dcffixq%s fr%u,fr%u dis_av_fp_cmp(ppc)(instr) vcmpeqfp%s v%d,v%d,v%d vcmpgefp%s v%d,v%d,v%d vcmpgtfp%s v%d,v%d,v%d vcmpbfp%s v%d,v%d,v%d dis_av_fp_cmp(ppc)(opc2) dctdp%s fr%u,fr%u drsp%s fr%u,fr%u dctfix%s fr%u,fr%u dcffix%s fr%u,fr%u dis_vx_move(ppc)(instr) mfvsrld %u,r%u mfvsrdd %u,r%u mfvsrws %u,r%u dis_vx_move(ppc)(opc2) dis_av_mult10(ppc)(instr) vmul10cuq v%d,v%d vmul10ecuq v%d,v%d,v%d vmul10uq v%d,v%d vmul10euq v%d,v%d,v%d dis_av_mult10(ppc)(opc2) vpmsumb v%d,v%d,v%d vpmsumd v%d,v%d,v%d vpmsumw v%d,v%d,v%d vpmsumh v%d,v%d,v%d vcfux v%d,v%d,%d vcfsx v%d,v%d,%d vctuxs v%d,v%d,%d vctsxs v%d,v%d,%d vrfin v%d,v%d vrfiz v%d,v%d vrfip v%d,v%d vrfim v%d,v%d dis_av_fp_convert(ppc)(opc2) vand v%d,v%d,v%d vandc v%d,v%d,v%d vor v%d,v%d,v%d vxor v%d,v%d,v%d vnor v%d,v%d,v%d vorc v%d,v%d,v%d vnand v%d,v%d,v%d veqv v%d,v%d,v%d dis_av_logic(ppc)(opc2=0x%x) dis_av_fp_arith(ppc)(instr) vmaddfp v%d,v%d,v%d,v%d vnmsubfp v%d,v%d,v%d,v%d vaddfp v%d,v%d,v%d vsubfp v%d,v%d,v%d vmaxfp v%d,v%d,v%d vminfp v%d,v%d,v%d vrefp v%d,v%d vrsqrtefp v%d,v%d vexptefp v%d,v%d => not implemented vlogefp v%d,v%d dis_av_cipher(ppc)(instr) vcipher v%d,v%d,v%d vcipherlast v%d,v%d,v%d vncipher v%d,v%d,v%d vncipherlast v%d,v%d,v%d vsbox v%d,v%d dis_av_cipher(ppc)(opc2) calculate_XER_OV_32: op = %u calculate_XER_OV_32(ppc)dis_av_load(ppc)(instr) ppc32g_dirtyhelper_LVSppc64g_dirtyhelper_LVSlvsl v%d,r%u,r%u lvsr v%d,r%u,r%u lvebx v%d,r%u,r%u lvehx v%d,r%u,r%u lvewx v%d,r%u,r%u lvx v%d,r%u,r%u lvxl v%d,r%u,r%u dis_av_load(ppc)(opc2) lhbrx r%u,r%u,r%u lwbrx r%u,r%u,r%u ldbrx r%u,r%u,r%u sthbrx r%u,r%u,r%u stwbrx r%u,r%u,r%u stdbrx r%u,r%u,r%u dis_int_ldst_rev(ppc)(opc2) calculate_XER_OV_64: op = %u calculate_XER_OV_64(ppc64)dis_av_store(ppc)(instr) stvebx v%d,r%u,r%u stvehx v%d,r%u,r%u stvewx v%d,r%u,r%u stvx v%d,r%u,r%u stvxl v%d,r%u,r%u dis_av_store(ppc)(opc2) prtyd r%u,r%u dis_int_parity(ppc)(opc2) dis_av_rotate(ppc)(instr) dis_av_rotate(ppc)(opc2) vrlwmi %d,%d,v%dvrldmi %d,%d,v%dvrlwnm %d,%d,v%dvrldnm %d,%d,v%dddedpd %llu,r%u,r%u denbcd %llu,r%u,r%u dis_fp_move(ppc)(instr) fcpsgn%s fr%u,fr%u,fr%u fneg%s fr%u,fr%u fmr%s fr%u,fr%u fnabs%s fr%u,fr%u fabs%s fr%u,fr%u dis_fp_move(ppc)(opc2) fmsubs%s fr%u,fr%u,fr%u,fr%u fmadds%s fr%u,fr%u,fr%u,fr%u fmsub%s fr%u,fr%u,fr%u,fr%u fmadd%s fr%u,fr%u,fr%u,fr%u fnmsub%s fr%u,fr%u,fr%u,fr%u fnmadd%s fr%u,fr%u,fr%u,fr%u dis_fp_multadd(ppc)(opc1) ddedpdq %llu,r%u,r%u stfs fr%u,%d(r%u) stfsu fr%u,%d(r%u) stfd fr%u,%d(r%u) stfdu fr%u,%d(r%u) dis_fp_store(ppc)(instr,b0) stfsx fr%u,r%u,r%u stfsux fr%u,r%u,r%u stfdx fr%u,r%u,r%u stfdux fr%u,r%u,r%u stfiwx fr%u,r%u,r%u dis_fp_store(ppc)(opc2) dis_fp_store(ppc)(opc1) dis_vx_logic(ppc)(instr) xxlxor v%d,v%d,v%d xxlor v%d,v%d,v%d xxlnor v%d,v%d,v%d xxland v%d,v%d,v%d xxlandc v%d,v%d,v%d xxlorc v%d,v%d,v%d xxlnand v%d,v%d,v%d xxleqv v%d,v%d,v%d dis_vx_logic(ppc)(opc2) getGST(ppc): reg = %ugetGST(ppc)slw%s r%u,r%u,r%u sraw%s r%u,r%u,r%u srawi%s r%u,r%u,%d srw%s r%u,r%u,r%u sld%s r%u,r%u,r%u srad%s r%u,r%u,r%u sradi%s r%u,r%u,%u srd%s r%u,r%u,r%u dis_int_shift(ppc)(opc2) dis_int_shift(ppc)(opc1) dis_av_quad(ppc)(instr) vaddcuq v%d,v%d,v%d vadduqm v%d,v%d,v%d vsubcuq v%d,v%d,v%d vsubuqm v%d,v%d,v%d vbpermq v%d,v%d,v%d vaddecuq v%d,v%d,v%d,v%d vaddeuqm v%d,v%d,v%d,v%d vsubecuq v%d,v%d,v%d,v%d vsubeuqm v%d,v%d,v%d,v%d dis_av_quad(ppc)(opc2.2) modud r%u,r%u,r%u moduw r%u,r%u,r%u cnttzw%s r%u,r%u cnttzd%s r%u,r%u modsd r%u,r%u,r%u modsw r%u,r%u,r%u dis_modulo_int(ppc)(opc2) dis_modulo_int(ppc)(opc1) dis_int_cmp(ppc)(flag_L) dis_int_cmp(ppc)(b22) cmpi cr%u,%u,r%u,%d cmpli cr%u,%u,r%u,0x%x dis_int_cmp(ppc)(0x1F,b0) cmp cr%u,%u,r%u,r%u cmpl cr%u,%u,r%u,r%u setb r%u,%d dis_int_cmp(ppc)(opc2) dis_int_cmp(ppc)(opc1) fdivs%s fr%u,fr%u,fr%u fsubs%s fr%u,fr%u,fr%u fadds%s fr%u,fr%u,fr%u fsqrts%s fr%u,fr%u fres%s fr%u,fr%u fmuls%s fr%u,fr%u,fr%u frsqrtes%s fr%u,fr%u dis_fp_arith(ppc)(3B: opc2) fdiv%s fr%u,fr%u,fr%u fsub%s fr%u,fr%u,fr%u fadd%s fr%u,fr%u,fr%u fsqrt%s fr%u,fr%u fsel%s fr%u,fr%u,fr%u,fr%u fre%s fr%u,fr%u fmul%s fr%u,fr%u,fr%u frsqrte%s fr%u,fr%u dis_fp_arith(ppc)(3F: opc2) dis_fp_arith(ppc)(opc1) dis_av_permute(ppc)(instr) vsel v%d,v%d,v%d,v%d vperm v%d,v%d,v%d,v%d dis_av_permute(ppc)(vsldoi) vsldoi v%d,v%d,v%d,%d vpermxor v%d,v%d,v%d,v%d vpermr v%d,v%d,v%d,v%d vmrghb v%d,v%d,v%d vmrghh v%d,v%d,v%d vmrghw v%d,v%d,v%d vmrglb v%d,v%d,v%d vmrglh v%d,v%d,v%d vmrglw v%d,v%d,v%d vextractub v%d,v%d,%d vextractuh v%d,v%d,%d vextractuw v%d,v%d,%d vextractd v%d,v%d,%d vinsertb v%d,v%d,%d vinserth v%d,v%d,%d vinsertw v%d,v%d,%d vinsertd v%d,v%d,%d vspltb v%d,v%d,%d vsplth v%d,v%d,%d vspltw v%d,v%d,%d vspltisb v%d,%d vspltish v%d,%d vspltisw v%d,%d vmrgow v%d,v%d,v%d vmrgew v%d,v%d,v%d dis_av_permute(ppc)(opc2) ty_src == tyty_src == Ity_I32ty_src == Ity_I64putGST(ppc): reg = %uputGST(ppc)tweqi r%u,%d tw%di r%u,%d tdeqi r%u,%d td%di r%u,%d tweq r%u,r%u tw%d r%u,r%u tdeq r%u,r%u td%d r%u,r%u dis_av_procctl(ppc)(instr) mfvscr v%d mtvscr v%d dis_av_procctl(ppc)(opc2) putGST_masked(ppc): reg = %uputGST_masked(ppc)dis_vvec_cmp(ppc)(instr) xvcmpeqdp%s crf%d,fr%u,fr%u xvcmpgedp%s crf%d,fr%u,fr%u xvcmpgtdp%s crf%d,fr%u,fr%u xvcmpeqsp%s crf%d,fr%u,fr%u xvcmpgesp%s crf%d,fr%u,fr%u xvcmpgtsp%s crf%d,fr%u,fr%u dis_vvec_cmp(ppc)(opc2) dcmpo %u,fr%u,fr%u dcmpoq %u,fr%u,fr%u dis_dfp_compare(ppc)(opc2) dtstsf %u,r%u,r%u dtstsfi %u,%u,r%u dtstsfq %u,r%u,r%u dtstsfiq %u,%u,r%u dis_fp_cmp(ppc)(instr) fcmpu crf%d,fr%u,fr%u fcmpo crf%d,fr%u,fr%u dis_fp_cmp(ppc)(opc2) cgdtstd%s %u,r%u,%u dtstd%sq %u,r%u,%u dtstex %u,r%u,r%d dtstexq %u,r%u,r%d dis_byte_cmp(ppc)(opc1) cmprb %u,%u,r%u,r%u cmpeqb %u,r%u,r%u dis_byte_cmp(ppc)(opc2) dis_av_bcd_misc(ppc)(instr) bcdcpsgn. v%d,v%d,v%d dis_av_bcd_misc(ppc)(opc2) xxsldwi v%d,v%d,v%d,%d xxpermdi v%d,v%d,v%d,0x%x xxmrg%cw v%d,v%d,v%d xxsel v%d,v%d,v%d,v%d xxperm v%u,v%u,v%u xxpermr v%u,v%u,v%u xxspltw v%d,v%d,%d dis_av_shift(ppc)(instr) vrlb v%d,v%d,v%d vrlh v%d,v%d,v%d vrlw v%d,v%d,v%d vrld v%d,v%d,v%d vslb v%d,v%d,v%d vslh v%d,v%d,v%d vslw v%d,v%d,v%d vsld v%d,v%d,v%d vsl v%d,v%d,v%d vslo v%d,v%d,v%d vsrb v%d,v%d,v%d vsrh v%d,v%d,v%d vsrw v%d,v%d,v%d vsr v%d,v%d,v%d vsrab v%d,v%d,v%d vsrah v%d,v%d,v%d vsraw v%d,v%d,v%d vsrad v%d,v%d,v%d vsro v%d,v%d,v%d vsrd v%d,v%d,v%d dis_av_shift(ppc)(opc2) dis_av_cmp(ppc)(instr) vcmpequb%s v%d,v%d,v%d vcmpneb%s v%d,v%d,v%d vcmpequh%s v%d,v%d,v%d vcmpneh%s v%d,v%d,v%d vcmpequw%s v%d,v%d,v%d vcmpnew%s v%d,v%d,v%d vcmpnezb%s v%d,v%d,v%d vcmpnezh%s v%d,v%d,v%d vcmpnezw%s v%d,v%d,v%d vcmpequd%s v%d,v%d,v%d vcmpgtub%s v%d,v%d,v%d vcmpgtuh%s v%d,v%d,v%d vcmpgtuw%s v%d,v%d,v%d vcmpgtud%s v%d,v%d,v%d vcmpgtsb%s v%d,v%d,v%d vcmpgtsh%s v%d,v%d,v%d vcmpgtsw%s v%d,v%d,v%d vcmpgtsd%s v%d,v%d,v%d dis_av_cmp(ppc)(opc2) lfs fr%u,%d(r%u) lfsu fr%u,%d(r%u) lfd fr%u,%d(r%u) lfdu fr%u,%d(r%u) dis_fp_load(ppc)(instr,b0) lfsx fr%u,r%u,r%u lfsux fr%u,r%u,r%u lfdx fr%u,r%u,r%u lfdux fr%u,r%u,r%u lfiwax fr%u,r%u,r%u lfiwzx fr%u,r%u,r%u dis_fp_load(ppc)(opc2) dis_fp_load(ppc)(opc1) rlwimi%s r%u,r%u,%d,%d,%d rlwinm%s r%u,r%u,%d,%d,%d slwi%s r%u,r%u,%d srwi%s r%u,r%u,%d rlwnm%s r%u,r%u,r%u,%d,%d rldcl%s r%u,r%u,r%u,%u rldcr%s r%u,r%u,r%u,%u rldic%s r%u,r%u,%u,%u srdi%s r%u,r%u,%u rldicl%s r%u,r%u,%u,%u sldi%s r%u,r%u,%u rldicr%s r%u,r%u,%u,%u rldimi%s r%u,r%u,%u,%u dis_int_rot(ppc)(opc2) dis_int_rot(ppc)(opc1) vclzb v%d,v%d vclzh v%d,v%d vclzw v%d,v%d vclzd v%d,v%d vpopcntb v%d,v%d vpopcnth v%d,v%d vpopcntw v%d,v%d vpopcntd v%d,v%d vgbbd v%d,v%d vbpermd v%d,v%d,v%d lbz r%u,%d(r%u) lbzu r%u,%d(r%u) lha r%u,%d(r%u) lhau r%u,%d(r%u) lhz r%u,%d(r%u) lhzu r%u,%d(r%u) lwz r%u,%d(r%u) lwzu r%u,%d(r%u) dis_int_load(ppc)(Ox1F,b0) lbzux r%u,r%u,r%u lbzx r%u,r%u,r%u lhaux r%u,r%u,r%u lhax r%u,r%u,r%u lhzux r%u,r%u,r%u lhzx r%u,r%u,r%u lwzux r%u,r%u,r%u lwzx r%u,r%u,r%u ldux r%u,r%u,r%u ldx r%u,r%u,r%u lwaux r%u,r%u,r%u lwax r%u,r%u,r%u dis_int_load(ppc)(opc2) ld r%u,%d(r%u) ldu r%u,%d(r%u) lwa r%u,%d(r%u) lq r%u,%d(r%u) dis_int_load(ppc)(opc1) dis_av_multarith(ppc)(instr) vmhaddshs v%d,v%d,v%d,v%d vmhraddshs v%d,v%d,v%d,v%d vmladduhm v%d,v%d,v%d,v%d vmsumudm v%d,v%d,v%d,v%d vmsumubm v%d,v%d,v%d,v%d vmsummbm v%d,v%d,v%d,v%d vmsumuhm v%d,v%d,v%d,v%d vmsumuhs v%d,v%d,v%d,v%d vmsumshm v%d,v%d,v%d,v%d vmsumshs v%d,v%d,v%d,v%d dis_av_multarith(ppc)(opc2) ,1dis_fp_scr(ppc)(instr) mtfsb1%s crb%d dis_fp_scr(ppc)(instr,mcrfs) mcrfs crf%d,crf%d mtfsb0%s crb%d mtfsfi%s crf%u,%d%s mffs%s fr%u mffsce fr%u mffscdrn fr%u,fr%u mffscdrni fr%u,%u mffscrn fr%u,fr%u mffscrni fr%u,%u mffsl fr%u mtfsf%s %d,fr%u (L=1) mtfsf%s %d,fr%u dis_fp_scr(ppc)(opc2) stb r%u,%d(r%u) stbu r%u,%d(r%u) sth r%u,%d(r%u) sthu r%u,%d(r%u) stw r%u,%d(r%u) stwu r%u,%d(r%u) dis_int_store(ppc)(0x1F,b0) stbux r%u,r%u,r%u stbx r%u,r%u,r%u sthux r%u,r%u,r%u sthx r%u,r%u,r%u stwux r%u,r%u,r%u stwx r%u,r%u,r%u stdux r%u,r%u,r%u stdx r%u,r%u,r%u dis_int_store(ppc)(opc2) std r%u,%d(r%u) stdu r%u,%d(r%u) stq r%u,%d(r%u) dis_int_store(ppc)(opc1) vclzlsbb %d,v%d vctzlsbb %d,v%d vnegw v%d,%d,v%dvnegd v%d,%d,v%dvprtybw v%d,v%dvprtybd v%d,v%dvprtybq v%d,v%dvextsb2w v%d,%d,v%dvextsh2w v%d,%d,v%dvextsb2d v%d,%d,v%dvextsh2d v%d,%d,v%dvextsw2d v%d,%d,v%dvctzb v%d,v%dvctzh v%d,v%dvctzw v%d,v%dvctzd v%d,v%dalb%s%s 0x%llx b%s%s 0x%x bc%s%s 0x%x, 0x%x, 0x%x bcctr%s 0x%x, 0x%x blr bclr%s 0x%x, 0x%x dis_int_branch(ppc)(opc2) dis_int_branch(ppc)(opc1) dis_av_pack(ppc)(instr) vpkuhum v%d,v%d,v%d vpkuwum v%d,v%d,v%d vpkuhus v%d,v%d,v%d vpkuwus v%d,v%d,v%d vpkshus v%d,v%d,v%d vpkswus v%d,v%d,v%d vpkshss v%d,v%d,v%d vpkswss v%d,v%d,v%d vpkpx v%d,v%d,v%d vpkudum v%d,v%d,v%d vpkudus v%d,v%d,v%d vpksdus v%d,v%d,v%d vpksdss v%d,v%d,v%d dis_av_pack(ppc)(vA_addr) vupkhsb v%d,v%d vupkhsh v%d,v%d vupklsb v%d,v%d vupklsh v%d,v%d vupkhpx v%d,v%d vupklpx v%d,v%d vupkhsw v%d,v%d vupklsw v%d,v%d dis_av_pack(ppc)(opc2) zdis_fp_round(ppc)(instr) fcfids%s fr%u,fr%u fcfidus%s fr%u,fr%u frsp%s fr%u,fr%u fctiw%s fr%u,fr%u fctiwz%s fr%u,fr%u fctiwu%s%s fr%u,fr%u fctid%s fr%u,fr%u fctidz%s fr%u,fr%u fctidu%s%s fr%u,fr%u fcfid%s fr%u,fr%u fcfidu%s fr%u,fr%u frin%s fr%u,fr%u friz%s fr%u,fr%u frip%s fr%u,fr%u frim%s fr%u,fr%u dis_fp_round(ppc)(opc2) andi. r%u,r%u,0x%x andis r%u,r%u,0x%x ori r%u,r%u,0x%x oris r%u,r%u,0x%x xori r%u,r%u,0x%x xoris r%u,r%u,0x%x extswsli%s r%u,r%u,%u and%s r%u,r%u,r%u andc%s r%u,r%u,r%u cntlzw%s r%u,r%u eqv%s r%u,r%u,r%u extsb%s r%u,r%u extsh%s r%u,r%u nand%s r%u,r%u,r%u nor%s r%u,r%u,r%u mr r%u,r%u or%s r%u,r%u,r%u orc%s r%u,r%u,r%u xor%s r%u,r%u,r%u extsw%s r%u,r%u cntlzd%s r%u,r%u cmpb r%u,r%u,r%u mftgpr r%u,fr%u mffgpr fr%u,r%u popcntd r%u,r%u popcntw r%u,r%u popcntb r%u,r%u bpermd r%u,r%u,r%u dis_int_logic(ppc)(opc2) dis_int_logic(ppc)(opc1) mtcrfmtocrfdis_proc_ctl(ppc)(opc1|b%d) mcrxr crf%d mfcr r%u mfocrf r%u,%u mfxer r%u mfspr r%u (DSCR) mflr r%u mfctr r%u mfspr r%u (TFHAR) mfspr r%u (TFIAR) mfspr r%u (TEXASR) mfspr r%u (TEXASRU) mfspr r%u (PSPB) mfspr r%u (PPR) mfspr r%u (PPR)32 mfvrsave r%u mfspr r%u, SPRG3(readonly) ppcg_dirtyhelper_MFTBmfspr r%u,%uppc32g_dirtyhelper_MFSPR_287mftbu r%umftb r%umftbl r%u%s 0x%x,r%u mtxer r%u mtspr r%u (DSCR) mtlr r%u mtctr r%u mtvrsave r%u mtspr r%u (TFHAR) mtspr r%u (TFIAR) mtspr r%u (TEXASR) mtspr r%u (PSPB) mtspr r%u (PPR) mtspr r%u (PPR32) mfvsrd r%u,vsr%d mfvsrwz r%u,vsr%d mtvsrd vsr%d,r%u mtvsrwa vsr%d,r%u mtvsrwz vsr%d,r%u dis_proc_ctl(ppc)(opc2) ldpx fr%u,r%u,r%u stdpx fr%u,r%u,r%u dis_fp_pair(ppc)(0x1F,b0) lfdp fr%u,%d(r%u) lxsd v%u,%u(r%u) lxssp v%u,%u(r%u) stfdp fr%u,%d(r%u) lxv v%u,%u(r%u) stxv v%u,%u(r%u) stxsd v%u,%u(r%u) stxssp v%u,%u(r%u) dis_fp_pair(ppc)(instr) dis_vx_store(ppc)(instr) stxsiwx %d,r%u,r%u stxvx %u,r%u,r%u stxvl %u,r%u,r%u stxvll %u,r%u,r%u stxsspx %u,r%u,r%u stxsdx %u,r%u,r%u stxsibx %u,r%u,r%u stxsihx %u,r%u,r%u stxvd2x %u,r%u,r%u stxvw4x %u,r%u,r%u stxvb8x %u,r%u,r%u stxvb16x %u,r%u,r%u dis_vx_store(ppc)(opc2) oaddic r%u,r%u,%d addic. r%u,r%u,%d li r%u,%d addi r%u,r%u,%d lis r%u,%d addis r%u,r%u,0x%x mulli r%u,r%u,%d subfic r%u,r%u,%d add%s%s r%u,r%u,r%u addc%s%s r%u,r%u,r%u adde%s%s r%u,r%u,r%u addex r%u,r%u,r%u,%d addex instruction addme%s%s r%u,r%u,r%u addze%s%s r%u,r%u,r%u divw%s%s r%u,r%u,r%u divwu%s%s r%u,r%u,r%u mulhw%s r%u,r%u,r%u mulhwu%s r%u,r%u,r%u mullw%s%s r%u,r%u,r%u neg%s%s r%u,r%u subf%s%s r%u,r%u,r%u subfc%s%s r%u,r%u,r%u subfe%s%s r%u,r%u,r%u subfme%s%s r%u,r%u subfze%s%s r%u,r%u mulhd%s r%u,r%u,r%u mulhdu%s r%u,r%u,r%u mulld%s%s r%u,r%u,r%u divd%s%s r%u,r%u,r%u divdu%s%s r%u,r%u,r%u divweu%s%s r%u,r%u,r%u divwe%s%s r%u,r%u,r%u divde%s%s r%u,r%u,r%u divdeu%s%s r%u,r%u,r%u dis_int_arith(ppc)(opc2) dis_int_arith(ppc)(opc1) dis_vx_load(ppc)(instr) lxsiwzx %d,r%u,r%u lxsiwax %d,r%u,r%u lxvx %u,r%u,r%u lxvl %u,r%u,r%u lxvll %u,r%u,r%u lxvwsx %u,r%u,r%u lxsspx %d,r%u,r%u lxsdx %d,r%u,r%u lxsibzx %u,r%u,r%u lxsihzx %u,r%u,r%u lxvd2x %d,r%u,r%u lxvdsx %d,r%u,r%u lxvw4x %u,r%u,r%u lxvh8x %u,r%u,r%u lxvb16x %u,r%u,r%u dis_vx_load(ppc)(opc2) dis_av_bcd(ppc)(instr) bcdadd. v%d,v%d,v%d,%u bcdsub. v%d,v%d,v%d,%u bcds. v%d,v%d,v%d,%d bcdsr. v%d,v%d,v%d,%d bcdus. v%d,v%d,v%d,%d increment_BCDstring32_helperbcdctsq v%d, v%d bcdcfsq v%d, v%d, %d bcdctz. v%d,v%d,%d convert_to_zoned_helperbcdctn. v%d,v%d convert_to_national_helperbcdcfz. v%d,v%d,%d convert_from_zoned_helperbcdcfn. v%d,v%d,%d convert_from_national_helperbcdsetsgn. v%d,v%d,%d dis_av_bcd(ppc)(opc2) xsaddqp v%d,v%d,v%d xsaddqpo v%d,v%d,v%d xsmulqp v%d,v%d,v%d xsmulqpo v%d,v%d,v%d xsmaddqp v%d,v%d,v%d xsmaddqpo v%d,v%d,v%d xsmsubqp v%d,v%d,v%d xsmsubqpo v%d,v%d,v%d xsnmaddqp v%d,v%d,v%d xsnmaddqpo v%d,v%d,v%d xsnmsubqp v%d,v%d,v%d xsnmsubqpo v%d,v%d,v%d xssubqp v%d,v%d,v%d xssubqpo v%d,v%d,v%d xsdivqp v%d,v%d,v%d xsdivqpo v%d,v%d,v%d xssqrtqp v%d,v%d xssqrtqpo v%d,v%d xscvqpuwz v%d,v%d xscvudqp v%d,v%d xscvqpswz v%d,v%d xscvsdqp v%d,v%d xscvqpudz v%d,v%d xscvqpdp v%d,v%d xscvqpdpo v%d,v%d xscvdpqp v%d,v%d xscvqpsdz v%d,v%d lwdis_memsync(ppc)(0x13,opc2) isync eieio mbar %u lwarx r%u,r%u,r%u,EH=%u lbarx r%u,r%u,r%u,EH=%u lharx r%u,r%u,r%u,EH=%u dis_memsync(ppc)(stwcx.,b0) stwcx. r%u,r%u,r%u dis_memsync(ppc)(stbcx.,b0) stbcx. r%u,r%u,r%u sthcx. r%u,r%u,r%u %ssync ldarx r%u,r%u,r%u,EH=%u dis_memsync(ppc)(stdcx.,b0) stdcx. r%u,r%u,r%u lqarx r%u,r%u,r%u,EH=%u dis_memsync(ppc)(stqcx.,b0) stqcx. r%u,r%u,r%u dis_memsync(ppc)(opc2) dis_memsync(ppc)(opc1) vaddcuw v%d,v%d,v%d vaddubm v%d,v%d,v%d vadduhm v%d,v%d,v%d vadduwm v%d,v%d,v%d vaddudm v%d,v%d,v%d vaddubs v%d,v%d,v%d vadduhs v%d,v%d,v%d vadduws v%d,v%d,v%d vaddsbs v%d,v%d,v%d vaddshs v%d,v%d,v%d vaddsws v%d,v%d,v%d vsubcuw v%d,v%d,v%d vsububm v%d,v%d,v%d vsubuhm v%d,v%d,v%d vsubuwm v%d,v%d,v%d vsubudm v%d,v%d,v%d vsububs v%d,v%d,v%d vsubuhs v%d,v%d,v%d vsubuws v%d,v%d,v%d vsubsbs v%d,v%d,v%d vsubshs v%d,v%d,v%d vsubsws v%d,v%d,v%d vmaxub v%d,v%d,v%d vmaxuh v%d,v%d,v%d vmaxuw v%d,v%d,v%d vmaxud v%d,v%d,v%d vmaxsb v%d,v%d,v%d vmaxsh v%d,v%d,v%d vmaxsw v%d,v%d,v%d vmaxsd v%d,v%d,v%d vminub v%d,v%d,v%d vminuh v%d,v%d,v%d vminuw v%d,v%d,v%d vminud v%d,v%d,v%d vminsb v%d,v%d,v%d vminsh v%d,v%d,v%d vminsw v%d,v%d,v%d vminsd v%d,v%d,v%d vavgub v%d,v%d,v%d vavguh v%d,v%d,v%d vavguw v%d,v%d,v%d vavgsb v%d,v%d,v%d vavgsh v%d,v%d,v%d vavgsw v%d,v%d,v%d vmuloub v%d,v%d,v%d vmulouh v%d,v%d,v%d vmulouw v%d,v%d,v%d vmuluwm v%d,v%d,v%d vmulosb v%d,v%d,v%d vmulosh v%d,v%d,v%d vmulosw v%d,v%d,v%d vmuleub v%d,v%d,v%d vmuleuh v%d,v%d,v%d vmuleuw v%d,v%d,v%d vmulesb v%d,v%d,v%d vmulesh v%d,v%d,v%d vmulesw v%d,v%d,v%d vsum4ubs v%d,v%d,v%d vsum4sbs v%d,v%d,v%d vsum4shs v%d,v%d,v%d vsum2sws v%d,v%d,v%d vsumsws v%d,v%d,v%d dis_av_arith(ppc)(opc2=0x%x) Unrecognized opcode %x sudis_vx_conv(ppc)(instr) dis_vx_conv(ppc)(opc2) xscvdpsxds v%u,v%u xscvdpsxws v%u,v%u xscvdpuxds v%u,v%u xscvsxdsp v%u,v%u xscvsxddp v%u,v%u xscvuxdsp v%u,v%u xscvuxddp v%u,v%u xvcvdpsxws v%u,v%u xvcvdpuxws v%u,v%uxvcvsp%sxws v%u,v%u xscvdpsp v%u,v%u xscvdpspn v%u,v%u xscvdpuxws v%u,v%u xscvspdp v%u,v%u xscvspdpn v%u,v%u xvcvdpsp v%u,v%u xvcvdpuxds v%u,v%u xvcvspdp v%u,v%u xvcvspsxds v%u,v%u xvcvspuxds v%u,v%u xvcvdpsxds v%u,v%u xvcvsxddp v%u,v%u xvcvuxddp v%u,v%u xvcvsxdsp v%u,v%u xvcvuxdsp v%u,v%u xvcvsxwdp v%u,v%u xvcvuxwdp v%u,v%u xvcvsxwsp v%u,v%u xvcvuxwsp v%u,v%u xscmpeqdp v%d,v%d,v%d xscmpgtdp v%d,v%d,v%d xsmaxcdp v%d,v%d,v%d xsmincdp v%d,v%d,v%d dis_vx_misc(ppc)(opc2) xvredpxvrsqrtedpxvrespxvrsqrtespxvmaxspxvminspxvmaxdpxvmindpnpmdis_vxv_misc(ppc)(instr) %s v%d,v%d %s v%d,v%d v%d xvcpsgndp v%d,v%d,v%d xvcpsgnsp v%d,v%d v%d xv%sabsdp v%d,v%d xvnegsp v%d,v%d xvnegdp v%d,v%d xvrdpi%s v%d,v%d xvrspi%s v%d,v%d xvrspic v%d,v%d dis_vxv_misc(ppc)(opc2) xsmindpxsmaxdpxsrespxsrsqrtespxsrsqrtedpxsredpdis_vxs_misc(ppc)(instr) xxspltib v%u,%u xscmpexpdp %u,v%u,v%u xxextractuw v%u,v%u,%u xxinsertw v%u,v%u,%u xsabsdp v%u,v%u xsxexpd %u,v%u xsxsigdp v%u,v%u xscvhpdp v%u, v%u xscvdphp v%u, v%u inst_select = %u xststdcsp %u,v%u,%u xststdcdp %u,v%u,%u xscpsgndp v%d,v%d v%d xsnabsdp v%d,v%d xsrdpi%s v%d,v%d xsrsp v%d, v%d xvtstdcsp v%u,v%u,%u xviexpsp v%d,v%d xsiexpdp v%u,%u,%u xvxexpdp v%d,v%d xvxsigdp v%d,v%d xxbrh v%u, v%u xvxexpsp v%d,v%d xvxsigsp v%d,v%d xxbrw v%u, v%u xxbrd v%u, v%u xvcvhpsp v%d,v%d xvcvsphp v%d,v%d xxbrq v%u, v%u xvtstdcdp v%u,v%u,%u xviexpdp v%d,v%d dis_vxs_misc(ppc)(opc2) dis_vxs_arith(ppc)(instr) xsaddsp v%d,v%d,v%d xssubsp v%d,v%d,v%d xsadddp v%d,v%d,v%d xsdivsp v%d,v%d,v%d xsdivdp v%d,v%d,v%d xsmadd%ssp v%d,v%d,v%d xsmadd%sdp v%d,v%d,v%d xsmsub%ssp v%d,v%d,v%d xsmsub%sdp v%d,v%d,v%d xsnmadd%sdp v%d,v%d,v%d xsnmadd%ssp v%d,v%d,v%d xsnmsub%ssp v%d,v%d,v%d xsnmsub%sdp v%d,v%d,v%d xsmulsp v%d,v%d,v%d xsmuldp v%d,v%d,v%d xssubdp v%d,v%d,v%d xssqrtsp v%d,v%d xssqrtdp v%d,v%d xstdivdp crf%d,v%d,v%d xstsqrtdp v%d,v%d dis_vxs_arith(ppc)(opc2) dis_fp_tests(ppc)(ftdiv) ftdiv crf%d,fr%u,fr%u dis_fp_tests(ppc)(ftsqrt) ftsqrt crf%d,fr%u dis_fp_tests(ppc)(opc2) addsubmuldivmdpadpdis_vxv_dp_arith(ppc)(instr) xv%sdp v%d,v%d,v%d xvsqrtdp v%d,v%d xv%sm%s%s v%d,v%d,v%d xvtsqrtdp cr%d,v%d xvtdivdp cr%d,v%d,v%d dis_vxv_dp_arith(ppc)(opc2) maddmspaspdis_vxv_sp_arith(ppc)(instr) xvaddsp v%d,v%d,v%d xvmulsp v%d,v%d,v%d xvsubsp v%d,v%d,v%d xvdivsp v%d,v%d,v%d xvsqrtsp v%d,v%d xvtsqrtsp cr%d,v%d xvtdivsp cr%d,v%d,v%d dis_vxv_sp_arith(ppc)(opc2) xscpsgnqp v%d,v%d,v%d xscmpoqp %u,v%d,v%u xscmpuqp %u,v%d,v%u xscmpexpqp %u,v%d,v%u xststdcqp %u,v%d,%u xsabsqp v%d,v%d xsxexpqp v%d,v%d xsnabsqp v%d,v%d xsnegqp v%d,v%d xsxsigqp v%d,v%d xsiexpqp v%d,v%d,v%d t(hwcaps_guest & mask32) == 0(hwcaps_guest & mask64) == 0 0x%llx: r3 = client_request ( %%r4 ) r3 = guest_NRADDR r3 = guest_NRADDR_GPR2 IR injection lmw r%u,%d(r%u) stmw r%u,%d(r%u) dis_syslink(ppc)(theInstr) sc ERROR: get_VSX60_opc2() xscmp%sdp crf%d,fr%u,fr%u dis_vx_cmp(ppc)(opc2) addpcis %u,%llu dis_cond_logic(ppc)(opc1) mcrf cr%u,cr%u crand crb%d,crb%d,crb%d crandc crb%d,crb%d,crb%d creqv crb%d,crb%d,crb%d crnand crb%d,crb%d,crb%d crnor crb%d,crb%d,crb%d cror crb%d,crb%d,crb%d crorc crb%d,crb%d,crb%d crxor crb%d,crb%d,crb%d dis_cond_logic(ppc)(opc2) wait %d tbegin. %u tend. %u tsr. %u tcheck. %u tabortwc. %u,%u,%u tabortdc. %u,%u,%u tabortwci. %u,%u,%u tabortdci. %u,%u,%u tabort. %u treclaim. %u trechkpt. dis_int_ldst_str(ppc)(opc1) lswi r%u,r%u,%d lswx r%u,r%u,r%u stswi r%u,r%u,%d stswx r%u,r%u,r%u dis_int_ldst_str(ppc)(opc2) dcbf r%u,r%u dcbst r%u,r%u dcbt r%u,r%u dcbtst r%u,r%u dcbzl r%u,r%u dcbz r%u,r%u icbi r%u,r%u dis_cache_manage(ppc)(opc2) dst%s r%u,r%u,%d dstst%s r%u,r%u,%d dss %d dssall dis_av_datastream(ppc)(opc2) isel r%u,r%u,r%u,crb%u maddhd r%u,r%u,r%u,r%u maddhdu r%u,r%u,r%u,r%u maddld r%u,r%u,r%u,r%u vshasigmaw v%d,v%d,%u,%u vshasigmad v%d,v%d,%u,%u dis_av_hash(ppc)(opc2) !allow_VX0 dres.len == 20xsaddspxsmaddaspxsmaddmspxscmpeqdpxssubspxscmpgtdpxxpermrxsmulspxsmsubaspxxmrghwxscmpgedpxsdivspxsmsubmspxxpermxsadddpxsmaddadpxscmpudpxssubdpxsmaddmdpxscmpodpxsmuldpxsmsubadpxxmrglwxstsqrtdpxsdivdpxsmsubmdpxscmpexpdpxstdivdpxvaddspxvmaddaspxvcmpeqspxvcvspuxwsxvsubspxvmaddmspxvcvspsxwsxvmulspxvmsubaspxvcmpgespxvdivspxvmsubmspxvtdivspxvadddpxvmaddadpxvcmpeqdpxvsubdpxvmaddmdpxvcmpgtdpxvmuldpxvmsubadpxvcmpgedpxvdivdpxvmsubmdpxvtdivdpxsmaxcdpxsnmaddaspxxlandxsmincdpxsnmaddmspxxlandcxsnmsubaspxxlorxsnmsubmspxxlxorxsnmaddadpxxlnorxsnmaddmdpxxlorcxscpsgndpxsnmsubadpxxlnandxsnmsubmdpxxleqvxvnmaddaspxvnmaddmspxvcpsgnspxvnmsubaspxviexpspxvnmsubmspxvnmaddadpxvnmaddmdpxvcpsgndpxvnmsubadpxviexpdpxvnmsubmdpxvcvsxddpxssqrtspxxselxscvdpuxwsxsrdpixssqrtdpxscvdpsxwsxsrdpizxsrdpipxsrdpicxsrdpimxvrspixvsqrtspxvrspizxxspltwxxextractuwxvcvuxwspxvrspipxvtsqrtspxvrspicxxinsertwxvcvsxwspxvrspimxvcvdpuxwsxvrdpixvsqrtdpxvcvdpsxwsxvrdpizxvcvuxwdpxvrdpipxvtsqrtdpxvrdpicxvcvsxwdpxvrdpimxscvdpspxscvdpspnxxrspxscvuxdspxststdcspxscvsxdspxscvdpuxdsxscvspdpxscvspdpnxscvdpsxdsxsabsdpxsxexpdp_xsxigdpxscvuxddpxsnabsdpxststdcdpxscvsxddpxsnegdpxvcvspuxdsxvcvdpspxvcvspsxdsxvabsspxvcvuxdspxvnabsspxvcvsxdspxvnegspxvcvdpuxdsxvcvspdpxvcvdpsxdsxvabsdpxvcvuxddpxvnabsdpxvnegdpop8 == Iop_Add8 || op8 == Iop_Sub8 || op8 == Iop_Mul8 || op8 == Iop_Or8 || op8 == Iop_And8 || op8 == Iop_Xor8 || op8 == Iop_Shl8 || op8 == Iop_Shr8 || op8 == Iop_Sar8 || op8 == Iop_CmpEQ8 || op8 == Iop_CmpNE8 || op8 == Iop_Not8typeOfIRExpr(irsb->tyenv,rot_amt) == Ity_I8typeOfIRExpr(irsb->tyenv, arg1) == Ity_I1typeOfIRExpr(irsb->tyenv, arg2) == Ity_I1typeOfIRExpr( irsb->tyenv, e ) == Ity_I32align == 2 || align == 4 || align == 8 || align == 16typeOfIRTemp(irsb->tyenv, addr) == Ity_I64typeOfIRTemp(irsb->tyenv, addr) == Ity_I32typeOfIRTemp(irsb->tyenv, t) == Ity_I32typeOfIRExpr(irsb->tyenv, src) == Ity_I64typeOfIRExpr(irsb->tyenv, e) == Ity_I8typeOfIRExpr(irsb->tyenv, e) == Ity_V128tyA == Ity_I32 || tyA == Ity_I64typeOfIRExpr(irsb->tyenv,res) == Ity_I32typeOfIRExpr(irsb->tyenv,argL) == Ity_I32typeOfIRExpr(irsb->tyenv,argR) == Ity_I32typeOfIRExpr(irsb->tyenv,oldca) == Ity_I32typeOfIRExpr(irsb->tyenv,res) == Ity_I64typeOfIRExpr(irsb->tyenv,argL) == Ity_I64typeOfIRExpr(irsb->tyenv,argR) == Ity_I64typeOfIRExpr(irsb->tyenv,oldca) == Ity_I64shift == 0 || shift == 8 || shift == 16 || shift == 24typeOfIRExpr(irsb->tyenv, t64) == Ity_I64typeOfIRExpr(irsb->tyenv, t3) == Ity_I64typeOfIRExpr(irsb->tyenv, t2) == Ity_I64typeOfIRExpr(irsb->tyenv, t1) == Ity_I64typeOfIRExpr(irsb->tyenv, t0) == Ity_I64typeOfIRExpr(irsb->tyenv, e) == Ity_D128typeOfIRExpr(irsb->tyenv,addr) == tytypeOfIRExpr(irsb->tyenv, vIn) == Ity_V128vEvn && *vEvn == IRTemp_INVALIDvOdd && *vOdd == IRTemp_INVALIDtypeOfIRExpr(irsb->tyenv,result) == Ity_I32 || typeOfIRExpr(irsb->tyenv,result) == Ity_I64typeOfIRTemp(irsb->tyenv, nia) == Ity_I64typeOfIRTemp(irsb->tyenv, nia) == Ity_I32typeOfIRExpr(irsb->tyenv, t128) == Ity_V128typeOfIRExpr(irsb->tyenv, e) == Ity_F64typeOfIRExpr(irsb->tyenv, e) == Ity_D64dis_dfp_extract_insert(ppc)(opc2) dis_dfp_extract_insertq(ppc)(opc2) ( size == Ity_I16 ) || ( size == Ity_I32 ) || ( size == Ity_I64 ) || ( size == Ity_F128 )( typeOfIRExpr(irsb->tyenv, mkexpr( src ) ) == Ity_I32 ) || ( typeOfIRExpr(irsb->tyenv, mkexpr( src ) ) == Ity_I64 ) || ( typeOfIRExpr(irsb->tyenv, mkexpr( src ) ) == Ity_F128 )typeOfIRExpr(irsb->tyenv, e) == Ity_I32dis_vx_Scalar_Round_to_quad_integer(ppc)(instr) dis_vx_Scalar_Round_to_quad_integer(ppc)(opc2) typeOfIRExpr(irsb->tyenv, e) == Ity_F128typeOfIRExpr(irsb->tyenv, e) == tydis_av_extract_element(ppc)(instr) dis_av_extract_element(ppc)(opc2) typeOfIRExpr(irsb->tyenv,result) == Ity_V128dis_dfp_quantize_sig_rrnd(ppc)(opc2) dis_dfp_quantize_sig_rrndq(ppc)(opc2) typeOfIRExpr(irsb->tyenv, argL0) == Ity_I32typeOfIRExpr(irsb->tyenv, argR0) == Ity_I32typeOfIRExpr(irsb->tyenv, argL0) == Ity_I64typeOfIRExpr(irsb->tyenv, argR0) == Ity_I64typeOfIRExpr(irsb->tyenv, e) == Ity_D32dis_av_polymultarith(ppc)(instr) dis_av_polymultarith(ppc)(opc2=0x%x) dis_av_fp_convert(ppc)(instr) dis_av_fp_convert(ppc)(UIMM_5) dis_av_logic(ppc)(opc1 != 0x4) dis_av_fp_arith(ppc)(vA_addr) dis_av_fp_arith(ppc)(opc2=0x%x) dis_int_ldst_rev(ppc)(opc1|b0) dis_int_parity(ppc)(0x1F,opc1:rB|b0) ERROR: dis_dfp_bcd(ppc), undefined opc2 case fnmsubs%s fr%u,fr%u,fr%u,fr%u fnmadds%s fr%u,fr%u,fr%u,fr%u dis_fp_multadd(ppc)(3B: opc2) dis_fp_multadd(ppc)(3F: opc2) ERROR: dis_dfp_bcdq(ppc), undefined opc2 case dis_fp_arith(ppc)(instr,fmul) ( ty_src == Ity_I64 ) || ( ty_src == Ity_I32 )dis_av_procctl(ppc)(opc2,dst) typeOfIRExpr( irsb->tyenv,src ) == Ity_I64typeOfIRExpr(irsb->tyenv,src ) == Ity_I32dis_dfp_significant_digits(ppc)(opc2) wrong dis_dfp_class_test(ppc)(opc2) dis_dfp_exponent_test(ppc)(opc2) dis_vx_permute_misc(ppc)(instr) dis_vx_permute_misc(ppc)(opc2) dis_av_count_bitTranspose(ppc)(instr) dis_av_count_bitTranspose(ppc)(opc2) dis_int_load(ppc)(lbzu,rA_addr|rD_addr) dis_int_load(ppc)(lhau,rA_addr|rD_addr) dis_int_load(ppc)(lhzu,rA_addr|rD_addr) dis_int_load(ppc)(lwzu,rA_addr|rD_addr) dis_int_load(ppc)(lwzux,rA_addr|rD_addr) dis_int_load(ppc)(lhaux,rA_addr|rD_addr) dis_int_load(ppc)(lhzux,rA_addr|rD_addr) dis_int_load(ppc)(ldux,rA_addr|rD_addr) dis_int_load(ppc)(lwaux,rA_addr|rD_addr) dis_int_load(ppc)(ldu,rA_addr|rD_addr) dis_int_load(ppc)(0x3A, opc2) dis_fp_scr(ppc)(instr,mtfsb1) dis_fp_scr(ppc)(instr,mtfsb0) dis_fp_scr(ppc)(instr,mtfsfi) dis_fp_scr(ppc)(mff**) Unrecognized instruction. dis_int_store(ppc)(stbu,rA_addr) dis_int_store(ppc)(sthu,rA_addr) dis_int_store(ppc)(stwu,rA_addr) dis_int_store(ppc)(stbux,rA_addr) dis_int_store(ppc)(sthux,rA_addr) dis_int_store(ppc)(stwux,rA_addr) dis_int_store(ppc)(stdux,rA_addr) dis_av_extend_sign(ppc)(instr) vctzb instruction not supported on non ISA 3.0 platform vctzh instruction not supported on non ISA 3.0 platform vctzw instruction not supported on non ISA 3.0 platform vctzd instruction not supported on non ISA 3.0 platform dis_av_extend_sign(ppc)(Unsupported vector extend sign instruction) bcl 0x%x, 0x%x (a.k.a mr lr,cia+4) dres->jk_StopHere == Ijk_INVALIDdis_int_branch(ppc)(0x13,b11to15)(%d) dis_int_branch(ppc)(bcctr,BO) dis_int_logic(ppc)(cntlzw,rB_addr) dis_int_logic(ppc)(extsb,rB_addr) dis_int_logic(ppc)(extsh,rB_addr) dis_int_logic(ppc)(extsw,rB_addr) dis_int_logic(ppc)(cntlzd,rB_addr) dis_proc_ctl(ppc)(mcrxr,b21to22|b11to20) dis_proc_ctl(ppc)(mfspr,SPR)(0x%x) dis_proc_ctl(ppc)(mtspr,SPR)(%u) dis_fp_pair(ppc) ldpx or stdpx: odd frT register dis_fp_pair(ppc) : X-form wrong opc2 dis_fp_pair(ppc) lfdp : odd frT register dis_fp_pair(ppc) : DS-form wrong opc2 dis_fp_pair(ppc) stfdp : odd frT register dis_fp_pair vector load/store (ppc) : DS-form wrong opc2 addex instruction, CY = %d is reserved. dis_int_arith(ppc)(addme,rB_addr) dis_int_arith(ppc)(addze,rB_addr) dis_int_arith(ppc)(mulhw,flag_OE) dis_int_arith(ppc)(mulhwu,flag_OE) dis_int_arith(ppc)(neg,rB_addr) dis_int_arith(ppc)(subfme,rB_addr) dis_int_arith(ppc)(subfze,rB_addr) dis_int_arith(ppc)(mulhd,flagOE) dis_int_arith(ppc)(mulhdu,flagOE) dis_av_bcd(ppc)(invalid inst_select) Erorr, dis_vx_Floating_Point_Arithmetic_quad_precision(ppc)(instr) dis_vx_Floating_Point_Arithmetic_quad_precision(0x324 unknown inst_select) dis_vx_Floating_Point_Arithmetic_quad_precision invalid inst_select (ppc)(opc2) dis_vx_Floating_Point_Arithmetic_quad_precision(ppc)(opc2) dis_memsync(ppc)(0x13,b11to25|b0) dis_memsync(ppc)(eieio,b11to20|b0) dis_memsync(ppc)(mbar,b11to20|b0) dis_memsync(ppc)(sync/lwsync,b11to20|b0) dis_memsync(ppc)(sync/lwsync,flag_L) dis_av_arith(ppc)(opc1 != 0x4) ( size == Ity_I16 ) || ( size == Ity_I32 ) || ( size == Ity_I64 ) || ( size == Ity_V128 )_do_vsx_fp_roundToInt(ppc)(opc2)typeOfIRExpr(irsb->tyenv, src ) == Ity_I32_get_vsx_rdpi_suffix(ppc)(opc2)dis_vxv_misc(ppc)(vrspi)(opc2) dis_vxv_scalar_extract_exp_sig invalid inst_select (ppc)(opc2) dis_vxs_misc(ppc) Invalid instruction selection The impossible happened: dis_vxv_dp_arith(ppc)The impossible happened: dis_vxv_sp_arith(ppc)dis_vx_scalar_quad_precision(ppc)(instr) dis_vx_scalar_quad_precision invalid inst_select (ppc)(opc2) dis_vx_scalar_quad_precision(ppc)(opc2) guest_arch == VexArchPPC32 || guest_arch == VexArchPPC64disInstr(ppc): Little Endian 32-bit mode is not supported disInstr(ppc): old ppc32 instruction magic detected. Code might clobber r0. disInstr(ppc): source needs to be recompiled against latest valgrind.h. branch-and-link-to-noredir r12 branch-and-link-to-noredir r11 dis_int_ldst_mult(ppc)(lmw,rA_addr) Error: undefined opcode 0x %x, the instruction = 0x %x dis_cond_logic(ppc)(crbD|crbA|crbB != 0) typeOfIRExpr(irsb->tyenv,bit) == Ity_I32dis_transactional_memory(ppc): unrecognized instruction dis_cache_manage(ppc)(dcbzl not supported by host) dis_cache_manage(ppc)(opc1|b0) lineszB == 16 || lineszB == 32 || lineszB == 64 || lineszB == 128dis_av_datastream(ppc)(instr) dis_av_datastream(ppc)(opc2,dst) dis_int_mult(ppc): unrecognized instruction disInstr(ppc): found the Floating Point instruction 0x%x that can't be handled by Valgrind on this host. This instruction requires a host that supports Floating Point instructions. disInstr(ppc): found an AltiVec or an e500 instruction 0x%x that can't be handled by Valgrind. If this instruction is an Altivec instruction, Valgrind must be run on a host that supportsAltiVec instructions. If the application was compiled for e500, then unfortunately Valgrind does not yet support e500 instructions. disInstr(ppc): found the instruction 0x%x that is defined in the Power ISA 2.06 ABI but can't be handled by Valgrind on this host. This instruction requires a host that supports the ISA 2.06 ABI. disInstr(ppc): found the General Purpose-Optional instruction 0x%x that can't be handled by Valgrind on this host. This instruction requires a host that supports the General Purpose-Optional instructions. disInstr(ppc): found the Graphics-Optional instruction 0x%x that can't be handled by Valgrind on this host. This instruction requires a host that supports the Graphic-Optional instructions. disInstr(ppc): found the decimal floating point (DFP) instruction 0x%x that can't be handled by Valgrind on this host. This instruction requires a host that supports DFP instructions. disInstr(ppc): found the Power 8 instruction 0x%x that can't be handled by Valgrind on this host. This instruction requires a host that supports Power 8 instructions. disInstr(ppc): found the Power 9 instruction 0x%x that can't be handled by Valgrind on this host. This instruction requires a host that supports Power 9 instructions. disInstr(ppc): unhandled instruction: 0x%x primary %d(0x%x), secondary %u(0x%x) xxbr[h|w|d|q]|xvxexpdp|xvxexpsp|xvxsigdp|xvxsigsp|xvcvhpsp|xvcvsphp|xscvdphp|xscvhpdpputXER_BCputXER_CA32putGSTgen_vpopcntd_mode32expand16Sx8mkQNarrow64Sto32mkV128from4x64SbreakV128to4x64SmkQNarrow64Uto32mkV128from4x64Uexpand8Ux16expand8Sx16expand16Ux8gen_POPCOUNTdis_int_logicputIRegintegerGuestRegOffsetgetIRegputVRegdis_cache_managegenerate_stsw_sequencegenerate_lsw_sequencegen_byterev32gen_byterev16gen_SIGBUS_if_misalignedputXER_SOset_XER_OV_64set_XER_OV_OV32_32set_XER_CA_64putXER_CAset_XER_CA_32mk64lo32Uto64mk64lo32Sto64putXER_OV32putXER_OVmake_redzone_AbiHintaddr_aligndis_branchputCRbitputDReg_pairputF128RegputFReggetFRegbreakV128to4x64Uset_AV_CR6handle_SNaN_to_QNaN_32breakV128to4x32breakV128to4xF64mkNOT1mkOR1putFPCCputGST_maskedputGST_fieldputCgenerate_store_FPRFmkAND1putVSRegvsxGuestRegOffsetputDReg32putDRegfloatGuestRegOffsetgetDRegdo_trapgetCR321getCR0storemkSzOpputCR0putCR321set_CR0ROTLdisInstr_PPC_WRKdisInstr_PPCnewTempsetup_value_check_argsUU U U V$U, V:V@VD'VH1VL9V`CVdKVhUV\VdVnVwVVVVVVVVVVVVVV VV"H W$ W0W@ WD(WL2W`Av  KAGF F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F J F A FD,X@ xAb E G  KAGE H K H K H K H K H K H K H K H K H K H K H K H K H K H K H K H K H K H I H I H I H I H I H I H I H I H I H I H I H I H I H\ _AA CCLHFARBFAMFF A$E(G,H0F4A8EkAA AANhA FCMF H$LZA J$A(E,F0A4A8HAF FAC AA AAE A A HAIK A$F(LZA J$A(E,K G K A$G(N G K A$G(F GK A$G(>@moAA ACN8IAC FIY$^(F$S(B,J0J$S(B,U0A4F8A U ,@ xR _U X p 6= U Vg@T T p@L`4DS Mp[4S t` ~!!OU ":@"D"oT #gS p#/U  8$/?U X% a%jU  &A &U `'S  'S  (S   )O+S DS ]p+g`S  ,]`,?lU  -?xU ./R P2o\U +2?Q X3{c 4n4~56OHR  8_\R 9e9_0T  P;/(<O==L?W T  p@~AR @C_$R DPF0GHIpL_)N8PDlR  ]RixR  TR  VR  XU PZ_*e*fFkbS {@morT uO4R  yO\T p| LT & `7 T P _ >m @U n p @ ЕO ^  p? j R  % 0-= `Q T j T @+ @T  p: R 8 S  ' 12 pT  K PX R q ] P @ dU 0 R  n @  & 4U  ? 8K PZY n 0 Tv   P( O O % |S & . $S ) 5_7 lS P @;c 0<p D  Q! ` v P} 0  TT ХG B p'<   %4@ M}\0 cQ  |Q Q  '*-o/T 4oT  +5:=GBWFrrZ} ^MpvP pO  @ `L!c. !? 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X d q+   Ε ݕ     % + 4 : G R e q x          ʖ Ֆ ޖ      ) 3 8 > G M [ g v        ȗ ԗ          @ G L c i r x        Ә ٘       ( 1 : E Q Z ` n }       ș љ י       " 2 > fE hK R ee z  f     ͚ ޚ     # 4 @ I O Z e q {         ś ʛ Л ܛ       ' 1 8 = D M Y d p y         Ü ʜ М ۜ       ) 5 A G R ] i x         Ý Ν ۝         & 0 7 < E P Z a f l z          ̞ ֞          " ) . 5 ; J U a i t      ˟ ֟       " * 5 ; I X c s      Q  Р f֠      , : A fM hS k ץ ݥ       / 7 A R Z b w     ¦ ˦      + 6 = B Y j q f} u  g + ݧ      "+ B I N W _ +    ƨ Ѩ ٨  + * 1 6 ? J R + Ω թ ک     C+ j+ + ª hӪ  i  j " k3 B lS b mh z+  n  o ū pԫ ߫ q  r  $ * 7 A P [ m    f h ¬ ɬ fլ ۬    ~      ˱ ױ 6 @ G L c p w | + Բ ߲    s .+ E P \ e l   f y + ͳ س   +  % 0 < E L h o t   f u  t Ӵ u  v  w 2+ I T ` k z+    x ʵ+   +   2 y; R z[ j {s  |    Ͷ  O Z  ,   Ƹ ߸      ( . ; G V _ e n t }     ƹ Ϲ        & ? J P c s        к ۺ       ' < G W g v        һ ޻       % 3 ? H N W ` f       ̼ ؼ        ( ? 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" ͪ #ܪ  $  % $ &3 A 'P ^ (m { )  *  +ī ҫ ,  -  . ) /8 F 0U c 1r  2  3  4ɬ ׬ 5  6  7  . 8= K 9Z h :w  ; +   ͭ <ԭ +   + # + B+ R X c o x ~   +  î ڮ+   +  # :+ K S j+ {  +   ʯ+ ۯ  +   *+ ; C U+ f n +    = İ >Ӱ  ?  @   A' 5 BD R Ca o D~  E  F Ʊ Gձ  H  I  J, : KI W Lf t M  N  O ˲ Pڲ  Q  R " S1 ? TN \ Uk y V  W  X³ г Y߳  Z  [ = C     ȴ Դ      ' 9 ? H O T c i q x }        ĵ ˵ е   f u    ) 6 B N _ k x       ¶ Ѷ ׶ ߶     f \ & 5 A M ^ j v      ͷ ӷ ܷ          * 1 6 = C O Y ^ v      Ƹ ׸       # , 3 8 E K S Z _ y     ڹ     * 7 H T a r ~    ٺ ߺ        " ) 0 5 ; G M Y b k q        » ͻ ٻ       ( 9 ? K Y e s         ¼ μ ڼ      ( 1 = H R Z   f u ٽ ]  ^     % 1 B N \ m y       ƾ ־       ! 1 A L Y ` e l r {      ȿ ο ؿ       " ) f5 u; G M Z i u               ' , 3 < W a q                 " ' : A fM uS g m z              ! ' 3 9 F V b                 f u " ) f5 _; L R      % @ K V ` g l ~      7+ J ] p {                ! , 8 D v `|  V e q       &+ A p `v  " . G R Y c h            0 ; J T Y  a          + ' b2 B I fU u[ +             M+ \ o z  +      %+ 7 G R ] h {    +  ! ) < O ~+            /+ A L _ j x    O+ {                    ! , 6 @ E K V ` g l u              ( . F S [ a y    +       & , 8 D f u        +      ! - [+ v              ( 4 D U a o              , 8 F W c                $ ) D O Y ` e ~                % 2 E R b l v {             , 9 D T f p w |            + B J V b j v   c +  d  e , f7 E gP i ho } i  j  k  l  m + - 8 K V d o +        ! + S+ e k s |   +      +   # , 2 > L W b k q } +    +       ' 3 K+ Z m x  +         + % + 3 < B N k+            +   # 6 A [+ n              - 8 F R n] k ov  p  q  r s  t  u ' v2 @ wN _ xm ~ y  z  {  |  }  ~* 4 F L Y i v |            " ) . = C N [ k y            % 6 B P a m {            ' 8 D R c o }       + 2 M T [ ` z                  3 N Z e o t }           +   2 9 fE uK d+ u                  + 7 J+ Z ` k v                 $ 0 < I P U ^ d n x }               & 2 > I S X a g o z              "+ 3 > J U a o z                  # 2 > R ^ r+                2 9 fE yK R ^ r ~        9 ? \ e ~       7 = Q ` l z         < C H \ h            ) 8 C [ a o             $ 0 > O [ i z               & 0 C M R Y _ m s               # . 6 G Q V _ g r z                + 6 A Z ` o u          f u   : @        & 1 ; B G Y d r y   +          R a m {                 ' 2 K ^ j t ~      $ 0 > O [ i z             ! & -+ G M Y _ w         4 C O [ l x           + ' 7 C L S j q f} y  +   C      % 0 : A F R ` k r w          + 4 C S ` s          ' 3 A Y v               $ 6 A H R W g+ |                , 8 V \ j p            * 8 I U c t           + H  w                      +  8  ?  D  M  `  k  v                    0  <  J  [  g  u                  !  2  >  L  ]  i  w             + n  t               ' 1 8 = F Q ^ e j s ~                   % 0 > E J i t               ' , D O Z h o t }             * ; G U v             ! + 5 : L W a k p w+         % 1 = N Z f w     +        # . 8 ? D V a o y                " . : C M ] i o y         f u & 1 = I V b p              * 4 ; @ F+ c i u {                " * G N S r ~    + $ M }               ( 4 : G R e q }                # 4 ? K W ] m x             ( . S e p |                 1 = G N S _ k u |                 # ( . ; I T ^ e j v               ) / ? K U \ a g r ~         &  3  D  X  ^  r  x   ]              ! ! ! ! *! 6! D! U! f! q! ]x! ~! ! ! ! ! ! ! ! ! ! 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R e q z              # * / 5 K j p        + . 9 @ E L R _ j v             ! - 8 D               ( 4 ` i t              A G S ^ j {             & 5 @ H U ` l x           ! ) 7 B N Z m          * 0 @ L X d j z               & 5 @ G L R k          # 2 g+ y                 $ 0 < J U \ a j s ~                # ( ?+ Q W e k w      +          * A+ S Y g m y  +         f y # 2 D S a l z          /        4 +       + 4           % 6 B P a m {           ) / ^ h o t           : G e k y   L+ _ o u |  - 3 N W j t   f      1 7 T    ( = H [ b g ~        + ? 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D$4ó|$鳳D$D$Owt$,t$8PVUD$t$Lt$0UPhT$RPh$PVP аD$5D$vt$,t$8PV=jPt$UPhD$t$`t$D-QL$j+t$(PD$`PL$QPD$D$D$0 D$Ugt$4t$0t$0WP|$$|$4uT$$9T$T$$9T$<$IUhL$ ‹D$,躑]X(Pt$PhPhjDVhP(P ^_$D$RPhhL$(‰4D$ -wD$4AqPht$L$$j{ +t$t$L$PT$0ȺXZ RPhhL$(‰裐D$ #- t$t$L$PT$0o]XRPhhL$(‰JD$ ʐ-D$D PPPƋ 0=xVj@P hjPƋ 0 =:V jDP D$ %ORPhhL$(‰^D$ ޏ-7 PhGAPPD$D$?dt$,t$ PWD$}D$dt$,t$ PW Ph?PPD$c5|$Lt |$ VhL$ ‹D$,]XZD$|hZx h0D$CnD$8nt$ T$RD${t$h‰ՍD$hD$ PPPL$$'$hL$‰蒍^D$D$bt$UP鴱D$bt$0t$8VRVWPt$T- Ph?PP Ph?PP'mPPY^2st$(PƋ 0 =#VjDP 銡PXlŋD$4lUPh n|PhL$ ‹D$"XZD$D$:aShY4 h0D$hjTD$hjPD$hjL hjHL$Qt$ UPPPjh,PB Pt$ P h h0D$hjTD$,hjPD$$hjL hjHL$$Qt$UPPPjh,PB Pt$P VhL$0‰h h0t$D$ jPD$ t$L$$QPh$4$PhPUP L$4޷D$,nD$_s Ph?PPjP]ZD$^PP^_UPhPVP |$( h] h0hjTD$hjPD$hjL hjHT$RL$ QWPPPjh,PB PUP hҎ h0D$hjTD$hjPD$ hjL hjHT$RL$QWPPPjh,PB Pt$P VhL$0‹D$Dχnt$D$$LkD$UL$ QPhT$RPh‰]L$0YD$(D$\saܞj|$  WPPD$ %ЈPXjjPŋD$(gƋD$,fVPh?jP Nj$fWPhVPhUPh$PhhL$$‹D$XD$ ؆t$HPh/ "UPhPWP W h‹L$D$\eWjPVhP t$X WUPl$LUhP  UPhjDWhPP $Vh‹D$8}Y^D$~D$RzRPhhL$(‰A}D$ }- Ph_>x Ph%B PhFPP= 0 && rot < 32iregNo >= 0 && iregNo <= 14r15written == Falser15guard == IRTemp_INVALIDr15kind == Ijk_Boringarmg_calculate_flags_nzcvmath_DEINTERLEAVE_2math_INTERLEAVE_2t0 && *t0 == IRTemp_INVALIDt1 && *t1 == IRTemp_INVALIDt2 && *t2 == IRTemp_INVALIDt3 && *t3 == IRTemp_INVALIDr%u, LSR #0(a.k.a. 32)r%u, LSR #%ur%u, ASR #0(a.k.a. 32)r%u, ASR #%ur%u, ROR r#%ur%ur%u, LSL #%uwrite_nzcvq || write_ger%u, LSL r%ur%u, LSR r%ur%u, ASR r%udesc[2 * si + 0] <= 2desc[2 * si + 1] <= 7math_INTERLEAVE_3math_DEINTERLEAVE_3vtb%c.8 d%u, {d%u-d%ud%u}, d%u math_DEINTERLEAVE_4u0 && u1 && u2 && u3r != rNm == nRegsnX <= 16nX > 0i < nXm == nXshift_amt < 32how < 4r%u, RRXr%u, ROR #%u[r%u, %c r%u LSL #%u][r%u, %cr%u, LSR #%u][r%u, %cr%u, ASR #%u][r%u, %cr%u, RRX][r%u, %cr%u, ROR #%u]index*shco == IRTemp_INVALID#0x%xsubaddrv%s%c.%c%d q%u, %c%u, d%u v%saddhn.i%d d%u, q%u, q%u vabal.%c%d q%u, d%u, d%u v%ssubhn.i%d d%u, q%u, q%u vabdl.%c%d q%u, d%u, d%u vml%cl.%c%d q%u, d%u, d%u vqdml%cl.s%d q%u, d%u, d%u vmull.%c%d q%u, d%u, d%u vqdmull.s%d q%u, d%u, d%u stld!condT != IRTemp_INVALIDcondT == IRTemp_INVALIDv%s%u.%d {, d%u[%u]}, [r%u], r%u %s vld%u.%d {d%u[]vrsra.%c%d %c%u, %c%u, #%u vrshr.%c%d %c%u, %c%u, #%u vsra.%c%d %c%u, %c%u, #%u vshr.%c%d %c%u, %c%u, #%u vsri.%d %c%u, %c%u, #%u vsli.%d %c%u, %c%u, #%u vshl.i%d %c%u, %c%u, #%u vqshl.u%d %c%u, %c%u, #%u vqshlu.s%d %c%u, %c%u, #%u vqshl.s%d %c%u, %c%u, #%u vshrn.i%d d%u, q%u, #%u vrshrn.i%d d%u, q%u, #%u vq%sshrn.%c%d d%u, q%u, #%u Uvq%sshrun.s%d d%u, q%u, #%u vmovl.%c%d q%u, d%u vshll.%c%d q%u, d%u, #%u sha1su1armg_dirtyhelper_SHA1SU1sha256su0armg_dirtyhelper_SHA256SU0dbhf64s32u32minmaxold_itstate != IRTemp_INVALIDnew_itstate != IRTemp_INVALIDold_itstate == IRTemp_INVALIDnew_itstate == IRTemp_INVALIDarmg_dirtyhelper_AESEarmg_dirtyhelper_AESDarmg_dirtyhelper_AESMCarmg_dirtyhelper_AESIMCaeseaesdaesmcaesimc%s.8 q%u, q%u ix >= 0 && ix < 7sha1csha1psha1msha1su0sha256hsha256h2sha256su1armg_dirtyhelper_SHA1Carmg_dirtyhelper_SHA1Parmg_dirtyhelper_SHA1Marmg_dirtyhelper_SHA1SU0armg_dirtyhelper_SHA256Harmg_dirtyhelper_SHA256H2armg_dirtyhelper_SHA256SU1%s.8 q%u, q%u, q%u armg_dirtyhelper_SHA1Hsha1harmg_dirtyhelper_VMULLP64vmull%s.p64 q%u, q%u, w%u ldabldahldastlbstlhstl%s r%u, [r%u]tt2 == 16tt2 <= 14dd == 16dd <= 14(tt) <= 14(tt2) <= 14ldrex%s%s r%u, r%u, [r%u] ldrex%s%s r%u, [r%u] strex%s%s r%u, r%u, [r%u] vsel%s.%s %c%u, %c%u, %c%u vrint%c.%s.%s %c%u, %c%u vcvt%c.%s.%s %c%u, %c%u v%snm.%s %c%u, %c%u, %c%u v%snm.f32 %c%u, %c%u, %c%u vcvt%c.%c32.f32 %c%u, %c%u vrint%c.f32.f32 %c%u, %c%u vmull.%c%d q%u, d%u, d%u[%u] vhadd.%c%d %c%u, %c%u, %c%u vqadd.%c%d %c%u %c%u, %c%u vrhadd.%c%d %c%u, %c%u, %c%u vand %c%u, %c%u, %c%u vbic %c%u, %c%u, %c%u vorr %c%u, %c%u, %c%u vmov %c%u, %c%u vorn %c%u, %c%u, %c%u veor %c%u, %c%u, %c%u vbsl %c%u, %c%u, %c%u vbit %c%u, %c%u, %c%u vbif %c%u, %c%u, %c%u vhsub.%c%d %c%u, %c%u, %c%u vqsub.%c%d %c%u, %c%u, %c%u vcgt.%c%d %c%u, %c%u, %c%u vcge.%c%d %c%u, %c%u, %c%u vshl.%c%d %c%u, %c%u, %c%u vqshl.%c%d %c%u, %c%u, %c%u vrshl.%c%d %c%u, %c%u, %c%u vqrshl.%c%d %c%u, %c%u, %c%u vmax.%c%d %c%u, %c%u, %c%u vmin.%c%d %c%u, %c%u, %c%u vabd.%c%d %c%u, %c%u, %c%u vaba.%c%d %c%u, %c%u, %c%u vadd.i%d %c%u, %c%u, %c%u vsub.i%d %c%u, %c%u, %c%u vtst.%d %c%u, %c%u, %c%u vceq.i%d %c%u, %c%u, %c%u vml%c.i%d %c%u, %c%u, %c%u vmul.%c%d %c%u, %c%u, %c%u vp%s.%c%d %c%u, %c%u, %c%u vqdmulh.s%d %c%u, %c%u, %c%u vpadd.i%d %c%u, %c%u, %c%u vadd.f32 %c%u, %c%u, %c%u vsub.f32 %c%u, %c%u, %c%u vpadd.f32 d%u, d%u, d%u vabd.f32 %c%u, %c%u, %c%u vml%c.f32 %c%u, %c%u, %c%u vmul.f32 %c%u, %c%u, %c%u vceq.f32 %c%u, %c%u, %c%u vcge.f32 %c%u, %c%u, %c%u vcgt.f32 %c%u, %c%u, %c%u vacg%c.f32 %c%u, %c%u, %c%u vmin.f32 %c%u, %c%u, %c%u vmax.f32 %c%u, %c%u, %c%u vpmin.f32 d%u, d%u, d%u vpmax.f32 d%u, d%u, d%u vrecps.f32 %c%u, %c%u, %c%u vrsqrts.f32 %c%u, %c%u, %c%u vmovvmvnvorrvbicvext.8 %c%u, %c%u, %c%u, #%u vrev64.%d %c%u, %c%u vrev32.%d %c%u, %c%u vrev16.%d %c%u, %c%u vpaddl.%c%d %c%u, %c%u vcls.s%d %c%u, %c%u vclz.i%d %c%u, %c%u vcnt.8 %c%u, %c%u vmvn %c%u, %c%u vpadal.%c%d %c%u, %c%u vqabs.s%d %c%u, %c%u vqneg.s%d %c%u, %c%u vcgt.%c%d %c%u, %c%u, #0 vcge.%c%d %c%u, %c%u, #0 vceq.%c%d %c%u, %c%u, #0 vcle.%c%d %c%u, %c%u, #0 vclt.%c%d %c%u, %c%u, #0 vabs.%c%d %c%u, %c%u vneg.%c%d %c%u, %c%u vswp %c%u, %c%u vtrn.%d %c%u, %c%u vuzp.%d %c%u, %c%u vzip.%d %c%u, %c%u vmovn.i%d d%u, q%u vqmovun.s%d d%u, q%u vqmovn.s%d d%u, q%u vqmovn.u%d d%u, q%u vshll.i%d q%u, d%u, #%d vrecpe.%c32 q%u, q%u vrecpe.%c32 d%u, d%u vrsqrte.%c32 q%u, q%u vrsqrte.%c32 d%u, d%u vcvt.f32.s32 %c%u, %c%u vcvt.f32.u32 %c%u, %c%u vcvt.s32.f32 %c%u, %c%u vcvt.u32.f32 %c%u, %c%u vdup.%u %c%u, d%u[%u] ezconq == ARMCondALf%smx%s r%u, {d%u-d%u} f%smiax%s r%u!, {d%u-d%u} f%smdbx%s r%u!, {d%u-d%u} f%smd%s r%u, {d%u-d%u} f%smiad%s r%u!, {d%u-d%u} f%smdbd%s r%u!, {d%u-d%u} fmstat%s fmrx%s r%u, fpscr fmxr%s fpscr, r%u vmov%s d%u, r%u, r%u vmov%s r%u, r%u, d%u vmov%s, s%u, s%u, r%u, r%u vmov%s, r%u, r%u, s%u, s%u vmov%s.8 d%u[%u], r%u vmov%s.16 d%u[%u], r%u vmov%s.32 d%u[%u], r%u vmov%s.%c8 r%u, d%u[%u] vmov%s.%c16 r%u, d%u[%u] vmov%s.32 r%u, d%u[%u] fconsts%s s%u #%ufconstd%s d%u #%uvdup.%d q%u, r%u vdup.%d d%u, r%u f%sd%s d%u, [r%u, %c#%u] fmacd%s d%u, d%u, d%u fnmacd%s d%u, d%u, d%u fmscd%s d%u, d%u, d%u fnmscd%s d%u, d%u, d%u fmuld%s d%u, d%u, d%u fnmuld%s d%u, d%u, d%u faddd%s d%u, d%u, d%u fsubd%s d%u, d%u, d%u fdivd%s d%u, d%u, d%u vfnmsd%s d%u, d%u, d%u vfnmad%s d%u, d%u, d%u vfmad%s d%u, d%u, d%u vfmsd%s d%u, d%u, d%u fcmpz%sd%s d%u fcmp%sd%s d%u, d%u fcpyd%s d%u, d%u fabsd%s d%u, d%u fnegd%s d%u, d%u fsqrtd%s d%u, d%u fsitod%s d%u, s%u fuitod%s d%u, s%u ftosi%sd%s s%u, d%u ftoui%sd%s s%u, d%u f%sms%s r%u, {s%u-s%u} f%smias%s r%u!, {s%u-s%u} f%smdbs%s r%u!, {s%u-s%u} fmrs%s r%u, s%u fmsr%s s%u, r%u f%ss%s s%u, [r%u, %c#%u] fmacs%s s%u, s%u, s%u fnmacs%s s%u, s%u, s%u fmscs%s s%u, s%u, s%u fnmscs%s s%u, s%u, s%u fmuls%s s%u, s%u, s%u fnmuls%s s%u, s%u, s%u fadds%s s%u, s%u, s%u fsubs%s s%u, s%u, s%u fdivs%s s%u, s%u, s%u vfnmss%s s%u, s%u, s%u vfnmas%s s%u, s%u, s%u vfmas%s s%u, s%u, s%u vfmss%s s%u, s%u, s%u fcmpz%ss%s s%u fcmp%ss%s s%u, s%u fcpys%s s%u, s%u fabss%s s%u, s%u fnegs%s s%u, s%u fsqrts%s s%u, s%u fsitos%s s%u, s%u fuitos%s s%u, s%u ftosi%ss%s s%u, d%u ftoui%ss%s s%u, d%u fcvtds%s d%u, s%u fcvtsd%s s%u, d%u vcvt.f32.%c32, s%u, s%u, #%d vcvt.f64.%c32, d%u, d%u, #%d vcvt.%c32.f64, d%u, d%u, #%d vcvt.%c32.f32, d%u, d%u, #%d INSN(11,9) == BITS3(1,0,1)tbbtxsmul%c%c%s r%u, r%u, r%u smulw%c%s r%u, r%u, r%u pkh%s%s r%u, r%u, r%u %s usat%s r%u, #0x%04x, %s ssat%s r%u, #0x%04x, %s ssat16%s r%u, #0x%04x, r%u usat16%s r%u, #0x%04x, r%u uadd16%s r%u, r%u, r%u sadd16%s r%u, r%u, r%u usub16%s r%u, r%u, r%u ssub16%s r%u, r%u, r%u uadd8%s r%u, r%u, r%u sadd8%s r%u, r%u, r%u usub8%s r%u, r%u, r%u ssub8%s r%u, r%u, r%u qadd8%s r%u, r%u, r%u qsub8%s r%u, r%u, r%u uqadd8%s r%u, r%u, r%u uqsub8%s r%u, r%u, r%u uhadd8%s r%u, r%u, r%u uhadd16%s r%u, r%u, r%u shadd8%s r%u, r%u, r%u qadd16%s r%u, r%u, r%u qsub16%s r%u, r%u, r%u qsax%s r%u, r%u, r%u qasx%s r%u, r%u, r%u sasx%s r%u, r%u, r%u smu%cd%s%s r%u, r%u, r%u smlaw%c%s r%u, r%u, r%u, r%u sel%s r%u, r%u, r%u usad8%s r%u, r%u, r%u usada8%s r%u, r%u, r%u, r%u qadd%s r%u, r%u, r%u qdadd%s r%u, r%u, r%u qsub%s r%u, r%u, r%u qdsub%s r%u, r%u, r%u uqsub16%s r%u, r%u, r%u shadd16%s r%u, r%u, r%u uhsub8%s r%u, r%u, r%u uhsub16%s r%u, r%u, r%u uqadd16%s r%u, r%u, r%u uqsax%s r%u, r%u, r%u uqasx%s r%u, r%u, r%u usax%s r%u, r%u, r%u uasx%s r%u, r%u, r%u ssax%s r%u, r%u, r%u shsub8%s r%u, r%u, r%u shasx%s r%u, r%u, r%u uhasx%s r%u, r%u, r%u shsax%s r%u, r%u, r%u uhsax%s r%u, r%u, r%u shsub16%s r%u, r%u, r%u smmls%s%s r%u, r%u, r%u, r%u cmncmpmulorreorandlsllsrasrror16nzlr,addssubsldrstrwfe yield ststteqrsbornbicmvnmovldrbstrbldrdstrd, LSL #1ubfxsbfxuxtbuxthsxtbsxthuxtb16sxtb16mlamlsgfwadcsbc???ldrshldrhldrsbstrh (thumb) 0x%x: r3 = client_request ( %%r4 ) r3 = guest_NRADDR IR injection %s r%u, r%u tst r%u, r%u negs r%u, r%u mvns r%u, r%u bics r%u, r%u adcs r%u, r%u sbcs r%u, r%u uxtb r%u, r%u sxtb r%u, r%u uxth r%u, r%u sxth r%u, r%u %ss r%u, r%u rev%s r%u, r%u revsh r%u, r%u add sp, #%u sub sp, #%u svc #0x%08x add(hi) r%u, r%u cmphi r%u, r%u mov r%u, r%u it%c%c%c %s cb%s r%u, 0x%x nRegs >= 1 && nRegs <= 9push {%s0x%04x} nRegs >= 0 && nRegs <= 8pc,pop {%s0x%04x} %s r%u, r%u, #%u %s r%u, r%u, r%u %s r%u, [r%u, r%u] %sh r%u, [r%u, r%u] ldrsh r%u, [r%u, r%u] ldrsb r%u, [r%u, r%u] %sb r%u, [r%u, r%u] %s r%u, #%u add r%u, pc, #%u add r%u, r13, #%u cmp r%u, #%u movs r%u, #%u ldr r%u, [pc, #%u] %s r%u, [r%u, #%u] %sh r%u, [r%u, #%u] %sb r%u, [r%u, #%u] %s r%u, [sp, #%u] ldmia r%u!, {0x%04x} stmia r%u!, {0x%04x} %ss r%u, r%u, #%u b 0x%x b%s 0x%x nop sev bl 0x%x (stay in Thumb mode) %sm%c%c r%u%s, {0x%04x} add%s.w r%u, r%u, #%u addw r%u, r%u, #%u %s.w r%u, #%u %s%s.w r%u, r%u, #%u subw r%u, r%u, #%u %s%s.w r%u, r%u, %s %s%s.w r%u, r%u, r%u %s%s.w r%u, %s %s.w r%u, %s %s%s.w r%u, #%u movw r%u, #%u movt r%u, #%u rN != rTloadsPC!loadsPCrN != 15%s.w r%u, [r%u, #%c%u] %s.w r%u, [r%u, #%c%u]! bP == 0 && bW == 1%s.w r%u, [r%u], #%c%u %s.w r%u, [r%u, +#%u] %s.w r%u, r%u, [r%u, #%c%u] %s.w r%u, r%u, [r%u, #%c%u]! %s.w r%u, r%u, [r%u], #%c%u b%s.w 0x%x b.w 0x%x tb%c [r%u, r%u%s] mask != 0%s r%u, r%u, #%u, #%u %s r%u, r%u, ror #%u mul.w r%u, r%u, r%u sdiv.w r%u, r%u, r%u udiv.w r%u, r%u, r%u %cmull r%u, r%u, r%u, r%u %s r%u, r%u, r%u, r%u %cmlal r%u, r%u, r%u, r%u umaal r%u, r%u, r%u, r%u smmul%s r%u, r%u, r%u smmla%s r%u, r%u, r%u, r%u sub r%u, pc, #%u bfc r%u, #%u, #%u bfi r%u, r%u, #%u, #%u clz r%u, r%u rbit r%u, r%u msr cpsr_%s%s, r%u mrs r%u, cpsr ldrex r%u, [r%u, #+%u] ldrex%c r%u, [r%u] ldrexd r%u, r%u, [r%u] strex r%u, r%u, [r%u, #+%u] strex%c r%u, r%u, [r%u] strexd r%u, r%u, r%u, [r%u] DSB DMB ISB pld%s [r%u, #%u] pld%s [r%u, #-%u] pld%s [r%u, r%u, lsl %u] mrc p15,0, r%u, c13, c0, 3 mcr p15,0, r%u, c13, c0, 2 mrc p15,0, r%u, c13, c0, 2 mrc p15,0, r%u, c9, c14, 0 clrex ldrt r%u, [r%u, #%u] strt r%u, [r%u, #%u] strbt r%u, [r%u, #%u] ldrht r%u, [r%u, #%u] ldrsht r%u, [r%u, #%u] strht r%u, [r%u, #%u] ldrbt r%u, [r%u, #%u] ldrsbt r%u, [r%u, #%u] pli [r%u, #%u] pli [r%u, #-%u] pli [pc, #%c%u] rscl(assumed not taken)(assumed taken)guest_arch == VexArchARM (arm) 0x%x: pld%c [r%u, #%c%u] eaEpld%c %s pli [r%u, #%c%u] op == Iop_Sub32op == Iop_And32shco == IRTemp_INVALIDshco != IRTemp_INVALID%s%s%s r%u, r%u, %s %s%s%s r%u, %s %s%s r%u, %s taT != IRTemp_INVALIDrD != rN%sr%s%s r%u, %s %sm%c%c%s r%u%s, {0x%04x} b%s%s 0x%x %s b%sx r%u b%sx%s r%u clz%s r%u, r%u mul%c%s r%u, r%u, r%u sdiv r%u, r%u, r%u udiv r%u, r%u, r%u ml%c%c%s r%u, r%u, r%u, r%u umaal %s r%u, r%u, r%u, r%u msr%s cpsr%s%sf, #0x%08x msr%s cpsr_%s%s, r%u mrs%s r%u, cpsr svc%s #0x%08x swp%s%s r%u, r%u, [r%u] movt%s r%u, #0x%04x movw%s r%u, #0x%04x %s%s r%u, r%u, ROR #%d bfc%s r%u, #%u, #%u bfi%s r%u, r%u, #%u, #%u %s%s r%u, r%u, #%u, #%u rD+0 != rNrD+1 != rNrev%s%s r%u, r%u revsh%s r%u, r%u smmul%s%s r%u, r%u, r%u smmla%s%s r%u, r%u, r%u, r%u ldrt%s r%u, [r%u], #%c%u ldrt%s r%u, %s ldrbt%s r%u, [r%u], #%c%u ldrbt%s r%u, %s ldrht%s r%u, [r%u], #%c%u ldrht%s r%u, [r%u], %cr%u ldrsht%s r%u, [r%u], #%c%u ldrsht%s r%u, [r%u], %cr%u ldrsbt%s r%u, [r%u], #%c%u ldrsbt%s r%u, [r%u], %cr%u strbt%s r%u, [r%u], #%c%u strbt%s r%u, %s strht%s r%u, [r%u], #%c%u strht%s r%u, [r%u], %cr%u strt%s r%u, [r%u], %c%u strt%s r%u, %s mrc%s p15,0, r%u, c13, c0, 3 mcr%s p15,0, r%u, c13, c0, 2 mrc%s p15,0, r%u, c13, c0, 2 mrc%s p15,0, r%u, c9, c14, 0 nop%s yield%s dres.whatNext == Dis_Continueirsb->next == NULLirsb->jumpkind == Ijk_Boringnpmwymk_EA_reg_plusminus_shifted_regmk_shifter_operanddecode_NV_instruction_ARMv7_and_belowdisInstr_ARM_WRKllPutIRegput_ITSTATEllPutFReg_up_to_64llGetFReg_up_to_64breakupV128to32sdecode_V8_instructiondecode_V6MEDIA_instructionmath_INTERLEAVE_4math_PERM_8x8x3dis_neon_load_or_storedis_neon_data_2reg_miscdis_neon_data_2reg_and_shiftppNeonImmTypebinop_w_fake_RMdecode_NEON_instruction_ARMv7_and_belowllPutFRegfloatGuestRegOffsetllGetFRegllPutDRegI64llPutDRegllGetDRegdoubleGuestRegOffsetllGetDRegI64mk_skip_over_A32_if_cond_is_falsellPutQRegquadGuestRegOffsetllGetQRegdecode_CP10_CP11_instructionputIRegTloadGuardedLEllGetIRegnewTempgetIRegTisBadRegTmk_skip_over_T32_if_cond_is_falseputMiscReg32put_GEFLAG32desynthesise_APSRmkU8genROR32gen_SIGILL_T_if_in_but_NLI_ITBlockgen_SIGILL_T_if_nonzerosetFlags_D1_D2_NDcompute_result_and_C_after_shift_by_imm5putIRegAintegerGuestRegOffsetgetIRegAmk_ldm_stmmk_skip_over_T16_if_cond_is_falsecompute_result_and_C_after_ASR_by_imm5compute_result_and_C_after_LSR_by_imm5compute_result_and_C_after_LSL_by_imm5mk_armg_calculate_condition_dynget_ITSTATEdisInstr_THUMB_WRKdisInstr_ARMtypeOfIRExpr(irsb->tyenv, cond) == Ity_I320 == (guest_R15_curr_instr_notENC & 1)typeOfIRExpr(irsb->tyenv, e) == Ity_I320 == (guest_R15_curr_instr_notENC & 3)typeOfIRExpr(irsb->tyenv, e) == Ity_V128typeOfIRExpr(irsb->tyenv, e) == Ity_F64typeOfIRExpr(irsb->tyenv, e) == Ity_I64typeOfIRExpr(irsb->tyenv, e) == Ity_F32lowbits_to_ignore == 0 || lowbits_to_ignore == 8 || lowbits_to_ignore == 16 || lowbits_to_ignore == 31shift_amt >= 1 && shift_amt <= 31typeOfIRTemp(irsb->tyenv, t_dep1 == Ity_I32)typeOfIRTemp(irsb->tyenv, t_dep2 == Ity_I32)typeOfIRTemp(irsb->tyenv, t_ndep == Ity_I32)cc_op >= ARMG_CC_OP_COPY && cc_op < ARMG_CC_OP_NUMBERshop && *shop == IRTemp_INVALIDmk_shifter_operand(0x%x,0x%x) VABA should not be in dis_neon_data_3diff VABL should not be in dis_neon_data_3diff (regs == 1 && (inc == 1 || inc == 2)) || (regs == 2 && inc == 2)regs == 1 && (inc == 1 || inc == 2)vcvt.%c32.f32 %c%u, %c%u, #%u vcvt.f32.%c32 %c%u, %c%u, #%u szBlg2 <= 2 && nn <= 14 && tt <= 14strex%s%s r%u, r%u, r%u, [r%u] vml%c.%c%d %c%u, %c%u, d%u[%u] vml%cl.%c%d q%u, d%u, d%u[%u] vqdml%cl.s%d q%u, d%u, d%u[%u] vmul.%c%d %c%u, %c%u, d%u[%u] vqdmull.s%d q%u, d%u, d%u[%u] vqdmulh.s%d %c%u, %c%u, d%u[%u] vqrdmulh.s%d %c%u, %c%u, d%u[%u] VABDL should not be in dis_neon_data_3same VABAL should not be in dis_neon_data_3samevqrdmulh.s%d %c%u, %c%u, %c%u conq >= ARMCondEQ && conq <= ARMCondALINSNA(31,28) == BITS4(0,0,0,0)sml%cd%s%s r%u, r%u, r%u, r%u smla%c%c%s r%u, r%u, r%u, r%u smlal%c%c%s r%u, r%u, r%u, r%u uxtab16%s r%u, r%u, r%u, ROR #%u sxtab16%s r%u, r%u, r%u, ROR #%u smlald%c%s r%u, r%u, r%u, r%u smlsld%c%s r%u, r%u, r%u, r%u branch-and-link-to-noredir r4 disInstr(thumb): unhandled instruction: 0x%04x 0x%04x n_guarded >= 1 && n_guarded <= 4bx r%u (possibly switch to ARM mode) blx r%u (possibly switch to ARM mode) blx 0x%x (switch to ARM mode) op == Iop_And32 || op == Iop_Or32%s.w r%u, [r%u, r%u, LSL #%u] %cxtah r%u, r%u, r%u, ror #%u %cxtab r%u, r%u, r%u, ror #%u blx 0x%x (and switch to Thumb mode) %sr%s%s r%u, %s! (at-EA-then-Rn=EA) %sr%s%s r%u, %s! (at-Rn-then-Rn=EA) %s%s r%u, %s! (at-EA-then-Rn=EA) %s%s r%u, %s! (at-Rn-then-Rn=EA) %cmull%c%s r%u, r%u, r%u, r%u %cmlal%c%s r%u, r%u, r%u, r%u %cxtab%s r%u, r%u, r%u, ror #%u %cxtah%s r%u, r%u, r%u, ror #%u mcr 15, 0, r%u, c7, c10, 5 (data memory barrier) mcr 15, 0, r0, c7, c10, 4 (data synch barrier) mcr 15, 0, r0, c7, c5, 4 (insn synch barrier) disInstr(arm): unhandled instruction: 0x%x cond=%d(0x%x) 27:20=%d(0x%02x) 4:4=%d 3:0=%d(0x%x) 1^D$8D$4 D$8D$4 $Ë$Ë,$ GNUzR| 0uAF v AB C AL lP}AA AAPBJ B$L(B,L0B4JAAA A$F(L,A0B4E8HKA AAl}AA AAPBJ B$L(B,L0B4JAAA A$F(L,A0B4E8HKA AA0(D$AL AFFHApAA ACNAH FAPB N$B(J,B0L4B8JAA E$J(A,A0A4F8LADAJAHADDDWXFZDDDPRJAEHJUVQn EE DKJAYBFZAEFAEHAEUAoDDAAGHdFIHAELLLAAEFAES]PKJAZ DDE GE zR| (24/e0"EA AAQFSBSFKAFFHta AA AAF 'IITPFSBMAFFJHSBSDFFSXEGGF>EGGOzFJHUAEFAEHENWAAGTGAFGFFJHLLFFHh KAGF ZIJATDGSADAAGQ[FFLQSFKHAEFEHBAEAFFHEBFJHLGFFNJFFLPTWF`FFLHOBFFHJFFLFFJA{DAAGSGGAO FSBJJSBNHSBQDFFMAHAFFIHAEFAHAFFJVJJDE  KAGN wDQAMFSBFCMFAAFFH[FSBJBPBNBLEBJDEAFLABEHKAFFHQJSHVeDAAGALNFSBSDFFfBLYO|FFJHLGFFHeFSBSDFFfELVKHAJAElHP\DAGALqFSBSDFFLpGJAMFSBFC[IHAEFAFFLIJPAkDDAADGLWFSBSDFFLpGJAMFSBNBJBPBHEDFEAAFLABEHKEFFJHSBFCTFIHAEMIJAAEJAEFAHAFFAAJPAw DDAADE EGGMGEGGFP EE vFFLFSAIAAL@FSGLDlDFFLLFJHLBFFJ_ KAGM FSBJJSBNHSBNHSBQAFFODHAFODFFIJLAAEIJIAEFAFFFHEPdSDDAGAALJNAWAG[fFSBJNMIIMSIPAiDAAAGVeFWETAFFIRrAAAG[bFFJHLBFFL|GHAgIHEGAAAHAFOFFJHLBFFLiFSBJJSBNHkBJAIAAEFFFHAEFHAEEFFHFFHEGAEAHAFFFEJU\ DDAGI |FOBRAAEFFH[FDHG MZAAJI P EK G KAGN uFFLJGTFFSB_GRJZLINENZAAGLFgB_GRJPFLXAEJTZAAAAG[ FSBJJSBNHSBQDFFMAHAFFIHAEFAHAFFJVJJDN |GRJcQAEJTZ AAAAK EXFSQFEJTU AAAAM ^ EbLIPTVAAR hEXFSQAEJTZ AAAAO _EoAKAEJTZ AAAAO GA[DAAAGAAHXFWAKAEJTZ AAAAR LFSBNHSBJJSEhAQ DFFOAFFLCFJJAEMFHDHMJAEFAELAAEFEFFFHEPcDADAK  EH ZNOFSBJAFFJHSEUAFFHX EF FSBJJSBNHSBTAYAFFIFMFLAJAEJAEFDHAFOJLFMJAEHMAEFAFFFHEPdDDDAGA[ELAGEFHAEOJV[ DDDAGM GFSBQAFFLQJPA_ DAGM R SSBJJSBQAFFFFELBFKFJJAELADAFEFFFHENWAAL DFOAMBFAQESFIFFJHLBFFLFSBNHSBNHSBNHSBNH]BHA^DFFODFFHDMJAEFDFFHDFEFDFFIHAEFAFFHLJPJT` FDGAGAAS mEF\AEGHHKAEFAEFAEHAEJV[ DDDAAO o FWEZFFAFFHHHuAAAGU A FJTSAAN G KAGE EFSBQAFFLYISAqF]B_GRJRFLXFEJTU AAAAS DFJULGHAqOGLS KAGE JFSBNHSBNHSBQDFFODHAFIMJAEFAHAFIAGJNA_ DAAGM  DAAAR C DAAAK FOBHAdDFAA AFFJHSBFSAAEFFHEFSBFHEFEFAHAFFJQhDAAJM | LIPTVAAS eFWBQLFDFFHiFSBIOIIKPQx DAGK RJPAJFSBJNMIIKHJL AK bGHAKOHEGAEAHAFSA[FEIHAEFAHAFFAQFSBJBPBNBLEBJDEAFLABEHKAFFHAJTAdHFAkOFSI EN k FJTSAK G EE t EE AFEIUmIAGAL\ EM P EK IFSAx FSBJJSBNHSBJJSBQAFFGFLBFJJAEJAEHADFFJFKFLAJAEJAEFAHAFFIHAEFAHAFFJVUDAT I FSBQAFFMJVMJJ EFFLIFgB_GRJPFLXAEJTZ AAAAM FQFA EGAEAFFJ ZGRJcQAEJTZ AAAAP lFgB_GRJPFLXAEJTZ AAAAO CFFJHLGFFHhGRJcQFEJTU AAAAO ITfINAeLDAEJFUgAGLYFFLd EH [FSBIOIIKPQTAJF^ EJTSAK DJPAIIHAAFAFFLELAGEFHAEOJV[ DDDAGI vJPAJ EJTSAK EF]B_GRJRFLXAEJTZ AAAAK YFSBIOIIKPSFF DAGE AMIHAEJAEHAAFFH_ DAGE B FIHAEMIG ALDAEJFUkAFNJSBFAIAFFLMVGJ`ROFSBFAHFJHSBQAFFLW EE SFJJAEhFLAPAEUt DAGE P EM EEF\AEFAEHAEJV\ DDAAK QPJPVRx FEJOIEJUVAAAJE W K G KAGE EFSBNHSBNLFDFFSNLFDFFJHSBNHSBMKFJJAEHDGRJRKFJLAAEIGQPQcFFJHLQFFLkBFJHLQFFLQFSBNHSBNHSBNHSBNHSBNH]BHA^DFFODFFLUAEFDFFILDJAEMJAEHADFFIFEFDHAFIFEFAFFHLJPJT` FDGAGAAJ RFKFFBFFHBFFBFFOFHAJFALQFFL]QJ FSBNHSBNHSBNHSBNHSBJJSBNHSBQDFFODHAFODFFMDHAFIFEMFELDMJAEJAEHDAEFAFFFHAEFDFFFFEHAAFFIJRJRVDDAAK yJPAOIHEFEGAEAHAFFASAEJT]EI[IINAFAEJTWINAFAEJTjFFJHLBFFJBFJHLQFFLMAEJTZEGGEZ DAGE Z DAGE GEGGEzJPA] FSB_GRJZLINENZAAK V HAAAJE GEGGEG KAGE TFMCTFJHLGFFHLFYAEHKJPAfFSBNBNBNBHEDJDAAFLABEHKDFFJHSBNBNBNBHEDJDAAFLABEHKDFFFJRHSBIMFMJAEHCAEFAFFYc KAGE BFFAOGFAFAEFAFFHPFSBJBPBNBHEDJEAAFLABEHKAFFJHSBNBNBNBHEDJEAAFLABEHKDFFFJ]ZLAAEJAEb{KGLSFGBF\AEGHHKAEFAEFAEHAEJVXFEHFAEFAFFFHEPo EE GFGBF\AEFAEHAEJVSJPJ_]JAELAAERHP]FEJTUF`KGALMFEJTeAEJTTEFHAEOJV]AEJTTFEJTOAEJTZ EE WJQAHJPJ_]JAELAAERHP]EFHAEOJVr DDAK BFFAFAEJTTAElHPd KAGE AJRHPd KAGE AJPAJOlIAAEFFIHAHAEEFFKHAHEGAEAFFHAJOAbAEJTe EE G EE G KAGE kJPAl EE G EE G KAGE G KAGE ALEFEQA JPAYDDAGE G EE ALEFEQJFFNAEQFLEFEQFLEFEQbHJJAE_JAEHTHEFEFAEHEHIHEFEFAEHAGEQLE 4Hu})}B S$Z _  C"  7/DD  ] " ` " +8 ?   , +F  _@ +{  p +   d   O   O4  80 OB  [ dP  }@ P0  Gx @    4pA  Zmz    P#O  _  0(t  AtK  dlw(    pOP     %`0@\x   !.# "  #t $ @%"&_/T  H (oe)mP+uP,~,  -O00/`3O6 9@=.AkB`CkTD_pI|<  `L' PN'  `P; 0Tb @' { PVO  Y @Z Z d ]w! awG dm hi h     0n      t yO+ @=  V a \  z  ) Е1     ! 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//(/0"5/thumbExpandImmmk_armg_calculate_flag_vmk_armg_calculate_flag_cname_ARMCondcodeassignirsbmk_armg_calculate_condition_dyn__PRETTY_FUNCTION__.3942mkU128mk_skip_over_T16_if_cond_is_false__curr_is_Thumbguest_R15_curr_instr_notENC__PRETTY_FUNCTION__.4016gen_SIGILL_T_if_nonzero__PRETTY_FUNCTION__.4024putMiscReg32__PRETTY_FUNCTION__.3850mk_skip_over_T32_if_cond_is_false__PRETTY_FUNCTION__.4020mk_skip_over_A32_if_cond_is_false__PRETTY_FUNCTION__.4012integerGuestRegOffset.part.0__PRETTY_FUNCTION__.3659isBadRegT__PRETTY_FUNCTION__.3695quadGuestRegOffset.part.0__PRETTY_FUNCTION__.3787doubleGuestRegOffset.part.0__PRETTY_FUNCTION__.3732floatGuestRegOffset.part.0__PRETTY_FUNCTION__.3809DIPimm.part.0__PRETTY_FUNCTION__.5694llGetIReg__PRETTY_FUNCTION__.3663llGetDRegI64__PRETTY_FUNCTION__.3753llGetDReg__PRETTY_FUNCTION__.3736getIRegA__PRETTY_FUNCTION__.3668mk_EA_reg_plusminus_imm8mk_EA_reg_plusminus_reggetIRegT__PRETTY_FUNCTION__.3673mkU8__PRETTY_FUNCTION__.3565llPutQReg__PRETTY_FUNCTION__.3799llPutDReg__PRETTY_FUNCTION__.3744llPutDRegI64__PRETTY_FUNCTION__.3761llPutFReg_up_to_64host_endness__PRETTY_FUNCTION__.3830llPutIReg__PRETTY_FUNCTION__.3678mk_armg_calculate_conditionnewTemp__PRETTY_FUNCTION__.3623put_ITSTATE__PRETTY_FUNCTION__.3859binop_w_fake_RM__PRETTY_FUNCTION__.4388llGetFReg__PRETTY_FUNCTION__.3813llGetFReg_up_to_64__PRETTY_FUNCTION__.3817llPutFReg__PRETTY_FUNCTION__.3825storeGuardedLEgetDRegsetFlag_QCloadGuardedLE__PRETTY_FUNCTION__.3619putDRegputQReg__PRETTY_FUNCTION__.3791putDRegI64or_into_QFLAG32signed_overflow_after_Sub32signed_overflow_after_Add32genROR32__PRETTY_FUNCTION__.3631gen_SIGILL_T_if_in_but_NLI_ITBlock__PRETTY_FUNCTION__.4029putIRegT__PRETTY_FUNCTION__.3691getFReggen_REV16mk_get_IR_rounding_modeput_GEFLAG32__PRETTY_FUNCTION__.3880set_GE_32_10_from_bits_31_15gen_REVputFRegputIRegAr15writtenr15guardr15kind__PRETTY_FUNCTION__.3685set_GE_3_2_1_0_from_bits_31_23_15_7armUnsignedSatQarmSignedSatQmk_convert_IRCmpF64Result_to_NZCVmath_PERM_8x8x3.part.0math_DEINTERLEAVE_2math_INTERLEAVE_2gen_BITREVbreakupV128to32s.constprop.0__PRETTY_FUNCTION__.6602compute_result_and_C_after_LSR_by_imm5__PRETTY_FUNCTION__.4127compute_result_and_C_after_ASR_by_imm5__PRETTY_FUNCTION__.4147compute_result_and_C_after_ROR_by_regcompute_result_and_C_after_LSL_by_imm5__PRETTY_FUNCTION__.4107setFlags_D1_D2_ND__PRETTY_FUNCTION__.3987setFlags_D1_D2setFlags_D1_ND.constprop.0desynthesise_APSR__PRETTY_FUNCTION__.4051compute_result_and_C_after_LSL_by_regcompute_result_and_C_after_LSR_by_regcompute_result_and_C_after_ASR_by_regcompute_result_and_C_after_shift_by_regmath_INTERLEAVE_3in0.5862__PRETTY_FUNCTION__.5828in1.5863in2.5864math_DEINTERLEAVE_3de0.5849de1.5850de2.5851dis_neon_vtbmath_DEINTERLEAVE_4math_INTERLEAVE_4__PRETTY_FUNCTION__.5900mk_ldm_stm__PRETTY_FUNCTION__.7022compute_result_and_C_after_shift_by_imm5__PRETTY_FUNCTION__.4180mk_EA_reg_plusminus_shifted_reg__PRETTY_FUNCTION__.4242mk_shifter_operand__PRETTY_FUNCTION__.4214dis_neon_data_3diffdis_neon_data_3diff.colddis_neon_load_or_store__PRETTY_FUNCTION__.5930dis_neon_data_2reg_and_shift__PRETTY_FUNCTION__.5210decode_V8_instruction.constprop.0CSWTCH.2462__PRETTY_FUNCTION__.6611CSWTCH.2463cvt.6770CSWTCH.2464CSWTCH.2465CSWTCH.2468CSWTCH.2469CSWTCH.2466CSWTCH.2467dis_neon_data_2reg_and_scalardis_neon_data_3samedis_neon_data_processing__PRETTY_FUNCTION__.5356decode_NEON_instruction_ARMv7_and_below.constprop.0__PRETTY_FUNCTION__.6034decode_CP10_CP11_instruction.constprop.0__PRETTY_FUNCTION__.7055decode_V6MEDIA_instruction.constprop.0__PRETTY_FUNCTION__.6045disInstr_THUMB_WRK.constprop.0it_length_table__PRETTY_FUNCTION__.8024__PRETTY_FUNCTION__.3854disInstr_THUMB_WRK.constprop.0.cold__PRETTY_FUNCTION__.7415__PRETTY_FUNCTION__.9069__PRETTY_FUNCTION__.7359.L36.L63.L64.L120.L1884.L1888.L1892.L1889.L1887.L1894.L3407.L4522.L4560.L4578.L4623.L4634.L4602.L5913.L5662.L8451.L8530.L8505.L8569.L8972.L8777.L8819.L10577.L10615.LC0.LC1.LC17.LC4.LC5.LC6.LC7.LC8.LC9.LC10.LC11.LC12.LC13.LC14.LC15.LC16.LC2.LC3.LC20.LC18.LC19.LC21.LC22.LC23.LC24.LC25.LC26.LC27.LC28.LC45.LC35.LC36.LC44.LC30.LC29.LC33.LC34.LC42.LC43.LC32.LC31.LC37.LC38.LC39.LC40.LC41.LC46.LC47.LC48.LC49.LC50.LC51.LC52.LC53.LC54.LC55.LC56.LC57.LC58.LC59.LC60.LC61.LC62.LC63.LC64.LC65.LC66.LC67.LC68.LC69.LC72.LC70.LC71.LC73.LC74.LC75.LC76.LC77.LC78.LC79.LC81.LC80.LC82.LC83.LC84.LC85.LC86.LC87.LC88.LC89.LC90.LC91.LC92.LC93.LC94.LC95.LC97.LC96.LC98.LC99.LC100.LC101.LC102.LC104.LC103.LC105.LC108.LC106.LC107.LC109.LC111.LC113.LC112.LC114.LC115.LC110.LC119.LC116.LC117.LC118.LC120.LC121.LC123.LC130.LC132.LC133.LC126.LC122.LC127.LC129.LC131.LC124.LC125.LC128.LC139.LC136.LC140.LC141.LC142.LC135.LC137.LC145.LC147.LC138.LC143.LC144.LC146.LC149.LC148.LC168.LC159.LC153.LC150.LC164.LC154.LC167.LC157.LC162.LC155.LC165.LC151.LC156.LC158.LC152.LC161.LC166.LC163.LC160.LC174.LC230.LC195.LC196.LC197.LC198.LC199.LC200.LC201.LC202.LC203.LC204.LC205.LC206.LC207.LC208.LC209.LC212.LC213.LC214.LC185.LC186.LC187.LC188.LC189.LC190.LC191.LC192.LC193.LC181.LC183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4$t$WPt$8Pt$Pt$,Pt$, PY[r|$$\DŽ$D$DŽ$DŽ$DŽ$|$$t~DŽ$D$DŽ$DŽ$DŽ$DŽ$D$DŽ$DŽ$DŽ$\DŽ$D$DŽ$DŽ$DŽ$4$PhPh{D$(jjPD$ L$QT$RPPPjW PPW‰ |$hD$ t$Ut$4Pj4$D$(t$D$t$ D$ t$,D$(L$4Qt$t$,T$4RP$PDŽ$pD$DŽ$qDŽ$rDŽ$s$NjD$ ËD$ SPT$R‰l3‹D$ x |$$QDŽ$|D$DŽ$}DŽ$~DŽ$$NjD$ ËD$ SPT$R‰‹D$ jT$1)ڍBD$D$у?1 EEl$|$ PhPP PhPP$׃D$ ÉD$ D$ D$$؉Pt$P|$R=jjZYPYPt$Pt$(D$,t$T$0RP)P$P|$(WP;AD$(= jPL$0D$QT$ RPh(PWPD$|$tCD$ $u*SPRPԋD$ j[D$ jP‹D$m UWP, PhPP Ph6PPDŽ$xD$DŽ$yDŽ$zDŽ${$ NjD$ËD$ SPT$R‰}D ‹D$    PXc PhgP‹D$]u |$D$ $D$ø |$$$DŽ$DŽ$DŽ$DŽ$ RSD$Ph‰R ‹D$(^T$ŋD$ CD$NjD$ $D$UWUL$ QUPSP u |$D$ ËD$$ |$$$FDŽ$DŽ$DŽ$DŽ$ RSD$‰> ‹D$ J T$ŋD$ /D$NjD$ $D$UWUL$ QUPSP DŽ$!DŽ$"DŽ$#DŽ$$RSD$Ph‰c* ‹D$(o DŽ$!DŽ$"DŽ$#DŽ$$RSD$‰‹D$  ؃$NjD$xPhXZD$ <$SRP‰|C‹D$ $$$$ D$ 8D$ŋD$ NjD$SUSWSPD$(P $D$$øNjD$‹$D$ |‰sD$j‰aWT$D$SD$WT$RPh‹D$T$‹D$$$$$uD$ D$ŋD$ NjD$uSUSWSPD$(P p >|4$D$0t$(D$WL$ QPhT$DRPhD$$$WT$RPh‹D$WPht$0D$4t$T$8RPh WPht$ WPh‹D$ OCWt$(D$,t$T$0RPhWPh$4$WPhZ9APh&PP u |$|$,  |$$ DŽ$`D$DŽ$aDŽ$bDŽ$cSǸG$:D$,D$0D$‰&D$4D$ ‰L$4QPS‰WPh‹D$WPh$‹D$jP|$8‰t$‹D$ D$% |$, |$$<T$ŋD$ YD$)NjD$ $D$UWUL$ QUPSP T$, TT$,0|$,|$,|$,P|$, T$, |$,|$, u |$}PøDNjD$ 9‰0D$'|$‰$SD$(t$T$,DŽ$DŽ$DŽ$DŽ$RPD$ D$8t$D$t$L$DŽ$DŽ$DŽ$DŽ$QPD$4DŽ$DŽ$DŽ$DŽ$T$L(RPD$‰ WD$WT$RPhPh‹D$T$KËD$ D$NjD$ ŋD$~SWSUSPP|$$uT$,ڃ|$,T$0؃‰8T$āwɃāvL$4ɃāxL$<:øD$D$$D$D$,D$ $D$8St$0T$@RPL$LQ\$$‰vSD$DD$,aD$(t$T$H|$0D|$4RL$QPW|$4‰)‹D$$5|$D$ D$ŋD$ NjD$|$01SUSWSPRP ى$,PQL$RЉD$TNjD$IËD$$>SPT$R‰'‹D$$3L$D$  D$ŋD$ NjD$|$,tN<$u:SUSWSQRPP$sč밍[P7|$, ʈT$4ى-D$L$,DŽ$:DŽ$vDŽ$;DŽ$w$'øǸD$D$D$$D$ D$ST$(Rt$Pt$‰m4|$‰WW‹D$,fL$,D$ >D$ŋD$ NjD$|$0SUSWSPRP \$$$DŽ$DŽ$DŽ$D$dD$XGD$ ^‹$PD$G‹$9$T$dD$X$$S|$0WfT$h‹D$$D$dɋ$ډ^ÅuqD$ ׿D$NjD$ $D$SWSL$ QSPUP 釿WX덍g|$0 ˆT$8 |$,A |$, |$,  ى҃ƀ|$8d }ʁǀL$T$$$D$ PWD$ D$ PWt$PT$NjD$.|$,tO|$0u:SUSWSQPRP$)č믍ZOiu |$|$$DŽ$D$DŽ$DŽ$DŽ$$KNjD$@ËD$ 5SPT$R‰‹D$ $ T$ŋD$  D$NjD$ $D$UWUL$ QUPSP 鹭|$D$ËD$ xST$D$(ø\X|$,?S‰=‹D$IY|$$T$ŋD$ D$NjD$ $D$UWUL$ QUPSP ϬDŽ$D$DŽ$DŽ$DŽ$$iNjD$^ËD$ SSPT$R‰6‹D$ B D$$ST$DŽ$DŽ$DŽ$DŽ$RPT$‰w‹D$$|$$7lu |$D$0|$$DŽ$ D$DŽ$DŽ$DŽ$$NjD$ ËD$ SPT$R‰‹D$ T$QŋD$ ԪD$NjD$ $D$UWUL$ QUPSP 鄪5DŽ$ D$DŽ$ DŽ$ DŽ$ $NjD$ËD$ SPT$R‰‹D$ |$$7DŽ$D$DŽ$DŽ$DŽ$$jNjD$_ËD$ TSPT$R‰7‹D$ C ODŽ$dD$DŽ$eDŽ$fDŽ$gw|$$DŽ$hD$DŽ$iDŽ$jDŽ$k0|$$&DŽ$D$DŽ$DŽ$DŽ$$3NjD$(ËD$ SPT$R‰‹D$ DŽ$lD$DŽ$mDŽ$nDŽ$oKLf[|$u $bøVDŽ$DŽ$NjD$ 5‰,D$#‰$$UL$QS+$D$$8P$|$RWPh:‰‹D$$sD$ D$tNjD$ dŋD$TSWSUSPPP S|$,IAى/ۃ|$06ʁÈL$NjD$$D$ $RPS‰‹D$ L$D$ D$lŋD$ \NjD$L|$0uaSUSWSPRP DRWPhv‰‹D$$t͍U띍J?ȁÆ.|$,ډT$|$$TƉNjD$ ~@$D$4$RPS ‰‹D$'|$D$ D$ŋD$ NjD$|$$uTSUSWSPRP 髣|$xƉNjD$|d$D$ 몍WLdbm_RepTo64priv/guest_arm64_toIR.cM == 32 || M == 64x == 0len <= 6M >= (1 << len)esize >= (S+1)esize >= (d+1)elem_s < (1ULL << esize)elem_d < (1ULL << esize)rot >= 0 && rot < widthnveqcsccmiplvsvchilsgeltgtlealne0bitQ <= 1 && size <= 38b4h2s1d16b8h4s2dsize < 4sizeNarrow < 4n >= 2 && n <= 64size < 3widenUto64(arm64)isPlausibleIRType(ty)i < 256arm64g_calculate_conditionsphost_endness == VexEndnessLElaneSzB > 0maxOff < 16wspt1 && *t1 == IRTemp_INVALIDt2 && *t2 == IRTemp_INVALIDt3 && *t3 == IRTemp_INVALIDt4 && *t4 == IRTemp_INVALIDsize <= 3ix <= 15is64 == True || is64 == Falseres && *res == IRTemp_INVALIDsize <= 2vecD == IRTemp_INVALIDbitQ == 1ty == Ity_I32imm < wmkSHRt6 && *t6 == IRTemp_INVALIDt7 && *t7 == IRTemp_INVALIDsh_amt < (is64 ? 64 : 32)imm <= 0xFFFFULLimm <= 0xFFFFFFFFULLsize == X01 || size == X10shift < laneBitsuqshlsqshlsqshlufmaddfmsubfnmaddfnmsub%s %s, %s, %s, %s bicorr%s %s.1d, %016llx %s %s.2d, #0x%016llx'%016llx mov %s, #0x%016llx'%016llx imm4 >= 1 && imm4 <= 7[%s, %s][%s, %s lsl %u][%s, %s uxtx][%s, %s uxtx, lsl %u][%s, %s sxtx][%s, %s sxtx, lsl %u]rhsarm64g_dirtyhelper_AESEarm64g_dirtyhelper_AESDarm64g_dirtyhelper_AESMCarm64g_dirtyhelper_AESIMCimcmcaes%c %s.16b, %s.16b aes%s %s.16b, %s.16b efccmp%s %s, %s, #%u, %s uaddlpuadalpsadalpsaddlpusqaddsuqaddclzclsnotcntsqnegsqabsfcmgtfcmgefnegfabs2sqxtnuqxtnsqxtunurecpeursqrtefrsqrtefrecpefcmeqfcmlefcmltrev64%s %s.%s, %s.%s rev32rev16rbitcm%s %s.%s, %s.%s, #0 abs %s.%s, %s.%s neg %s.%s, %s.%s %s %s.%s, %s.%s, #0.0 xtn%s%s %s.%s, %s.%s shll%s %s.%s, %s.%s, #%d fcvtn%s %s.%s, %s.%s fcvtxn%s %s.%s, %s.%s fcvtl%s %s.%s, %s.%s frint%c %s.%s, %s.%s fcvt%c%c %s.%s, %s.%s ok%ccvtf %s.%s, %s.%s fsqrtfmov%s %s, %s fcvt %s, %s frint%c %s, %s ushrusrassrasshrurshrursrasrsrasrshrsqshrnuqshrnsqrshrnuqrshrnsqshrunsqrshrunucvtfscvtffcvtzufcvtzssh >= 1 && sh <= 64!isU%s d%u, d%u, #%u sri d%u, d%u, #%u sh >= 0 && sh < 64shl d%u, d%u, #%u sli d%u, d%u, #%u size >= 0 && size <= 3%s %c%u, %c%u, #%u size >= X00 && size <= X10size == X10 || size == X11bhsdzip1zip2uzp1uzp2trn1trn2%s %s.%s, %s.%s, %s.%s fcvtz%c %s, %s, #%d %ccvtf %s, %s, #%d fminnmfmulfsubfaddfdivfmaxfminfmaxnm%s %s, %s, %s fnmul%s %s, [%s, #%lld] (at-Rn) stldldrs%c %s, [%s], #%llu ldrs%c %s, [%s, #%llu]!ldrstr%s %s, [%s], #%lld %s %s, [%s, #%lld]! ldurstur(fallback implementation)aldrbldrhstrbstrh%s %s, [%s, #%u] ldurbldurhsturbsturhbL == 0 && bX == 0ldr %s, 0x%llx (literal) ldr %s, %s str %s, %s ldruh %s, %s strh %s, %s ldrub %s, %s strb %s, %s bitX == 0ldrsw %s, [%s, #%u] ldrsh %s, [%s, #%u] ldrsb %s, [%s, #%u] ldurs%c %s, [%s, #%lld]ldrsw %s, %s ldrsh %s, %s ldrsb %s, %s %s %s, [%s, #%lld] , #%u, %srbrhrld%sx%s %s, [%s] %s narrowFrom64(arm64)st%sx%s %s, %s, [%s] %s lda%s %s, [%s] stl%s %s, [%s] prfm prfop=%u, [%s, #%u] prfm prfop=%u, %s ARM64 front end: load_store lndres->len == 4dres->continueAt == 0b.%s 0x%llx b%s 0x%llx ret %s blr %s jmp %s cb%sz %s, 0x%llx tb%sz %s, #%u, 0x%llx svc #0 msr tpidr_el0, %s mrs %s, tpidr_el0 msr fpcr, %s mrs %s, fpcr msr fpsr, %s mrs %s, fpsr msr %s, nzcv arm64g_calculate_flags_nzcvmrs %s, nzcv mrs %s, dczid_el0 (FAKED) mrs %s, ctr_el0 mrs %s, cntvct_el0 mrs %s, cntfrq_el0 ic ivau, %s dc cvau, %s dsbdmbisb#0oshldoshstosh#4nshldnshstnsh#8ishldishstish#12sy%s %s nop brk #%u yield hint #%u clrex #%u ARM64 front end: branch_etc uaddlvsaddlvsmaxvumaxvsminvuminvaddvnm%s %s.%c, %s.%s %s %s, %s.%s %s%sv s%u, %u.4s %s %c%u, %c%u cm%s d%u, d%u, #0 abs d%u, d%u neg d%u, d%u %s %s, %s, #0.0 fcvtxn s%u, d%u fcvt%c%c %c%u, %c%u %ccvtf %c%u, %c%u frecpxfmlsfmlafmulxsqmullsqdmlalsqdmlslsqrdmulhsqdmulh%s %c%u, %c%u, %s.%c[%u] %s %c%u, %c%u, v%u.%c[%u] %s %c%u, %c%u, v%d.%c[%u] masslishlrshrnshrn%s %s.%u%c, %s.%u%c, #%u sri%s %s.%s, %s.%s, #%u shift >= 1sh < 32sh < 16sh < 8immh == 0%cshll%s %s.%s, %s.%s, #%u nLanes == 2 || nLanes == 4usubluaddlsaddlssublusubwuaddwsaddwssubwrsubhnraddhnaddhnsubhnuabdluabalsabalsabdlmullmlalmlslsqdmull1q%s%s %s.%s, %s.%s, %s.%s %c%s%s %s.%s, %s.%s, %s.%s size == X11arm64g_dirtyhelper_PMULLQpmullbhsddup %s.%s, %s.%c[%u] dup %s.%s, %s ins %s.%c[%u], %s %cmov %s, %s.%s[%u] ins %s.%c[%u], %s.%c[%u] fcvt%c%c %s, %s %ccvtf %s, %s fmov s%u, w%u fmov d%u, x%u fmov v%u.d[1], x%u fmov w%u, s%u fmov x%u, d%u fmov x%u, v%u.d[1] mlamlsmul%s %s.%s, %s.%s, %s.%c[%u] %s%s %s.%s, %s.%s, %s.%c[%u] lsrlslasrsubaddsbcadcrormaddmsub%s%s %s, %s, %s, %s #%u arm64g_calculate_flag_c%s%s %s, %s, %s mov %s, %s %s %s, %s, %s, %s #%u %cmulh %s, %s, %s cselcsinccsinvcsneguxtbuxthuxtwuxtxsxtbsxthsxtwsxtx%s%s %s, %s, %s %s lsl %u ccm%c %s, #%u, #%u, %s ccm%c %s, %s, #%u, %s revcl%c %s, %s lslvlsrvasrvrorv%cdiv %s, %s, %s %cm%sl %s, %s, %s, %s arm64g_calc_crc32barm64g_calc_crc32harm64g_calc_crc32warm64g_calc_crc32xarm64g_calc_crc32cbarm64g_calc_crc32charm64g_calc_crc32cwarm64g_calc_crc32cxcrc32bcrc32hcrc32wcrc32xcrc32cbcrc32chcrc32cwcrc32cxfaddp d%u, v%u.2d faddp s%u, v%u.2s addp d%u, %s.2d %s%sp %c%u, v%u.2%c uqsubuqaddsqaddsqsubcmgtcmhicmgecmhssrshlurshlushlsshluqrshlsqrshlcmeqcmtstfacgtfacgefrsqrtsfrecps%s %c%u, %c%u, %c%u fabd %s, %s, %s fmulx %s, %s, %s psbfmubfmbfm%ss %s, %s, 0x%x %s %s, %s, 0x%x adr%s %s, 0x%llx andeorands%s %s, %s, 0x%llx imm64 < 0x100000000ULLmovz %s, 0x%llx movn %s, 0x%llx movk %s, 0x%x, lsl %u hw <= 1%s %s, %s, immR=%u, immS=%u imm6 > 0 && imm6 < szBitsextr %s, %s, %s, #%u tbxtbluhsubuhaddshaddshsuburhaddsrhaddumaxuminsmaxsminuabduabasabasabdpmuluminpumaxpsmaxpsminp#0.0guest_arch == VexArchARM64 (arm64) 0x%llx: x3 = client_request ( x4 ) x3 = guest_NRADDR IR injection dup %s, %s.%s[%u] ornbslbitbifaddp %s.%s, %s.%s, %s.%s fabd %s.%s, %s.%s, %s.%s %s%sp %s.%s, %s.%s, %s.%s faddpsha1csha1psha1msha1su0sha256hsha256h2sha256su1arm64g_dirtyhelper_SHA1Carm64g_dirtyhelper_SHA1Parm64g_dirtyhelper_SHA1Marm64g_dirtyhelper_SHA1SU0arm64g_dirtyhelper_SHA256Harm64g_dirtyhelper_SHA256H2arm64g_dirtyhelper_SHA256SU1%s q%u, s%u, v%u.4s %s v%u.4s, v%u.4s, v%u.4s %s q%u, q%u, v%u.4s sha1hsha1su1sha256su0arm64g_dirtyhelper_SHA1Harm64g_dirtyhelper_SHA1SU1arm64g_dirtyhelper_SHA256SU0%s s%u, s%u %s v%u.4s, v%u.4s fcmp%s %s, %s fcsel %s, %s, %s, %s exp < (1ULL << E)frac < (1ULL << F)1 + E + F == Nfmov %s, #0x%llx disInstr(arm64): %s eonbicsq0q1q2q3q4q5q6q7q8q9q10q11q12q13q14q15q16q17q18q19q20q21q22q23q24q25q26q27q28q29q30q31d0d1d2d3d4d5d6d7d8d9d10d11d12d13d14d15d16d17d18d19d20d21d22d23d24d25d26d27d28d29d30d31s0s1s2s3s4s5s6s7s8s9s10s11s12s13s14s15s16s17s18s19s20s21s22s23s24s25s26s27s28s29s30s31h0h1h2h3h4h5h6h7h8h9h10h11h12h13h14h15h16h17h18h19h20h21h22h23h24h25h26h27h28h29h30h31b0b1b2b3b4b5b6b7b8b9b10b11b12b13b14b15b16b17b18b19b20b21b22b23b24b25b26b27b28b29b30b31w0w1w2w3w4w5w6w7w8w9w10w11w12w13w14w15w16w17w18w19w20w21w22w23w24w25w26w27w28w29w30wzrx0x1x2x3x4x5x6x7x8x9x10x11x12x13x14x15x16x17x18x19x20x21x22x23x24x25x26x27x28x29x30xzrpmzmapz putPCputQRegHI64dis_AdvSIMD_fp_to_from_fixedp_convVFPExpandImmdis_AdvSIMD_fp_immediatedis_AdvSIMD_fp_data_proc_2_sourcedis_AdvSIMD_fp_data_proc_1_sourcedis_AdvSIMD_vector_x_indexed_elemdis_AdvSIMD_two_reg_miscmath_REARRANGE_FOR_FLOATING_PAIRWISEmkVecMULmath_MULL_ACCdis_AdvSIMD_three_differentmkVecSHLNdis_AdvSIMD_shift_by_immediatedis_AdvSIMD_scalar_x_indexed_elementmkVecCMPGTSnewTempsV128_7dis_AdvSIMD_scalar_two_reg_miscmath_VEC_DUP_IMMmath_SQDMULHmkVecSUBnewTempsV128_2math_SQDMULL_ACCdis_AdvSIMD_scalar_three_differenttwo_to_the_plustwo_to_the_minusupdateQCFLAGwithDifferenceZHImath_ZERO_ALL_EXCEPT_LOWEST_LANEmkVecQANDqrsarNNARROWSUmkVecQANDqsarNNARROWSUmkVecQANDqrshrNNARROWUUmkVecQANDqrsarNNARROWSSmkVecQANDqshrNNARROWUUmkVecQANDqsarNNARROWSSmkVecSHRNmkVecSARNnewTempsV128_3math_QSHL_IMMdis_AdvSIMD_scalar_shift_by_immmkVecZEROHIxxOFV128math_DUP_VEC_ELEMmath_FOLDVmkVecADDmath_WIDEN_LO_OR_HI_LANESmkVecMINFmkVecMAXFdis_AdvSIMD_across_lanesmkVecCATEVENLANESdis_AdvSIMD_EXTsetFlags_ADD_SUB_conditionallygetShiftedIRegOrZRsetFlags_ADC_SBCgen_indexed_EAnameArr_Q_SZgetQRegLaneputQRegLaneputQReg128math_MAYBE_ZERO_HI64math_DUP_TO_64math_DUP_TO_V128nameQRegLOputQRegLOpreferredVectorSubTypeFromSizeoffsetQReg128offsetQRegLanegetQRegLOgen_narrowing_storegen_zwidening_loadmath_INTERLEAVE4_128math_INTERLEAVE4_64math_INTERLEAVE3_128math_INTERLEAVE3_64math_INTERLEAVE2_128math_INTERLEAVE2_64math_DEINTERLEAVE4_128math_DEINTERLEAVE4_64newTempsV128_4math_DEINTERLEAVE3_128math_DEINTERLEAVE3_64math_DEINTERLEAVE2_128math_get_doubler_and_halvermath_DEINTERLEAVE2_64dis_ARM64_load_storemk_arm64g_calculate_condition_dyndis_ARM64_branch_etcmkU8getIRegOrZRnewTempmathREPLICATEmathRORdbm_RORdbm_highestSetBitdbm_DecodeBitMasksputIReg32orZRputIReg32orSPputIReg64orSPsetFlags_D1_D2_NDdis_ARM64_data_processing_immediateoffsetIReg64putIReg64orZRdisInstr_ARM64_WRKdisInstr_ARM64typeOfIRTemp(irsb->tyenv, t_dep1 == Ity_I64)typeOfIRTemp(irsb->tyenv, t_dep2 == Ity_I64)typeOfIRTemp(irsb->tyenv, t_ndep == Ity_I64)typeOfIRExpr(irsb->tyenv, e) == Ity_I64typeOfIRExpr(irsb->tyenv, e) == Ity_V128typeOfIRExpr(irsb->tyenv, e) == Ity_I32typeOfIRExpr(irsb->tyenv, cond) == Ity_I64opZHI == Iop_ZeroHI64ofV128 || opZHI == Iop_ZeroHI96ofV128 || opZHI == Iop_ZeroHI112ofV128mas == 'm' || mas == 'a' || mas == 's'rearrL && *rearrL == IRTemp_INVALIDrearrR && *rearrR == IRTemp_INVALIDlaneSzBlg2 >= 0 && laneSzBlg2 <= 2sat2q && *sat2q == IRTemp_INVALIDsat2n && *sat2n == IRTemp_INVALIDrshift >= 1 && rshift < laneBitsrshift >= 0 && rshift < laneBits-1ext v%u.16b, v%u.16b, v%u.16b, #%u ext v%u.8b, v%u.8b, v%u.8b, #%u gen_indexed_EA: unhandled case optS == 0x%x shift >= 0 && shift < lanebitsshift >= 1 && shift <= (8 << size)fbits >= 1 && fbits <= (isD ? 64 : 32)fbits >= 1 && fbits <= (isI64 ? 64 : 32)%s %s, [%s], #%lld (at-Rn-then-Rn=EA) %s %s, [%s, #%lld]! (at-EA-then-Rn=EA) %sp %s, %s, [%s, #%lld] (at-Rn) %sp %s, %s, [%s, #%lld]! (at-EA-then-Rn=EA) %sp %s, %s, [%s], #%lld (at-Rn-then-Rn=EA) ldpsw %s, %s, [%s, #%lld] (at-Rn) ldpsw %s, %s, [%s, #%lld]! (at-EA-then-Rn=EA) ldpsw %s, %s, [%s], #%lld (at-Rn-then-Rn=EA) %snp %s, %s, [%s, #%lld] (at-Rn) %s%u {v%u.%s .. v%u.%s}, [%s]%s %s1 {v%u.%s .. v%u.%s}, [%s]%s ld%ur {v%u.%s .. v%u.%s}, [%s]%s %s%u {v%u.%s .. v%u.%s}[%u], [%s]%s szB == 8 || szB == 4 || szB == 2 || szB == 1prfum prfop=%u, [%s, #0x%llx] dres->whatNext == Dis_Continuedres->jk_StopHere == Ijk_INVALIDarchinfo->arm64_dMinLine_lg2_szB >= 2 && archinfo->arm64_dMinLine_lg2_szB <= 17 && archinfo->arm64_iMinLine_lg2_szB >= 2 && archinfo->arm64_iMinLine_lg2_szB <= 17arm64g_dirtyhelper_MRS_CNTVCT_EL0arm64g_dirtyhelper_MRS_CNTFRQ_EL0archinfo->arm64_iMinLine_lg2_szB >= 2 && archinfo->arm64_iMinLine_lg2_szB <= 17archinfo->arm64_dMinLine_lg2_szB >= 2 && archinfo->arm64_dMinLine_lg2_szB <= 17op != Iop_INVALID && nm != NULLsat1q != IRTemp_INVALID && sat1n != IRTemp_INVALIDshift >= 1 && shift <= lanebits%c%s%s %s.%s, %s.%s, %s.%c[%u] ARM64 front end: data_processing_register ARM64 front end: data_processing_immediate (archinfo->arm64_dMinLine_lg2_szB - 2) <= 15(archinfo->arm64_iMinLine_lg2_szB - 2) <= 150 == (guest_PC_curr_instr & 3ULL)branch-and-link-to-noredir x8 %s %s.%s, {v%u.16b .. v%u.16b}, %s.%s 0 == (imm & 0xFFFFFFFF00000000ULL)dres.len == 4 || dres.len == 20disInstr(arm64): unhandled instruction 0x%08x TX]`cfilorux{  !%)-159=AEILORUX[^adgkosw{  !%)-158;>ADGJMPSW[_cgkosw{  !$'*-0369<?CGKOSW[_cgkosw{?@$Ë $Ë$Ë4$Ë<$ GNUzR| hnAB AM~ AAA A F AAA A d ACA A C ACA A A AHA E pAA LAC8 CA AAK I AA AANDoHIL|PHDSHBLUPATIXG\F`AdDhHDAHDLFPFTIXI\|`HDSHBLFPDTKXD\H`AdDhHDAHALFPFTIXF\C`FdFhHDAHFLgPATDXF\F`FdFhHDiHFDSHBLPPHDSHBLNPITJDdHALDPFTFXF\F`KdHDDHdDAHALAPFTFXF\F`KdHDAHFLFPFTHDC AA AAE G HKLAPGTF G HKLAPGTF G HKLAPGTF G HKLAPGTF CHFLFPFTFXHDT HKLAPGTF YHALDPFTFXF\F`KdHDDHdDV HKLAPGTE GHKLAPGT45mAA AANHQLFHSLBPJTEXH\F`AdFhFlHHELFHSLBPJTEXH\F`AdFhFlHHELFHSLBPMTFXF\A`FdFhHHELFHSLBPJTFXH\A`EdFhDlHHALFPJTHHSLBPFTHXH\A`EdFhAlHHALFPJTHHSLBPFTLXH\A`EdFhAlHHALFPJTHHSLBPFTKXH\A`EdFhAlHHALFPJTHHSLBPFTLXJ\A`EdFhAlHHALFP^THHSLBPMTFXF\A`FdFhHHMLFHSLBPHLAHQLFPATFXF\J`HHSLBPFTKXH\A`EdFhAlHHALFPJTHHSLBPFTKXH\A`EdFhAlHHALFPJTHHSLBPITLXJ\A`EdFhAlHHALFPJTHHSLBPFTTXF\A`EdFhAlHHALFPJTHHSLBPFTHXH\A`EdFhAlHHALFPJTHHOLBPITHXH\A`EdFhAlHHALFPJLAHVLFHT LKPATGXE ELFHOLBPITQXF\A`EdFhAlHHALFPJTHHSLBPFTHXE\I`HdAhElHHALHPATEXF\A`FdFhHCA AAL8t>AC AAx C AAE EFSBG H$F(H,A0E4HAHA E$F(A,F0F4HEFSBG H$F(H,A0E4HAHA E$F(A,F0F4HEFSBG H$F(H,A0E4HAHA E$F(A,F0F4HC A AAC E FSBG H$F(H,A0E4HAHA E$F(A,F0F4HEFSBG H$F(H,A0E4HAHG EFOBG H$F(H,A0E4HAJA E$F(A,F0F4HT KA G$E GKA G$:wSAC ACNE FS B$H Ax FS B$J(HU E$F AA E$F(F,O0H4H8APAC AANp tKxA|GE WtLxJ|AEFAFFHpAtJxJ|AEFAFFHpEtFpStBxF|HHAEFAHpAtFxJ|HpStBxF|HEFAFFHpE AA AAA E tFpStBxJ|JpStBxF|LJAEFAHpAtFxF|JJAEFAHpAtFxJ|HpStBxJ|JpStBxN|HpStBxN|HpStBxJ|JJAEFAHpAtFxF|JJAEFDHpAtFxF|FHAEFDHpAtFxF|FHAEFDHpAtFxJ|HpStBxU|LJADFAHpAtFxI|IHADFAHpAtFxJ|HpStBxF|HHADFAHpAtFxP|HEE O tHpStBxF|LJAEFAHpAtFxF|JJAEFAHpAtFxJ|HpStBxJ|JpStBx\|HpStBxJ|JJAEFAHpAtFxF|JJAEFDHpAtFxF|FHAEFDHpAtFxF|FHAEFDHpAtFxJ|HpStBxJ|JpStBxN|HpStBxN|HpStBxx|HpStBxJ|FHAEFAHpAtFxF|FHAEFDHpAtFxJ|FHAEFDHpAtFxF|FHAEFDHpAtFxJ|FHAEFDHpAtFxF|FHAEFDHpAtFxJ|FHAEFDHpAtFxF|FHAEFDHpAtFx|FHAEFDHpAtFxI|IHAAFAHpAtFxI|IHAAFDHpAtFxI|IHAEFDHpAtFxJ|HpStBxJ|JpStBxF|KHADFAHpAtFxI|IHADFAHpAtFxJ|HpStBxF|HHADFAHpAtFxJ|HpStBxF|HEE E tFpStBxJ|JpStBxF|LJAEFAHpAtFxF|JJAEFAHpAtFxJ|HpStBxJ|JpStBxN|HpStBxN|HpStBxJ|JJAEFAHpAtFxF|JJAEFDHpAtFxF|FHAEFDHpAtFxF|FHAEFDHpAtFxJ|HpStBxJ|JpStBxJ|JpStBxN|HpStBxN|HpStBxN|HpStBxN|HpStBxN|HpStBxJ|JJAEFAHpAtFxF|JJAEFAHpAtFxI|IHAEFDHpAtFxI|IHAEFDHpAtFxI|IHAEFDHpAtFxI|IHAEFDHpAtFxI|IHAEFDHpAtFxI|IHAEFDHpAtFxJ|HpStBxJ|JpStBxN|HpStBxN|HpStBxN|HpStBxN|HpStBxN|HpStBxN|HpStBxN|HpStBxN|HpStBxN|HpStBxN|HpStBxN|HpStBxN|HpStBxN|HpStBxN|HpStBxJ|JJAEFAHpAtFxF|JJAEFDHpAtFxF|FHAEFDHpAtFxF|FHAEFDHpAtFxJ|FHAEFDHpAtFxF|FHAEFDHpAtFxJ|FHAEFDHpAtFxF|FHAEFDHpAtFxJ|FHAEFDHpAtFxF|FHAEFDHpAtFxJ|FHAEFDHpAtFxF|FHAEFDHpAtFxJ|FHAEFDHpAtFxF|FHAEFDHpAtFxJ|FHAEFDHpAtFxF|FHAEFDHpAtFxJ|HpStBxJ|JpStBxJ|JpStBxN|HpStBxN|HpStBxN|HpStBxi|JJADFAHpAtFxI|IHADFAHpAtFxI|IHADFDHpAtFxI|IHADFDHpAtFxI|IHADFDHpAtFxI|IHADFDHpAtFxI|IHADFDHpAtFxI|IHADFDHpAtFxJ|HpStBxJ|JpStBxN|HpStBxX|FHAEFAHpAtFxI|IHAAFDHpAtFxI|IHAAFDHpAtFxI|IHAEFDHpAtFxJ|HpStBxN|HpStBxI|HHAEFDHpAtFxI|IHAAFAHpAtFxJ|HpStBxF|KHAAFAHpAtFxJ|HpOtBxF|HEJ GtKxA|GM0EA AN8l `  m t>- x F wSW  p 0{  }7 4  P H  0 (  &@ ?^M f /PF P  M$ =pS l (T l  c @'/  HX  TT  ``9 " PB  [ d+ # Dwm  @ " ~\h    $  $ 5 N6n 0X  T       % $Jl cT  |`  `6D pH R H  D  (  A[Vj " oW- 0  p|5к*`$ y  #      `%,(3:'A8H:O <V#s]a{d@kryWhw  $ f  > G W 7 u                ! ' - 30 9` ? E K  Q W ] c i o u {! * 9 K    T f |            / K U ^ 8  #| ) / 5 ; A G M S Y _ e k q( wL }D 3 Y    t p                n J 1 "X ): 0| 7 > E L S Z a h o v. }, /  k d    r V O   ] H ~ v ( z   : c g  % , 3L : A H Oz V ] d k r y             " 2 ? '  R O ^ ( c u ! ( /{ 6 =T DY K R Yi `o g n; u0 |   P t  f                  $ + 2% 9 @ G N U; \, c j q; x          <  l ` ] M P S   ~     ' . 5 <" C J QU X. _{ fc m tA {      d H    @    j ( m  B   U a # *{ 1 8 ? F M7 T [S b i[ p w ~ m   =  *       @ v "    d   N , b  &C -K 4 ; B I P W ^ e l s z         P   D i w 8 > P J   1 *  X  U "  )  0  7  >  E  L  S  Z  a H h ? o  v " } P  ( / 7 j        D      ! !3 ! ! ! %!Z ,!T 3! :!~ A! H!f O!x V! ]! d!` k!N r! y! ! ! !r !l ! ! ! ! !  ! !& ! ! !2 !l ! !4 !J !0 "Y ", ". " !" (" /"  6" =" D" K" R" Y"# `"' g"+ n"d u"G |" " "y "} " " "# "( "- "2 "7 "< "A " " " " "y " # # # # # $#* +#> 2#R 9#f @#z G# N# U# \# c# j# q# x#a # #  # # #e #i #m #q #u # #F # # # # # # # # $ $ $ $ $$ '$q .$x 5$ <$ C$ J$ Q$: X$ _$) f$R m$K t$D {$W $4 $? $ $ $ $c $. $] $i $ $m $ $ $ $ $ $ $ %N % % % % #% *%= 1%, 8% ?% F%e M%M T% [%= b% i% p% w%? ~% %2 % % %< % %+ % %I %O %W % % %` % % % %! %' &/ &7 &@ &J &c &&| -& 4& ;& B& I& P&` W& ^& e&| l& s& z&4 & & &a & &z &  & &- & & & & & & & & & &' & ' '! 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颟T$1ɉ1T$1҉ljD$ 9909]9@96>T$D$։PD$ %PD$ PЄy T$D$։PD$ %PD$ P讜 閞T$D$։PD$ %PD$ Pd LT$D$։PD$ %PD$ P r T$D$j ։щD$T$ PD$%PD$ Pp覵鮝T$D$j ։щD$T$ PD$%PD$ P_RZT$D$j։щD$T$ PD$%PD$ PT$D$j ։щD$T$ PD$%PD$ PY誴鲜T$D$։PD$ %PD$ Pи耚 hT$D$։PD$ %PD$ P6 T$D$։PD$ %PD$ PP ԛT$D$։PD$ %PD$ PP袙 銛T$D$։PD$ %PD$ P X @T$D$j։щD$T$ PD$%PD$ PT$D$j ։щD$T$ PD$%PD$ P0`萲阚T$D$։PD$ %PD$ Pf NT$D$։PD$ %PD$ P T$D$։PD$ %PD$ Pҗ 麙T$D$։PD$ %PD$ P舗 pT$D$։PD$ %PD$ P> &|$%P PPVIY^|$%P P@IXZ鸘|$%P PH_X遘|$%P P)HY^J|$%P P(zHXZ|$%P P`PCH_Xܗ|$%P PN HY^饗|$%P PLGXZnT$D$։PD$ %PD$ PX $T$D$։PD$ %PD$ PW ږ|$%P PPv G_X飖|$%P P wFY^l|$%P PuFXZ5T$D$T$ PD$ %P`\LXZT$D$T$ PD$ %PpLXZ鵕T$D$T$ PD$ %P KXZuT$D$T$ PD$ %PKXZ5T$D$T$ PD$ %PLXZT$D$T$ PD$ %PLXZ鵔T$D$T$ PD$ %P|LXZuT$D$T$ PD$ %PP; 9r7>T$L$ iT$L$pt܊T$L$p<龊T$L$Pu頊T$L$hw邊T$L$pYdT$L$h;FT$L$s(T$L$0 T$L$rT$L$PΉD$ T$a9X8>0D$T$P @=!XkD$T$P p;(XBD$T$P IXD$T$P EXD$T$P P}ZLjD$T$P Y鞈D$T$P b[^uD$T$P c2_LD$T$P ] X#v}D_邆>σ9y9o9>T$L$0E鰇T$L$'钇T$L$@tT$L$VT$L$8T$L$*T$L$pAT$L$-#ކT$L$UT$L$067领T$L$`鄆T$L$`f99:99>T$L$p T$L$T$L$xυT$L$鱅T$L$v铅T$L${juT$L$гLWT$L$ .9T$L$ T$L$Яt$D$ PPh[ƄT$L$V騄909 3 9 :>T$L$PMT$L$ t/T$L$`VT$L$8T$L$ՃT$L$ b鷃jjPD$ ;jjP 镍hD$@BYX镍jjP 饧hD$@BXZjjP *t$ T$= v1v3 - v1 <= 16vstmtcxbtcebtcdbclststcmstcmybcticicys390_do_cu41cu41s390_do_cu42cu42brctclclecdlftrcdftrs390_do_cu24cu24lngfrlpgfrrllgvstvlgvstrvs390_do_cu21cu21s390_irgen_VEC: unknown typevecs390_irgen_VECL: unknown typeveclmvcinmvcltebrltdbrldebrcdfbrlcdfrlpdfrrlllaxglaoglangencode_dfp_rounding_modecdlgtrclfxtrclgxtrcfxtrcdgtrcdgtraldxtrledtrclfdtrclgdtrcfdtralcrs390x_dirtyhelper_STFLEstflealcgrcpsdralclpebrlpdbrlcebrlcdbrlaalglaagclhlrclhhrchlrclrcrcgrtmhltmlhchhrtmllclgrlndfrtmhhslagalcglaxlaolanldebslbrpopcntcsgslbgrchicihclfilndbrcfilnebrclihslbclgfrcgfrcgficlgficghilaallaaslaslakrxsbgrnsbgrosbgslbgclhfclgclicchfltgfchhsitmclycytmyclhhsiclcliycgicmhclcbassldlsrdlclmyclmcscsys390x_dirtyhelper_STCKstcks390x_dirtyhelper_STCKEstckechsilzrfclfhsilaelalaylaeysrdalzrgcghsichchys390x_dirtyhelper_STCKFstckfclghsiclgfcgfcghbctgriihftdgxttdcdttdcetldetrtdgdtlrvhtdcxtcdlfbrtdgetmdtrmdtraddtrddtratralsihnicmicmycgxtroihlnilhnihlnilloihhcgdtrclrlnihhoilloilhclgrlcrlsldtsrdtcgrliedtrefpclfhlocfhsdtrsdtraadtradtralghrlgfilgbrlghilgdrllilllgfrllgcrllgfrllghrllilfvstllatlfhatrrdtrqadtrmvstllihfllihlllilhlocglgllihhxihfnihfsrlgsrloilfxilfnilfmsfioihfsrlklgatiilflhillzrgfclgfrlcghrlchrlmhiclhrlclghrlmghicgfrllhrllhrlbrllcrsrstbasrbxhgbxlegbxhbxlebctrlhhllchllhhlbhlyloclbrxhbrxlgmsgfibrxlebrxhgllgfatlarlstmstmystmhstmgstamstamyoixixiynioiyniylerldrngrkxgrkogrngrogrkmsgrnrmsrxrkorknrkorllgfllghllgclghlgflgblmlmylamlamylmglmhalgrkalgragrkagrslhhhrshhhralhhlrshhlrahhhrslhhlralhhhrslgrkslgrsgrsgrkahhlralrsrksrarslrkalrkarkslrm = %d lcbbdsgdsgfdsgrdsgfrs390_do_cvbcvbycvbstrvglbllclhyllhlhvlrvmxvmnvmxlvmnlvsvavavgvavglvmaevmalevmalvmevmlevmhvmlvmlhvpkvesravvesrlvverllvveslvvxvovnvmrhvmrlvlpvuphvuplvuplhvupllvnovncvclzvctzm3 == 0vpopctm5 == 4vsbivacvselvesravesrlverllveslvsbcbivacccvcksmvlmvlvmaovmalovmovmlovfeneverimvchvchlvceqvpksvpklsvperms390_irgen_VLVG: unknown typevlvgm3 < 4vlcvscbivaccm4 == 3vfchvfchevfces390_vr_fill: invalid IRTypefrom <= tos390_irgen_VGM: unknown typevgmvlrepvrepivsumqvsumgvsumvgbmvfmsvfmavfsqvfsvfavfdvfmmsgfrclrtcrtclgrtcgrtlzerflogragfralgfrmsyslgfrnngogsgfrooynyxgxmsgxymsalgslgslslysyaysalyagsgala(m4 & 2) == 0(m4 & 8) == 0vpdivllezvfpsos390_irgen_VSEG: unknown typevsegltgrlgrllzdrtrebcsraalsihlcralhsikslfiahiahikalfiafisraksragaihlocfhrvllvlbbbraslbrasleylecdsgldldycltclgtclfitcitclgitcgitsldacextrcedtrcxtrcdtrcxbrkxbrcdbrkdbrcebrkebrwfcwfkcdbkdbcebkebvtmalgfialghsikagfiaghimhyaghiklcgrslgfimhmsgfllgtrlrlltrsgfahahyalgfslgfagfshyshdrdlrddldlgdlgrllgtatlocgrlrvgrsfpcmlrmlgrmrxrxcocnclochhilrvxgrlrvglghrlllghrlllgfrllgfrlltgfrlcgfrvgfmtrtotroolxrltgltxtrlxdtrcxlftrcxlgtrcxftriextrcxgtrsrxtslxtrrxtrqaxtrsxtrsxtraaxtraxtradxtrdxtramxtrmxtralocrcxgbrcxfbrlcxbrltxbrlnxbrlpxbrlxebrlxdbrcxlgbrcxlfbrlxeblxdbalsiasilrvrrisbgrisbgns390x_dirtyhelper_EXtrottrttmfymlprmlglnrmlcdscdsyllhrllhrllderlrlgrllgtlocghiagsialgsicrbclrbclgrbcgrbencode_bfp_rounding_modeclgxbrcgxbrcdgbrcegbrcdlgbrcelgbrclfxbrcfxbrcefbrcelfbrfidbrafiebrafixbralexbrldxbrledbrsqxbrsqdbrsqebrsqdbsqebs390_do_pfpopfposvcclgdbrclgebrcgdbrcgebrclfdbrclfebrcfdbrcfebrdxbrmxbrsxbraxbrddbrmdbrsdbradbrmeebrdebrsebraebrddbmdbsdbadbmeebdebsebaebmsdbrmadbrmsebrmaebrmsdbmadbmsebmaebvclgdvcdlgvcgdvcdgvldevledvfivcgldcibclibltlpgrlngrcrjcgrjclgrjclrjcijcgibclgibclijvslvsravsrlbvsrabvslbvsrlvgfmaclgijcgijvsldblochiltdtrrisbhgrisblgcpyasarearldgrpfdvftcivrepvlvgppfdrlvex s390->IR: unknown insn: unimplemented insn: unimplemented special insn: specification exception: decoding error: s390_decode_and_irgen%02x%02x %02x%02x ex@mvcex@clcex@xcex@ocex@ncex@trex@mvcinex which was executed by exrlguest_arch == VexArchS390XdisInstr_S390_WRKtypeOfIRTemp(irsb->tyenv, cc) == Ity_I64typeOfIRExpr(irsb->tyenv, emwarning) == Ity_I32s390_vr_offset_by_index: unknown types390_vr_offset_by_index: index = %d ; type = s390_vr_offset_by_index: invalid index for given types390_vr_get_type: reserved m valuetypeOfIRExpr(irsb->tyenv, expr) == Ity_I64typeOfIRExpr(irsb->tyenv, expr) == Ity_I32typeOfIRExpr(irsb->tyenv, expr) == Ity_I8typeOfIRExpr(irsb->tyenv, condition) == Ity_I1s390_V128_get_complement: unknown types390_V128_calculate_carry_out: unknown typetypeOfIRExpr(irsb->tyenv, expr) == typetypeOfIRExpr(irsb->tyenv, emfailure) == Ity_I32s390x_dirtyhelper_PPNO_sha512_load_param_blocks390x_dirtyhelper_PPNO_sha512_save_param_blocktypeOfIRExpr(irsb->tyenv, expr) == Ity_I16typeOfIRExpr(irsb->tyenv, expr) == Ity_F32typeOfIRExpr(irsb->tyenv, expr) == Ity_D64typeOfIRExpr(irsb->tyenv, expr) == Ity_F64s390_irgen_VLGV: unknown o2typetypeOfIRExpr(irsb->tyenv, expr) == Ity_D32dis_res->whatNext == Dis_Continues390_getCountToBlockBoundary: invalid mguest_IA_next_instr - guest_IA_curr_instr == S390_SPECIAL_OP_PREAMBLE_SIZE + S390_SPECIAL_OP_SIZEtypeOfIRExpr(irsb->tyenv, expr) == Ity_V128m4 < sizeof(ops) / sizeof(ops[0])m5 < sizeof(mul_ops) / sizeof(mul_ops[0])(index >= 0) && (index < sizeof(ops) / sizeof(ops[0]))m3 < sizeof(ops) / sizeof(ops[0])m5 < sizeof(ops) / sizeof(ops[0])s390_irgen_VREPI: unknown types390_irgen_VSUMQ: invalid type s390_irgen_VSUMG: invalid type s390_irgen_VSUM: invalid type s390_irgen_VLLEZ: unknown types390_irgen_VFPSO: Invalid m5 value?s390_format_RSY_RDRMs390_vr_getVRindexs390_irgen_VESLs390_irgen_VERLLs390_irgen_VLMs390_irgen_VESRLs390_irgen_VESRAs390_irgen_VSTMs390_irgen_VGMs390_irgen_VPOPCTs390_irgen_VCTZs390_irgen_VCLZs390_irgen_VISTRs390_irgen_VMRLs390_irgen_VMRHs390_irgen_VESLVs390_irgen_VERIMs390_irgen_VERLLVs390_irgen_VESRLVs390_irgen_VESRAVs390_irgen_VFEExz{%&'s390_irgen_VFENEs390_irgen_VFAEput_vr_dw0s390_irgen_VPDIs390_irgen_VSTRCs390_irgen_VPKs390_irgen_VPKLSs390_irgen_VPKSs390_irgen_VMLHs390_irgen_VMLs390_irgen_VMHs390_irgen_VMLEs390_irgen_VMLOs390_irgen_VMEs390_irgen_VMOs390_irgen_VMALHs390_irgen_VMALs390_irgen_VMAHs390_irgen_VMALEs390_irgen_VMALOs390_irgen_VMAEs390_irgen_VMAOs390_irgen_VACCCs390_irgen_VACs390_irgen_VSBCBIs390_irgen_VSBIput_vrput_vr_dw1s390_irgen_VUPLLs390_irgen_VUPLHs390_irgen_VUPLs390_irgen_VUPHs390_irgen_VLCs390_irgen_VLPs390_irgen_VFCHs390_irgen_VAVGLs390_irgen_VAVGs390_irgen_VAs390_irgen_VSs390_irgen_VCEQs390_irgen_VCHLs390_irgen_VCHs390_irgen_VMNLs390_irgen_VMXLs390_irgen_VMNput_vr_qw@P`p 0@P`p 0vr_offsets390_irgen_VMXput_gpr_hw0put_gpr_hw1put_gpr_hw2put_gpr_hw3mkU16s390_cc_setput_fpc_w0emulation_warning_with_exprput_gpr_b3put_gpr_b2put_gpr_b1put_gpr_b0s390_irgen_PPNOput_gpr_w0restart_ifput_counter_w0put_counter_w1put_counter_dw0if_condition_gotoput_ar_w0  $(,048<put_gpr_b7put_gpr_b6put_gpr_b5put_gpr_b4put_dpr_dw0put_dpr_w0emulation_failure_with_exprmkU8if_condition_goto_computediterate_ifnext_insn_ifmkiteput_gpr_w1newTempput_fpr_dw0put_fpr_w0@P`p 0fpr_offset@HPX`hpxgpr_offsetput_gpr_dw0s390_decode_special_and_irgendisInstr_S390$Ë$Ë4$Ë<$Ë,$ GNUzR| `{AC CLEFF F$E(F,F0HAEFF I$E(F,F0HA AA`hAC AAMBF G$B(H,H0C4HAGB H$F(LAA AA((AL EFFHA( $AL AFFHAT<PAC ACLFJ HfAHAA C AAF N J LrAA CENHA F$f(B,H0PCA AAXphAE ACLAF U$B(H,G0B4JAJHAAA AAh@AA CENAA F$J(F,E0F4H8EoAF AAUJFAEAF F$HA A AAC GKA G$<%p>WEA AWFEE J$UG AA<&>WEA AWFEE J$UG AA<P&0?WEA AWFEE J$UG AA<&?WEA AWFEE J$UG AA<&?WEA AWFEE J$UG AA<'P@WEA AWFEE J$UG AA`P'@nAA ACMBF F$H(E,F0H4E8HBDF J$JAA AA`' AnAA ACMBF F$H(E,F0H4E8HBDF J$JAA AAL(ArAA CENEA F$i(C,E0TAA AAh(BoEA AAN$r GA AAF t(H,M0D4F8M@jAC CLHFAMGFF HA  AAC G KAG F GKAG d>jAC CLHFAMGFF HA  AAC G KAG F GKAG 4?`kWEA QBFUB F$R GA8L?k`EA QBFWF E$E(Q GAH? lEA q AH LGFET G AF GKAGH?lEA q AH LGFET G AF GKAG @`mEA AMFGH I$H(E,F0A4E8HAAEG H$J(E,H0A4E8HAAEF J$HHEFF HG  AAI GKAG d@`nEA AAUBF I$H(A,E0F4E8JOGF A$E(TG A AAG |(AoEA AQFMA E$G(H,F0A4E8HAESB HTDFF HG  AAD G KAG F AoEA AAiGF H$A(E,F0F4HEAG B$H(F,H0A4E8HAAE F$F(HG A AAH ,BpEA AAdCI H$A(E,F0F4KJCG B$H(I,H0A4E8HAAE F$F(HG A AAA dBqEA AAQBF I$H(A,E0F4E8HPKF A$E(QG A AAC dC rEA AAUBF I$H(A,E0F4E8JOKF A$E(TG A AAK pCrEA AAQBF HPHF A$E(R,G0B4JAJA H$A(E,OG A AAK xCsEA AANMB F$HTH F$A(E,U0B4]8LEA J$A(E,QGA AADpDpt?EA AANX Hk D$F(F,A0E4JQ J$F(A,E0F4F8HK GA AAG G  K$A(G,N G  K$A(G,F G K$A(G,T EuEA ATFOBRA F$F(XG  AAF GKAG pdEPvEA ATFOBFCQGFA F$F(XG  AAI G KAG F GKAG pE wEA ATFOBFCQGFA F$F(XG  AAI G KAG F GKAG lLFwEF AAN04E8UAC HANN A$E(F,A0F4F8TEA AAXFOBFAZDF E$F(A,F0F4JQ A AAH G KA G$F %?-AA ACN$P(F$S(B,F(C$H(B,F0H$P(A,F0J4A8E0nEA AAN Z$F d$D(F,F0A4E8F oFEA SFEET GA>po7EF AAN@nDFHRLAPETFXH\R`AdEhH@ADAHDLRPATDXTGA AAH@GDKHALGPx?p7EF AAN@nDFHRLAPETFXH\R`AdEhH@ADAHDLRPATDXTGA AAH@GDKHALGP|@qEF AAN0N4F8REA AANI HS B$J(JS B$J(JS B$L DM G$F(A,F0F4I8Fp?EA AANMFSB FA]C J$A(F,F0F4S8BLKPGTEXHHLBPFTLHGLBPFTHHLLLPFLCHGLBPFTHHLLLPHLAHGLBPFTHHKLNH_ LKPATGXE G LE VLUPJTNH[LUPJTNHoLUPJTNH|LUPJTNH[LUPJTNHpLFPJTPH[LUPJTNHLLAPFTJXA\E`FdDhHHALFPFLAHYLFPFTAXH\M`JdAhElHHALAPETFXF\NHLLFPRTAXH\F`YHNLBPETAXD\A`GdEhHHGLBPFTHHLLEPOTFXE\M`JdAhElHHULPPFTFXH\A`EdFhJlHHHLEPFTFXI\F`FdHhAlEpHHGLBPFTMHLLKPATGX0dcREA AANy SI AA AAA U SI AA AAK T SI AA AAA I SI AA AAB B SI AA AAF B SI AA AAF w B$F(SQ J$A(E,M0F4E8E0O< iz4< < `!; 0#; $_A 20%K&XA  q&| A  '*T@  0+GdA + 1!09/1`9/A9GG? `9fyP;>o= p>W>W0?W?W?W P@W @n: An] Ar| Bo D HA E 0F PG @H Ho 8@ 7 @OG ?  ` Ov   PP 0Q 0R ?  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D E " F " "  " G H I J  "$ "( ", "0 K4 "8 "< "@ "D "H "L "P "T "X "\ "` "d "h "l "p "t "x "| " " " " " L M " " " " " " N O P Q R S T U V W X " Y Z [ " \ ] " ^ " _ "  ` " a b c  d 8`$\ ,4( Sxu^uxHx P @t$ t$ PPhP0[Ít& Ph#PP Ph$PP Ph%PP Ph&PPSxuV8uyxx P @QPPhP0[ÍPhPP&fPhPPPhPPPhPPSPhP0[ÍS\PhPPt&SPhPPt&UWVSPhP6hh0h h0D$WUP6hhPhPt$P6 Ut$WPhu PhP6[^_]Ít&PhPP<PhPPPh1fUWVSPhP6hh0D$h h0WPP6hhPhP|$WP6 WUWPhu"PhP6[^_]Í&PhPP<PhPPPh1fUWVSh^h0UPP6u[jWhUhPP6 @tNjjP [^_]Í&jjWhUhPP6$롐jPZY[^_]Ít&<PhPP&fUWVSt{)jP_҉X$T$QL$0ZY$9aL$$|QPP7hZhT$0UPPT$2u4jWhUVP[^_]Í&jjWhUVP[^_]ÐjjP ҁT$$PD$0ZYT$ $9u7$|f<PhPPTPhWPPUWVS $jP]҉XT$T$QEL$ 0ZYT$9L$$|QPPuG &A GhZgh0t$PP7u`jD$UhT$ RVPP7 jPPhP7 [^_]Í&jjD$UhT$RVPP7$jjPPhP7 [^_]Ít&jjP ҁT$T$PD$E0ZYT$L$9uD$|\&<PhPP&fTPhWPPSD$uw.[Ít&PhPPPhPPSD$u#w>hPZY[Í&Ph1PPPh2PPSuhhZY[Ít&|Ph:PPSD$t9uw`RPZY[ÐwCt&tjjP [jP[Z[Í&tPhJPP&fUWVSVZ@V0V V0D$V V0D$ V V0V V0YXjPjPjPt$P7jPt$ P7XZtojjP P'UP7UUWPV,1[^_]Í&<PhPPjPZY뒍&jjPjjPfUWVSt$wet$0ZY9ulu[^_]Ívt't$PP7[^_]Í׍&TPhVPPTPhWPPUWVS <hZ h0h h0D$h h0D$ YXjZPUP6jPD$ UT$$RPh(P|$WP6WP|$WP6WPj 1[^_]Í<PhPPjjjPjPjVPhPj PhPUP6jPD$( UT$ RPhP|$WP6 WPh &ST$D$ wt[ÍvPhZY[ÐDPhhPPSD$t#Ph P0[Ít&[J&vSD$t#PhP0[Ít&[Z&vUWVS$D$PT$lt$8L$`D$D$\T$=D$dPǁ@@9D$D$ljD$ D$LD$ D$<D$D$ $l$ȉD$0wNd $D$L|$\$L$T$ ~^N V$[^_]fD$ cPPPhP7wt&L$`jjjPL$`PY|$jPPhP71ɺ]\$L$1T$ fjjPPhP7&fPD$Z&vjjPPhP7jj$L1RPh&D$ L$TRTRTRPPv,Ph(bPP&fj'&f,Ph/bPPPhaPPpriv/guest_mips_toIR.cdres->len == 0dres->continueAt == 00priv/mips_defs.hisPlausibleIRType(ty)!mode64acNo <= 3iregNo < 32archreg < 32sll r%u, r%u, %u 0x%llx: 0x%08x dres->whatNext == Dis_Continuedres->jk_StopHere == Ijk_INVALIDtypeOfIRExpr(irsb->tyenv, e) == tyty == Ity_I32 || ty == Ity_I64guest_arch == VexArchMIPS32 || guest_arch == VexArchMIPS64VEX_MIPS_HOST_FP_MODE(archinfo->hwcaps) >= fp_mode64Error occured while trying to decode MIPS32 DSP instruction. Your platform probably doesn't support MIPS32 DSP ASE. vex mips->IR: unhandled instruction bytes: 0x%x 0x%x 0x%x 0x%x jmp_lit32jmp_lit64disInstr_MIPS_WRKdisInstr_MIPSnewTempmkNarrowTo32putIRegintegerGuestRegOffsetgetIReggetDSPControlgetAccaccumulatorGuestRegOffset$ GNUzR| lA} DFFEF H$HA F G  KAGF G  KAGF G  KAGF G KAGhAx FFEFH HA G G  KAGN G  KAGF G  KAGF G KAG(*AL EFHHA $+AR KAG H@+AR KAGlp^AA CANAE L$B(J,HOB J$JOB J$A(F,B0HRE F$E(F,D0F4B8HAI H$A(E,HJE F$B(HAA AAFGE G$G(FG K A$G(F GE D^AA CANAE L$B(J,HOB N$HOB F$A(H,B0HRE F$E(F,E0F4B8HAF H$A(E,HJE F$B(HAA AAHGE G$G(FG K A$G(F GE 0AC AAPFSDF A$H(B,HKFL A$E(A,F0B4HTBF HA A AAH BBF L$A(E,A0F4B8HEFFAA A AAE GKA G$PAC ACNS F$M KP F$F A` A$F(B,HE FS H$F(A,H0F4JT F$L(A,A0A4HI AA AAH B B$F(L,A0A4A8HI AA AAB B B$F(H] H$F Ai  K$A(G,F G K$A(G,,@AA CCN Z$F(M$K O$I(F$A a$A(F,C0O \$F S$D(I,A0H4B8J T$J(J,E0A4A8FITb@|t P(D  ,9 RW\a&f k<peu>zODmwht     )9EWanu o0  O  #_0F60F<Jjmp_lit64__PRETTY_FUNCTION__.4216jmp_lit32__PRETTY_FUNCTION__.4210putPCintegerGuestRegOffset.part.0__PRETTY_FUNCTION__.3977accumulatorGuestRegOffset.part.0__PRETTY_FUNCTION__.4088putLO.part.0__PRETTY_FUNCTION__.3776__PRETTY_FUNCTION__.4220putHI.part.0dis_branch_likely.constprop.0dis_branch.constprop.0bstmt.7517__PRETTY_FUNCTION__.4297dis_branch_compact.constprop.0__PRETTY_FUNCTION__.4224__PRETTY_FUNCTION__.4232dis_instr_branch.isra.0.constprop.0disInstr_MIPS_WRK_00.isra.0.constprop.0__PRETTY_FUNCTION__.4307has_msa__PRETTY_FUNCTION__.7560__PRETTY_FUNCTION__.7524.LC0.LC1.LC2.LC3.LC4.LC5.LC8.LC6.LC7.LC9.LC10.LC11.LC12.LC13.LC14.LC17.LC18.LC20.LC19.LC15.LC16__x86.get_pc_thunk.bx_GLOBAL_OFFSET_TABLE_IRConst_U64IRExpr_ConstIRStmt_PutirsbaddStmtToIRSBvex_assert_failIRConst_U32isPlausibleIRTypenewIRTempIRStmt_WrTmpmode64IRExpr_GetIRExpr_UnopIRExpr_RdTmpIRExpr_BinopIRStmt_ExittypeOfIRExpraccumulatorGuestRegOffsetgetAccgetDSPControlgetIRegputIRegvex_traceflagsIRConst_U8vex_printfmkNarrowTo32putLOputHIdisInstr_MIPSguest_code; <C=I>T?[+@bAr y  B   !B   "B   #B; <*C0>;?B+@IAZ a m sB   !B   "B   #B; <?+@A; < % 1 $7BB;H <N U a $gBw;} <?+@ADEDEFA GHI(F0A9JDJPKY Gg?oA   %B  & 'B ; <?+@ADE*DCELFTA] GsH~IFAJJK G?A   %B   & 'B" 7;= <GDV+@dEmFuA~ GCJLA G=>=JLAC>* 1 &= 'CBY;_ <l GzC> G+@M G?AD+@ EF!A5 G?CGJTL] u=}JL => G+@M G   & 'B" ) 5 (;BI;O <c GqCw>} G+@M G?A D +@! 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tSV F EE։CS [^ST$ L$D$ZXZXZXZXZXZXZXZXZ X Z X Z X Z X Z X ZXRP[Í&t&WVS9N91Hf8߁yNyHfx߁yNyHfx߁y Ny HfHف:N HfHفzNJHfH فzNJHfH z NZ HfX[^_ÍvSYXYXYXYXY XY XIH HJH JH JH JH J H J HRP[Í&t&SfYfXYfXI [fH fHJfH JfH R fPÐSYXYXI [P Í&t&WVSt$\$L$T$ǁ@Eljǁ EljǁEljƁHƉƁEƉƁǀEƉƁEƉÀˀHÉÃ@EÉà ŀEÉÃE[^_HEƀEE GNUzR|  .EC dA@07En\p7Enx7En7En0EE$PED  A$pED  A(8QEA AV mF4dYEC CAt G FAB PPEA HAE,PEA A AA tEn(?EZD5Ef,`EA A AA.070p7H7`7x0PpQY PP#;P_t?5h_generic_calc_Mul32x4h_generic_calc_Max32Sx4h_generic_calc_Min32Sx4h_generic_calc_Max32Ux4h_generic_calc_Min32Ux4h_generic_calc_Max16Ux8h_generic_calc_Min16Ux8h_generic_calc_Max8Sx16h_generic_calc_Min8Sx16h_generic_calc_CmpEQ64x2h_generic_calc_CmpGT64Sx2h_generic_calc_SarN64x2h_generic_calc_SarN8x16h_generic_calc_QNarrowBin32Sto16Ux8h_generic_calc_NarrowBin16to8x16h_generic_calc_NarrowBin32to16x8h_generic_calc_Perm32x4h_generic_calc_GetMSBs8x16 D`|<h,Hd.symtab.strtab.shstrtab.text.data.bss.note.GNU-stack.note.gnu.property.rel.eh_frame@ !E 'E ,E <H Sd O @T    ]/1023 0 0 0 644 948 ` ELF4( SYXYXY X YXYXYXI[P GNUzR| eEVeh_generic_calc_Perm32x8 .symtab.strtab.shstrtab.text.data.bss.note.GNU-stack.note.gnu.property.rel.eh_frame@e!',<S4O @  x]/1066 0 0 0 644 980 ` ELF4( ST$ [Í&USU [] GNUzR| EI 8 EB AHA  h_generic_calc_MAddF32h_generic_calc_MAddF64 <.symtab.strtab.shstrtab.text.data.bss.note.GNU-stack.note.gnu.property.rel.eh_frame@6!v'v,v<xSXO @  |/]/1107 0 0 0 644 20488 ` ELFL4(   UWVShD$,T$D$0D$4D$8 D$<(D$@yD$DlD$HED$L D$Pq&D$TTsD$XYD$\ D$`) D$d}$$\$h[^_]ÍCt$01҉D$(t$$&v9ЍR u}$ |$$D$ 9l$(|$,l$ ؉|$Ǎt&L$T$ q9\$Yft$f\$vpq $9OD$t$) $f;p|ӉˋD$D$ D$D$fsfCD$ 9D$u|$ G9|$$|$ D$ o9l0"|$$D$ f9l$(|$,l$ ؉|$Ǎt&L$T$ 1Y9t$qf\$ft$vpq $9|cD$t$) $f9p׉ˋD$D$ D$D$fsfCD$ 9D$u|$ G;|$$|$ D$ o=t&t$\$먍t&t$\$HPhPP&t&UWVS˃ 9uV͋$;/s[<$/~#81ݍv \L\ 9ɉ [^_]ÍXPhPP&SH;H}H[Í&RPXZ[Í&SPhPPt&UWVS$@$x:D$@$@D$$@ D$=D$D$@t$HD$ D$4ЉD$$9D$CD$$9D$D$ |$8|$4& @@@@9uD$,t$$t&fx9uD$@D$ЉD$ 9TD$ t$|$ 8f1ۃ fp1fxfXfp@9uԋ$k@LD$ D$<9|$ D$l@ 9|$t$h<Ӊ|$099 t$ t$0t&@9u鋄$XD$lD$8t$ D$D$L|$D$D$@(P$4V$PF< t N@1FHF8D$D$4$1҃fD$$Dfǁ9|$\$  pYT9$D$f9_ D$fA9T$v4$V^ ~T$P ډD$ T$,T$,D$(D$(|$T lj\$Xt$,t$,_ZT$,Džnƒ\$?)9ӍCG9T$t$`$T$\v;<$y\$(11ҋt$, ى!! t͋\$t$TL$P!!ËD$X!щt$! Ɖ D$<\ D$0D$D$ ;\$|D$4P1 t$$ N9 ;D$:uJ;L$|̍pPhPP|$89|$u:|$9|$HuD$@Ĭ[^_]ÍpPhPPpPhPPpPhPPpPhPPpPh%PPpPhPP}pPh$PP19T$D$$Pt/ ;D$ k D$4x @%9u뵍pPhPPpPhbPPD$8D$$WDŽ$p8T$Lt$( fD$ÃT$DD$ 9L$~89\$DtmSyU{$uЀD$%9D$ L$$ Ayk D$H;L$ ;L$= HRcInt32 && rc <= HrcLAST0 == (con->guest_sizeB % LibVEX_GUEST_STATE_ALIGN)doRegisterAllocation: out-of-range vregvreg_lrs[k].reg_class == hregClass(vreg)doRegisterAllocation: first event for vreg is ReaddoRegisterAllocation: first event for vreg is ModifydoRegisterAllocation: first event for rreg is ReaddoRegisterAllocation: first event for rreg is Modify(rreg_live_after[j] == INVALID_INSTRNO && rreg_dead_before[j] == INVALID_INSTRNO) || (rreg_live_after[j] != INVALID_INSTRNO && rreg_dead_before[j] != INVALID_INSTRNO)rreg_lrs_la[j-1].live_after <= rreg_lrs_la[j].live_afterrreg_lrs_db[j-1].dead_before <= rreg_lrs_db[j].dead_beforevreg_lrs[j].reg_class == HRcINVALID0 == ((UShort)vreg->spill_offset % 16)0 == ((UShort)vreg->spill_offset % 8)rreg_state[hregIndex(reg)].disp == Unavailrreg_state[j].disp == Bound || rreg_state[j].disp == Free || rreg_state[j].disp == Unavailrreg_state[j].eq_spill_slot == FalsehregClass(con->univ->regs[j]) == hregClass(rreg_state[j].vreg)hregIsVirtual(rreg_state[j].vreg)hregIndex(rreg_state[k].vreg) == jhregClass(vregS) == hregClass(vregD)IS_VALID_VREGNO(hregIndex(vregD))IS_VALID_VREGNO(hregIndex(vregS))rreg_lrs_la_next <= rreg_lrs_usedii == rreg_lrs_la[rreg_lrs_la_next].live_aftervreg_lrs[m].reg_class != HRcINVALIDvreg_lrs[m].dead_before >= ii+1! sameHReg(reg_usage_arr[ii].vRegs[0], reg_usage_arr[ii].vRegs[1])vreg_lrs[p].reg_class != HRcINVALIDreg_usage_arr[ii].vMode[j] == HRmModifyreg_alloc: can't find a register in class: reg_alloc: can't create a free register.rreg_state[spillee].disp == BoundhregClass(con->univ->regs[spillee]) == hregClass(vreg)! sameHReg(rreg_state[spillee].vreg, vreg)rreg_lrs_db_next <= rreg_lrs_usedii+1 == rreg_lrs_db[rreg_lrs_db_next].dead_beforerreg_lrs_la_next == rreg_lrs_usedrreg_lrs_db_next == rreg_lrs_usedLibVEX_N_SPILL_BYTES is too low. Increase and recompile.size >= 0used == *sizepriv/host_generic_regs.hinstrs_in->arr_used <= 15000n_vregs < 32767n_rregs > 0hregIsVirtual(vreg) vreg %d, n_vregs %d OFFENDING VREG = %d doRegisterAllocation(1) OFFENDING RREG = OFFENDING instr = isR && isW!hregIsVirtual(rreg)ix < n_rregs!hregIsVirtual(reg)k < rreg_lrs_usedIS_VALID_VREGNO(k)vreg_state[k] == jIS_VALID_RREGNO(k)rreg_state[k].disp == BoundIS_VALID_VREGNO(m)IS_VALID_RREGNO(n)IS_VALID_VREGNO(vregno)spill1 || spill2rreg_state[n].disp == Boundn == INVALID_RREG_NOreload1 || reload2IS_VALID_RREGNO(spillee)vreg_lrs[m].dead_before > iirreg_lrs_db_next >= 0rreg_state[k].disp == UnavailhregClassfindMostDistantlyMentionedVRegsanity_check_spill_offsetsortRRLRarrayensureRRLRspace_SLOWdoRegisterAllocation_v2$Ë4$Ë,$ GNUzR| PAA AAN| AA AAA KAGLpAA ALEW AA AAA I K A$G(E ,3A_ H A AF AA +AR KAGEL AAF G L A Q  F F A ;  K A  C L H G E I G L I  K A G L Y  K A G L I  K A G L I  K A G L G  K A G F G  K A G F 2  R K L Q P K L M )  K A G E _  K A G E I  K A G E I  K A G E V  Q P K O A A L E I  K A G E I  K A G E O  R K L Q P K L E x J F A q  K A G N   K A G E G  C L E T  E I  K A G E  E I G E ^ AA AAA I  K A G E I  K A G E G E I G E I  K A G E I  K A G E I  K A G E W  K A G E G  E E I  K A G E K  K A G E I  K A G E I  K A G E G  E E I  K A G E f  K A G E G E I G E   K A G E G  E E I  K A G E V  K A G E I  K A G E   E E m A A I ] L E M  D D P l  K A G E  G D P { A F H H M  E I G E r E F A ~  E E I  K A G E  A D H H M  A F H H M } D D H T E I G E G E I G E I  K A G E G  E E G  E B [  K A G E I  I L L E S E I G E G E I G E I  K A G E I  K A G E I  K A G E G  E E ^ A F A D M n E I G E O  E E G  E E G  E E G  E E G  E B I  K A G E G  E E I  K A G E G  E E E P H c   K A G E I  K A G E G  E E G  E E I  K A G E R  K A G E I  K A G E f  E E G K A G   4H (=X V3`+q  p ,         j  @1 N ^  %~ + 1h7= C I  O Ut[Hag4m sy> `< , `4$Q l   H    0? !'-03 9w ?\E& KQd W]Tctir ou{\     &5>V l{sortRRLRarray__PRETTY_FUNCTION__.3440ensureRRLRspace_SLOW__PRETTY_FUNCTION__.3417addHInstrhregClass.part.0__PRETTY_FUNCTION__.3177__PRETTY_FUNCTION__.3491__PRETTY_FUNCTION__.3407__PRETTY_FUNCTION__.3393.LC0.LC1.LC2.LC3.LC4.LC17.LC14.LC15.LC9.LC13.LC5.LC6.LC7.LC8.LC18.LC10.LC19.LC22.LC23.LC21.LC24.LC25.LC11.LC12.LC26.LC27.LC20.LC30.LC28.LC16.LC73.LC29.LC38.LC72.LC71.LC31.LC34.LC47.LC33.LC32.LC35.LC37.LC39.LC36.LC43.LC48.LC44.LC45.LC46.LC42.LC50.LC55.LC59.LC56.LC58.LC51.LC66.LC65.LC60.LC61.LC52.LC41.LC63.LC62.LC64.LC40.LC49.LC53.LC54.LC70.LC69.LC68.LC67.LC57__x86.get_pc_thunk.bx_GLOBAL_OFFSET_TABLE_vex_assert_fail__x86.get_pc_thunk.siprivate_LibVEX_alloc_currprivate_LibVEX_alloc_lastprivate_LibVEX_alloc_OOMaddHInstr_SLOW__ctzdi2doRegisterAllocation_v2__x86.get_pc_thunk.bpnewHInstrArrayvpanicvex_printfvex_bzeroaddToHRegRemapHRegUsage__containsppHRegClassd e   fg e+h+iR [ g mftjd ekd e   fn e1ot+i}+htl p  q  p & / 5 fB K W ] fz   f   f   f   f  % + fU ] c q q q q ! p  " f) 2 > #D fJ S _ $e fk t  % f j  q q & q ' p  ( f  & ),f2 : @q]qc iqq *prX a m +sfW ` l ,rfx q -p .p   /f   0f) 2 > 1DfJ S _ 2efk w  3f   4f   5f   6f   7f / 8 D 8Jf   9f   :f   ;f    <!f   =f   >fA J V ?\fb s |  @f   Af   Bf s ' 3 C9fs   Dft    Efs   Ff   Gf   H!f' 8 X a m Isfy Jqu q Kp   Lf   Mf    Nf  , O2f8 A M PSfY    Q# f1 B S d u  R f  S f ! ! ! T!f! ! ! U!f! " " " )" V/"f>" G" S" WY"f_" h" t" Xz"f" " " " Y"f t $8.symtab.strtab.shstrtab.group.rel.text.data.bss.rodata.str1.4.rodata.str1.1.rodata.text.__x86.get_pc_thunk.bx.text.__x86.get_pc_thunk.si.text.__x86.get_pc_thunk.bp.note.GNU-stack.note.gnu.property.rel.eh_frame4d<gDn&P"" @A ,#2#72 #F2*Up-]-y-... .D @K@d6`d =K/1153 0 0 0 644 18400 ` ELFD4(   SH;H}H[Í&RPXZ[Í&SPhPPt&UWVS,|$Pl$@L$L$HD$ D$L9F$ ;,S D$4 $D$kT$HLT$DT$L$t& ;,w1>uFD$Pt$ ZYt5D$P ;,vϋD$L$ ,[^_]Ív$9D$HD$T$|$ L$H|$t$$l$@։D$(t&EL9,$tMWVZYt|$ t$$l$@9L$aD$9 $D$eD$PL$|$ t$$l$@L$(9L$!D$D$D$(D$ PUPPD$HD$(멍&UWVS\$8l$0|$\$ \$,؋\$4D$D$<,9@D$$t$ L7&vt$f;^}r+\$ ;$v $D$ 9|K2utCqf9f;n}2|$ uϋ\$ PhPPt&D$[^_]øt&UWVS $;T$$t$ փ~N ρ9|$,T$4Tj-h9$f9F~D$4D$D$P(FRPQD$PD$PD$HP T$|D$0L$0@;A L$0AT$uAF FF %@D$(@@ [^_]ÍD$0L$0@;ADˋ C뜍t&PhNPP&fPhPPPhHPPPhIPPPhLPPPhMPPPhOPPT$PhVPPt&Rt$4Y]f&Rt$4XZV&UWVS$@$@ D$HD$ $@D$ t$ D$\$ {S KL$($jQt$ PL$8D$ /L$(;L$ ${DD$,T$|$tL$D$CD$tQ(D$xRPt$4t$L$P$P$L$X D$HL$DT$xL$DtD$HL$DL$Dk L$H@D$,CC PQt$< D$|$t kD$( DD$l(PhPP$$@D$0PD$Pt$(t$8D$L$$t$`t$ 0instrs_in->arr_used <= 15000hregIsVirtual(vreg)vreg %u (n_vregs %u) Offending vreg = %u Offending instruction = 0 Offending rreg = isR && isWIS_VALID_VREGNO(vs_idx)IS_VALID_VREGNO(vd_idx)! sameHReg(vregS, vregD)IS_VALID_VREGNO(v_idx)rreg_lrs->lrs_used > 0IS_VALID_RREGNO(_r_free_idx)move != NULLhregIsInvalid(rreg)rc >= HRcInt32 && rc <= HrcLASTdoRegisterAllocation_v3: cannot find a register in class: doRegisterAllocation_v3: cannot find a register.priv/host_generic_reg_alloc3.cvreg_state[v_idx].disp == AssignedhregClass(con->univ->regs[r_idx]) == hregClass(vreg)vreg_state[v_idx].dead_before > (Short) current_iivreg_state[v_idx].reg_class != HRcINVALIDspill1 != NULL || spill2 != NULL(con->guest_sizeB % LibVEX_GUEST_STATE_ALIGN) == 0doRegisterAllocation_v3: out-of-range vregvreg_state[v_idx].reg_class == hregClass(vreg)doRegisterAllocation_v3: first event for vreg is "Read" (should be Write)doRegisterAllocation_v3: first event for vreg is "Modify" (should be Write)doRegisterAllocation_v3: first event for rreg is "Read" (should be Write)doRegisterAllocation_v3: first event for rreg is "Modify" (should be Write)hregClass(vregS) == hregClass(vregD)vreg_state[v_idx].reg_class == HRcINVALID(vreg_state[v_idx].spill_offset % 16) == 0(vreg_state[v_idx].spill_offset % 8) == 0!hregIsVirtual(vreg_state[v_idx].rreg)rreg_state[r_idx].disp == BoundhregIndex(rreg_state[r_idx].vreg) == v_idxhregClass(vreg_state[v_idx].rreg) == hregClass(con->univ->regs[r_idx])hregIsVirtual(rreg_state[r_idx].vreg)hregIndex(vreg_state[v_idx].rreg) == r_idxrreg_state[r_idx].eq_spill_slot == Falserreg_lrs->lr_current_idx < rreg_lrs->lrs_usedrreg_lrs->lr_current->live_after <= (Short) ii(Short) ii < rreg_lrs->lr_current->dead_beforehregIsInvalid(vreg_state[vs_idx].rreg)vreg_state[v_idx].dead_before >= (Short) (ii + 1)! sameHReg(reg_usage[ii].vRegs[0], reg_usage[ii].vRegs[1])reload1 != NULL || reload2 != NULLN_SPILL64S is too low in VEX. Increase and recompile.spill_vregfind_free_rreghregClassdoRegisterAllocation_v3$Ë<$Ë,$ GNUzR| ,3A_ H A AF AA L@+AR KAGdppAA AAN@DDHFDA@o CA AAD FDAHFDA@x DFHLLLPE LP AA LAC, 0K4A8G a +^ +_   U, 5 W; A Wa g Wm s Y  ! U   U  " U   #U$ - 9 $?UE N Z %`Uo[   &U]a 'W W  W (Yb   ) U  ' *-U3 < H +NUT ] i ,oUu ~  -U   .U WW /W 0Y  W W7 =WC 1IYMcu   2U   3!UEcS _ h 4nUt   5U > 3 < H 6NU   7U   8U $ 0 96U<    :U   U   ;U   <U   =#U) : C O >UU[ d p vU|   ?U   @U [V  C L X A^Ud BlYr    CU     DU    EU   FU 'W W $ W* G0 Y6 Pt,  .symtab.strtab.shstrtab.group.rel.text.data.bss.rodata.str1.1.rodata.str1.4.rodata.text.__x86.get_pc_thunk.bx.text.__x86.get_pc_thunk.di.text.__x86.get_pc_thunk.bp.note.GNU-stack.note.gnu.property.rel.eh_frame4R<ZD]&PE " @:, 2 72 F2H"U)@]D)yH)L)P)P)l) @lCHX1@R 7KC/1199 0 0 0 644 90028 ` ELF[4(SPhPPt&SPhPPt&SJwu?x[wp[Í PhPP&fPh8PPPh9PPPh;PPSJwu?x[ƒxuo[Ív PhPP&fPh.PPPh/PPPh1PPWVS~xax~we|x8x׍p σx8 ʃ[^_ÍPh/PP PhPPPh.PPPh1PPPhLPPWVSw]~wm΃x׍H  [^_Í&PhPP PhPPPh.PPPh/PPPh1PPPhLPPUWVStdu|rt6uzvWUD$Fv WUD$F [^_]fvWPD$FY[[^_]ÍvrWPD$FXZ[^_]ÍPP&t&VS t[^ÍvV ƃJ4DŽ 0DŽ$`DŽ(pDŽ,DŽ0DŽ4 XJ@J DŽ80DŽ<0DŽ@ 0DŽD 00DŽH @0DŽL P0dJ HJDŽP @DŽT @DŽX @DŽ\0@DŽ`@@DŽdP@DŽh`@DŽlp@lJ$DŽp@ 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JMmGوGGك~G FJƒ\G ݍG W $rT$jl$ UT$ r jUG GD$GGًN G1Vu-f/FhF AGœ@G묅RG9iiV ĉo<PvF-$fFGوGfGF LJPGوGfoF螇ƒ_.oFN P7NG1P&vff/n FfnVGN RyN 9N@I f븍Ph PPPhN PPPh- PPPh PPPh PPPh PPPh PPPh PPPh PPPh PPGfVJV IPh GًN G褐G݋N G苐Ph 9t$G W G W GN 蝇kV [衄h0UZY0hUZYh UZYu  Ph PPPPh;PPPPPPPh 믍&vÍUWVSl$|$t$uk>~WZ9D$ ~~D$$)PW ufFEZY[^_]&fXPh PPXPh% PPXPh& PPXPh( PPXPh) PPUWVS|$|$t$u{>t&DPh^ PP&~uԀ~ u΍nUZD9D$ ut$$U7fFGZY[^_]DPhI PPSD$|$ 8xxx'x=xuwxMxcxyx x x x x L$HʋL$P A[t&0Ph~ PP0Phv PP0Phy PP0Phz PP0Ph{ PP0Ph| PP0Ph} PP0Ph PP0Ph PP0Ph PP0Ph PP0Ph PP0Ph PP0Ph PP0Ph PPpriv/host_x86_defs.c1 <= i && i <= 70 <= i && i <= 6priv/host_generic_regs.hhregClass(r) == HRcFlt64!hregIsVirtual(r)n <= 5hregClass(r) == HRcInt32n <= 7(reg|regmem) < 8gregEnc < 8mapRegs_X86AModemapRegs_X86RMr >= 0 && r < 8%sr >= 0 && r < 6%%fake%d%%xmm%dppHRegX86ALWAYSobnbznzbenbesnspnplnllenlenoppX86CondCodeshift >= 0 && shift <= 3dopyX86AMode(0x%x(),,%d)ppX86AModeshift < 4(regindex|regbase) < 8doAMode_M: unknown amode$0x%xppX86RMIppX86RIppX86RMnegnotshowX86UnaryOpmulmovaddsubadcsbbandorxorcmpshowX86AluOpshrsarshlshowX86ShiftOp2xm1divscaleatanyl2xyl2xp1premprem1sqrtabschssincostanroundshowX86FpOppunpcklqmov(?!)maxmincmpFeqcmpFltcmpFlecmpFunrcprsqrtandnpaddbpaddwpadddpaddqpaddusbpadduswpaddsbpaddswpsubbpsubwpsubdpsubqpsubusbpsubuswpsubsbpsubswpmullwpmulhuwpmulhwpavgbpavgwpmaxwpmaxubpminwpminubpcmpeqbpcmpeqwpcmpeqdpcmpgtbpcmpgtwpcmpgtdpsllwpslldpsllqpsrlwpsrldpsrlqpsrawpsradpackssdwpacksswbpackuswbpunpckhbpunpckhwpunpckhdpunpckhqpunpcklbpunpcklwpunpckldshowX86SseOpop != Xalu_MULis_sane_RetLoc(rloc)cond != Xcc_ALWAYSszSmall == 1 || szSmall == 2sz == 1 || sz == 2sz == 4 || sz == 2 || sz == 1sz == 2 || sz == 4 || sz == 8hregClass(dst) == HRcVec128sz == 4 || sz == 8op != Xsse_MOVorder >= 0 && order <= 0xFFfastslowllwdmode64 == False%sl %%cl,$%d,testl $%d,leal %cmull %cdivl %sdl %%cl, $%d,pushl call%s[%d,] 0x%x(xDirect) if (%%eflags.%s) { movl $0x%x,; (xIndir) if (%%eflags.%s) { movl (xAssisted) movl cmov%s mov%c%cl mov%c setl%s bs%cl mfence(%s)lock cmpxchg%c {%%eax->%%ebx},g%sD gld%c , gst%c gild%s gist%s gdtof gcmov%s fldcw fstsw %%axgcmp const $0x%04x,movups movs%s %sps %sss %spd %ssd %s pshufd $0x%x,(evCheck) decl ; jns nofail; jmp *; nofail:ppX86InstraddRegUsage_X86AModeaddRegUsage_X86RMIaddRegUsage_X86RIaddRegUsage_X86RMgetRegUsage_X86InstrmapRegs_X86RMImapRegs_X86RImapRegs_X86InstroffsetB >= 0!hregIsVirtual(rreg)nbuf >= 32 emit_X86Instr:call:regparmsdelta > 0 && delta < 40disp_cp_xindir != NULLemit_X86Instr:mfence:hwcaps! hregIsInvalid(swap)do_fop1_st: unknown opdo_fop2_st: unknown opemitX86Instr(FpLdSt,load)emitX86Instr(FpLdSt,store)0hregClass(r) == HRcVec128(gregEnc|eregEnc) < 8p - p0 == 3p - p0 == 5p - p0 == 8!(*is_profInc)emit_X86Instrp - &buf[0] <= 32endness_host == VexEndnessLEp[0] == 0xBAp[5] == 0xFFp[6] == 0xD2validp[0] == 0x83p[1] == 0x05p[2] == 0x00p[3] == 0x00p[4] == 0x00p[5] == 0x00p[6] == 0x01p[7] == 0x83p[8] == 0x15p[9] == 0x00p[10] == 0x00p[11] == 0x00p[12] == 0x00p[13] == 0x00%eax%ecx%edx%ebx%esp%ebp%esi%edirc >= HRcInt32 && rc <= HrcLASTdoAMode_M: can't emit amode IRRSdoAMode_M: can't emit amode IRop == Xsh_SHL || op == Xsh_SHRregparms >= 0 && regparms <= 30 == (hwcaps & ~(VEX_HWCAPS_X86_MMXEXT |VEX_HWCAPS_X86_SSE1 |VEX_HWCAPS_X86_SSE2 |VEX_HWCAPS_X86_SSE3 |VEX_HWCAPS_X86_LZCNT))sz == 4 || sz == 8 || sz == 10movl $disp_cp_chain_me_to_%sEP,%%edx; call *%%edx }; movl $disp_indir,%%edx; jmp *%%edx }; movl $IRJumpKind_to_TRCVAL(%d),%%ebp; movl $disp_assisted,%%edx; jmp *%%edx }lock cmpxchg8b {%%edx:%%eax->%%ecx:%%ebx},(profInc) addl $1,NotKnownYet; adcl $0,NotKnownYet+4getRegUsage_X86Instr:Call:regparmsi->Xin.Sse32Fx4.op != Xsse_MOVi->Xin.Sse32FLo.op != Xsse_MOVi->Xin.Sse64Fx2.op != Xsse_MOVi->Xin.Sse64FLo.op != Xsse_MOVgenSpill_X86: unimplemented regclassgenReload_X86: unimplemented regclassgenMove_X86: unimplemented regclassspill_off >= 0 && spill_off < 10000! sameHReg(i->Xin.Alu32R.dst, vreg)! sameHReg(i->Xin.CMov32.dst, vreg)i->Xin.Sh3232.op == Xsh_SHL || i->Xin.Sh3232.op == Xsh_SHRdisp_cp_chain_me_to_slowEP != NULLdisp_cp_chain_me_to_fastEP != NULLemit_X86Instr.Xin_XAssisted: unexpected jump kindi->Xin.CMov32.cond != Xcc_ALWAYSemitX86Instr(FpBinary,PREM/PREM1/SCALE)emitX86Instr(Xin_FpLdStI-load)emitX86Instr(Xin_FpLdStI-store)i->Xin.SseLdzLO.sz == 4 || i->Xin.SseLdzLO.sz == 8read_misaligned_UInt_LE(&p[1]) == (UInt)(Addr)disp_cp_chain_me_EXPECTED9)=-% 59)! 1;+# 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$D$$ũ14$t$(P‹EM R&OD$$肩L$$ $hPwY_1RL$Q뤍t&WU;u 4P‹ELY[jPP t&z蜩U;u 4u PVP‹EL]Xnt&W覬hPwPVj‹EK6t&N D$$zt$t$(jj‹EK&WW Ɖ*VPj‹EwK &E;u O4D$$ N D$$ҧt$t$(jvPhPPN D$$蒧t$$t$Pj‹EJ%WO ƍD$$yVt$(jjVP XWϧO ƍD$$/Vt$(jOD$$t$$hPwPVj‹E1JT$,D$(wR_;u E8+UD$( K‹EID$,J‹EI#jPP 'PD$Q^XD$PD$($ht$ Vt$4‹EgIOD$$t$$hPwlj7NWVjj‹E"ItT$4D$0w QOD$(蚥t$(Vjt$@WPj‹EHVj$t$0VhPwD$P Ƌt FT$4D$0wQt$8t$Pj‹ETHt$DVPj$‹E5HjVP PD$QY^D$PD$QXZD$jPP zjVP PD$Q_XD$jPP jPP DjPP X$PhPP$PhPPVRXZPh5PD$QY^D$APhPPjPP $PhIPP$PhZPP$PhQPP$PhJPP$Ph[>$PhhPPVRYXPD$QXZD$jVRXZPD$QXZD$ PD$Q_XD$PD$Q_XD$NPD$RY^D$W pVPj‹E?EP&t&UWVSt$HD$8|$4t$t$L $t$$x7F$;F T$ FD$0T$AF D$‰ՋT$ 9l$ /l$nl$ 9D$<$nFD$P~|$FM4$)11L w8HQPfu׹t$vdJt_ׁ&f8׹v׹v0PhPP8PhPP8PhPP8PhPPD$'l$PhhPt$WjPUNjFP;P <P$FV P [^_]Ít$PUPWP`PhnPP&17jWP tU: T$hPt$~XZT$B1;FRjWPNjFP;PWPXZt$PUPWPNjFP;PB<P$jWP D$(|$PymhPt$~Y]jPW NjFP;P&jWP WPXZPhNPPPhMPPPhPPhjPWJWP]X`Ph!PPD$hjWt$$advance4(x86,host)priv/host_generic_regs.hix <= 0xFFFFFenc == 0 priv/host_x86_isel.chregClass(src) == HRcVec128hregClass(dst) == HRcVec128hregClass(src) == HRcInt32hregClass(dst) == HRcInt32etmp < env->n_vregmape->Iex.Load.ty == Ity_I64is_sane_RetLoc(rloc)rloc.pri == RLPri_2IntaddToSp == 0iselInt64ExprhregClass(*rHi) == HRcInt32hregIsVirtual(*rHi)hregClass(*rLo) == HRcInt32hregIsVirtual(*rLo)ty == Ity_F64iselDblExpr(x86): conste->Iex.Load.ty == Ity_F64iselDblExpr_wrkhregClass(r) == HRcFlt64hregIsVirtual(r)ty == Ity_F32e->Iex.Load.ty == Ity_F32iselFltExpr_wrkty == e->Iex.CCall.rettyrloc.pri == RLPri_InthregClass(r) == HRcInt32ty == Ity_I32sane_AMode(am)sane_AMode(rm->Xrm.Mem.am)sane_AMode(rmi->Xrmi.Mem.am)nGSPTRs == 0 || nGSPTRs == 1retTy != Ity_V256nVECRETs == 00argreg >= 0argregX >= 0!hregIsInvalid(r_vecRetAddr)not_done_yet == 0*stackAdjustAfterCall == 0is_RetLoc_INVALID(*retloc)iselCondCode(x86): CmpXX16iselCondCode(x86): CmpXX32iselCondCode(x86): CmpXX64iselCondCodety == Ity_V128iselVecExpr_wrkhregClass(r) == HRcVec128 -- d->tmp == IRTemp_INVALIDrloc.pri == RLPri_Nonerloc.pri == RLPri_V128SpReladdToSp >= 16cas->expdHi == NULLcas->dataHi == NULLiselStmtarch_host == VexArchX86iselBB: IRTemp type -- PUT(%d) = ; exit-cdst->tag == Ico_U32rc >= HRcInt32 && rc <= HrcLASTn > 0 && n < 256 && (n%4) == 0sane_AMode: unknown x86 amode tagtypeOfIRExpr(env->type_env,e) == Ity_I64e->Iex.Const.con->tag == Ico_U64! hregIsInvalid(env->vregmapHI[tmp])e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U64vexGetAllocMode() == VexAllocModeTEMPcee->regparms >= 0 && cee->regparms <= 3ty == Ity_I32 || ty == Ity_I16 || ty == Ity_I8e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U8e->Iex.Unop.arg->Iex.Get.ty == Ity_I8e->Iex.Unop.arg->Iex.Get.ty == Ity_I16iselIntExpr_R: cannot reduce treeiselIntExpr_RMI.Iex_Const(x86h)hregClass(ri->Xri.Reg.reg) == HRcInt32hregIsVirtual(ri->Xri.Reg.reg)iselIntExpr_RI: unknown x86 RI taghregClass(rm->Xrm.Reg.reg) == HRcInt32hregIsVirtual(rm->Xrm.Reg.reg)iselIntExpr_RM: unknown x86 RM taggenGuestArrayOffset(x86 host)(1)genGuestArrayOffset(x86 host)(2)hregClass(rmi->Xrmi.Reg.reg) == HRcInt32hregIsVirtual(rmi->Xrmi.Reg.reg)iselIntExpr_RMI: unknown x86 RMI tagretTy == Ity_V128 || retTy == Ity_V256retTy != Ity_V128 && retTy != Ity_V256pushArg(x86): can't handle arg of this typetypeOfIRExpr(env->type_env, arg) == Ity_I32typeOfIRExpr(env->type_env,e) == Ity_I1e->Iex.Const.con->tag == Ico_U1e->Iex.Const.con->Ico.U1 == True || e->Iex.Const.con->Ico.U1 == FalseiselCondCode(x86): CmpXX8(expr,0:I8)iselCondCode(x86): CmpXX8(expr,expr)cal->Iex.CCall.retty == Ity_I32con->Iex.Const.con->tag == Ico_U32e->Iex.Const.con->tag == Ico_V128iselVecExpr (hwcaps = %s): can't reduce iselStmt(x86): Ist_Exit: dst is not a 32-bit value0 == (hwcaps_host & ~(VEX_HWCAPS_X86_MMXEXT | VEX_HWCAPS_X86_SSE1 | VEX_HWCAPS_X86_SSE2 | VEX_HWCAPS_X86_SSE3 | VEX_HWCAPS_X86_LZCNT))archinfo_host->endness == VexEndnessLEiselNextiselIntExpr_R_wrkiselIntExpr_RiselCondCode_wrkmk_iMOVsd_RRlookupIRTempiselIntExpr_AMode_wrkiselIntExpr_AModeadd_to_esplookupIRTemp64pushArgdoHelperCallmk_vMOVsd_RRiselVecExpr_wrkiselVecExpriselFltExpr_wrkiselFltExpriselDblExpr_wrkiselDblExpriselIntExpr_RM_wrkiselIntExpr_RMiselInt64Expr_wrkiselInt64ExpriselIntExpr_RMI_wrkiselIntExpr_RMIhregClassiselIntExpr_RI_wrkiselIntExpr_RIiselStmtmkHRegiselSB_X86$Ë4$ GNUzR| $0AL FP A G HD0AA Av  AAE G KAG F GKAG PjAA Na  AAE BALHC  AAD AEFAX CD qABH A AK G KAGF G KAGF GKAG\@CF qFABH A AC G KAGF G KAGF GKAG(GCa D G KAG(GCa D G KAG( GCa D G KAG$pAA FCN K$B(B,K h$B(B,K h$D(B,K b CA AAE B$A(L,H K$A(L,H E AA AAH B$A(L,H J$E(F$A L$E(F$A T$E(F$A pAA FXJAB Ka  AAE AAFAN KAG F BALHA AAXAA ACNEB J$H(HjFa HA AAO BA L$HKA L$HJA FAHE FA`AC NAJAB Ka  AAB BALHC  AAD AEFA@P.AA ACNH B$T(D,B0B4Ki D$B(B,He HA AAJ B A$L(HO A$L(HQ A$F AM E$F A@AA w AF ` AO G KAGF i@ _&AA AANTTXD\FXAT} XL\F XB\J`AdLhDlXpEtBxHTKXJ\A`BdShJlApBtHT| AA AAD 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p0 == 3p - p0 == 5p - p0 == 8!(*is_profInc)emit_AMD64Instrp - &buf[0] <= 64endness_host == VexEndnessLEp[0] == 0x49p[1] == 0xBBp[10] == 0x41p[11] == 0xFFp[12] == 0xD3validsizeof(ULong*) == 8%eax%ecx%edx%ebx%esp%ebp%esi%edi%r8d%r9d%r10d%r11d%r12d%r13d%r14d%r15d%rax%rcx%rdx%rbx%rsp%rbp%rsi%rdi%r8%r9%r10%r11%r12%r13%r14%r15rc >= HRcInt32 && rc <= HrcLASTppHRegAMD64_lo32: invalid regclassdoAMode_M: can't emit amode IRdoAMode_M: can't emit amode IRRSregparms >= 0 && regparms <= 6cond != Acc_ALWAYS && (szB == 4 || szB == 8)szSmall == 1 || szSmall == 2 || szSmall == 4sz == 8 || sz == 4 || sz == 2 || sz == 1sz == 4 || sz == 8 || sz == 16movabsq $disp_cp_chain_me_to_%sEP,%%r11; call *%%r11 }; movabsq $disp_indir,%%r11; jmp *%%r11 }; movl $IRJumpKind_to_TRCVAL(%d),%%rbp; movabsq $disp_assisted,%%r11; jmp *%%r11 }lock cmpxchg%db {%%rdx:%%rax->%%rcx:%%rbx},(profInc) movabsq $NotKnownYet, %%r11; incq (%%r11)getRegUsage_AMD64Instr:Call:regparmsi->Ain.Sse32Fx4.op != Asse_MOVi->Ain.Sse32FLo.op != Asse_MOVi->Ain.Sse64Fx2.op != Asse_MOVi->Ain.Sse64FLo.op != Asse_MOVgenSpill_AMD64: unimplemented regclassgenReload_AMD64: unimplemented regclassgenMove_AMD64: unimplemented regclassspill_off >= 0 && spill_off < 10000! sameHReg(i->Ain.Alu64R.dst, vreg)disp_cp_chain_me_to_slowEP != NULLdisp_cp_chain_me_to_fastEP != NULLemit_AMD64Instr.Ain_XAssisted: unexpected jump kindi->Ain.CMov64.cond != Acc_ALWAYSi->Ain.CLoad.cond != Acc_ALWAYSi->Ain.CLoad.szB == 4 || i->Ain.CLoad.szB == 8i->Ain.CStore.cond != Acc_ALWAYSi->Ain.CStore.szB == 4 || i->Ain.CStore.szB == 8i->Ain.A87Free.nregs > 0 && i->Ain.A87Free.nregs <= 7i->Ain.A87PushPop.szB == 8 || i->Ain.A87PushPop.szB == 4(gregEnc3210|eregEnc3210) < 16i->Ain.SseCStore.cond != Acc_ALWAYSi->Ain.SseCLoad.cond != Acc_ALWAYSi->Ain.SseLdzLO.sz == 4 || i->Ain.SseLdzLO.sz == 8read_misaligned_ULong_LE(&p[2]) == (Addr)disp_cp_chain_me_EXPECTED9)! 1;+# 3patchProfInc_AMD64unchainXDirect_AMD64chainXDirect_AMD64doAMode_M_encrexAMode_M_encdoAMode_R_enc_encvregEnc3210iregEnc3210rexAMode_R_enc_encdoAMode_R_enc_regiregEnc210iregEnc3mkSIBrexAMode_M__wrkdo_ffree_stemit_AMD64InstrdirectReload_AMD64genReload_AMD64genSpill_AMD64mapRegs_AMD64InstrgetRegUsage_AMD64InstrppAMD64InstrAMD64Instr_SseMOVQAMD64Instr_SseShufAMD64Instr_SseCMovAMD64Instr_Sse64FLoAMD64Instr_Sse64Fx2AMD64Instr_Sse32FLoAMD64Instr_Sse32Fx4AMD64Instr_SseLdzLOAMD64Instr_SseCLoadAMD64Instr_SseCStoreAMD64Instr_SseLdStAMD64Instr_SseSF2SIAMD64Instr_SseSI2SFAMD64Instr_SseUComISAMD64Instr_A87PushPopAMD64Instr_A87FreeAMD64Instr_DACASAMD64Instr_ACASAMD64Instr_StoreAMD64Instr_LoadEXAMD64Instr_CStoreAMD64Instr_CLoadAMD64Instr_CMov64AMD64Instr_CallAMD64Instr_DivAMD64Instr_Alu32RAMD64Instr_Alu64MppHRegAMD64_lo32AMD64AMode_IRRShregClassppHRegAMD64# ( - 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j0VP‹E MjVPj(‹E MVjhp P‹E uMVjh` P ‹E UMVj h P‹E 8Mh` jPt$Djj(‹E Mh jPt$|$D$8@9AD$8{}$dPhhPPpqL$ ZYL$=t= }D$8 mpqL$ ZYL$P=}$= 5D$8 %pqL$ ZYL$}$VD$$D$JuL$$D$L$D$+ED$$D$D$Et$$jVL$Q‹E B|$@C‹E BVj@j7‹E BVWj$‹E B$0D$0QD$@9AuD$8eD$@9A&vUWVS(|$<$T$W1Y]=,==u#G=qw.=ok=@WPv=uOl$KT$H0$O KT$HD$evl$V$T$BD$T$D$ BD$WD$GD$tO D$KL$PZq) AN Q;Q9QESt$1|$@PN Q;Q9QET$ gAN Q;Q9QET$  5AN Q;Q>1QE$t$0D$t$ 0$HED$H ([^_]Ðl$V$T$>AD$T$D$ +AD$W D$GD$rT$$D$D$ wD$$ >@N _Q;Q9QEsD$$ @N Q;Q9QEt$1j|$qPN Q;Q,PD$QXZD$!HPhPPPhPPPh PPG;F *V:SNt$4$t&Ph PP&fjPP Ot&PhPPjPP qt&jPP !t&jPP t&jPP Ct&jPP t&Ph PPPh PPPh PPPh PPPD$Q]XD$G&vPD$QY_D$&vPD$QXZD$g&vPD$QY_D$PhPPvPD$QXZD$PhPPvUWVSL|$xD$h|$d|$ |$||$8|$D$x>G(;G$T$T$G D$`L$$@G D$9c؉O9T$D$ t$_OL$GwG $|$1҉ً$1<$4d>t&dֻ|$49D$u|$W$hP t$thP $PVƋG P;P4PD$~ |$ t$`D$V 1L$L$`Q ƒ $$ $D$- >t&`ֻCZt>ց Ztցt&PhPPPhQPPPhRPPPh_PPVP&$H9QL$RP\$D$$S \$4YvL$D$(؋IjL$T$4؋IT$,jL$T$4؋IT$0jL$T$4؋IT$jT$4\$O GT$9T$S9 D$L$= $T$D$ 8W J;JJL$T$D$N8W J;JJL$D$  8W J;J$JL$YD$ 7W J;J=JL$D$$ 7W J;JJL$D$(0 z7W J;JJL$4$t$$W [[J;J]JL$'t$h jW J;JJL$t$h jW J;JJL$tjPP D$ƒL$`9q D$`@$D$`pHtHL$4$PL$QL$PVPL$ 9   >D$,>L$,P}SɉL$&hP t$VjPL$QƋG P;P4PD$ G W$P L[^_]ÍL$4$PL$ QPVPtPh6PP&$@86$S|D$hP \$s\$D$YC Z=|-4>$pD$0fD$p t$t$t$<G P;P}~ PD$ƒjQPD$ ƒu4$Pv$xuۉG P;P|QL$PXZ $v$@D$@ eP7XZw=oL$T$DD$@D$@D$DD$HqSL$ L$QL$qԈT$TD$X_& PhPP&$@8D$p7ZY=5 =TD$PoL$ÍD$,ITD$L$,P $ySL$QP‹G 71F$H9L$CA1Q \$ 4o\$$D$,KcD$,SO;W  ʉL$1W J;JgJL$ D$Pxt$t$T$RPG P;P8$p7D$D$p 7Ë$xB|$4X    $D$,IbT$,RT$jT$D$RjL$T$TD$D$Pq %t$t$\jj$‹G W/t$ t$Djj‹G n_vregmap hregClass(src) == HRcVec128hregClass(dst) == HRcVec128hregClass(src) == HRcInt64hregClass(dst) == HRcInt640!preShift32Rc->tag == Ico_U8ty == e->Iex.CCall.rettyis_sane_RetLoc(rloc)rloc.pri == RLPri_IntaddToSp == 0hregClass(r) == HRcInt64hregIsVirtual(r)sane_AMode(rm->Arm.Mem.am)-10000 < bias && bias < 10000elemSz == 1 || elemSz == 8ty == Ity_I64sane_AMode(am)sane_AMode(rmi->Armi.Mem.am)eiselCondCode(amd64): CmpXX16iselCondCode(amd64): CmpXX64iselCondCode(amd64): CmpXX32iselCondCode(amd64)e->tag != Iex_VECRETe->Iex.Get.ty == Ity_I64!hregIsInvalid(r_vecRetAddr)nVECRETs == 1nVECRETs == 0nGSPTRs == 0 || nGSPTRs == 1*stackAdjustAfterCall == 0is_RetLoc_INVALID(*retloc)ty == Ity_F32e->Iex.Load.ty == Ity_F32hregClass(r) == HRcVec128iselFltExpr_wrkty == Ity_F64iselDblExpr(amd64): conste->Iex.Load.ty == Ity_F64iselDblExpr_wrkty == Ity_V128iselVecExpr_wrkty == Ity_V256iselDVecExpr_wrkhregClass(*rHi) == HRcVec128hregClass(*rLo) == HRcVec128hregIsVirtual(*rHi)hregIsVirtual(*rLo)iselInt128ExprhregClass(*rHi) == HRcInt64hregClass(*rLo) == HRcInt64arch_host == VexArchAMD64iselBB(amd64): IRTemp type -- d->tmp == IRTemp_INVALIDrloc.pri == RLPri_Nonerloc.pri == RLPri_V128SpReladdToSp >= 16rloc.pri == RLPri_V256SpReladdToSp >= 32cas->expdHi == NULLcas->dataHi == NULLiselStmt(amd64) -- PUT(%d) = ; exit-cdst->tag == Ico_U64rc >= HRcInt32 && rc <= HrcLASTn > 0 && n < 256 && (n%8) == 0sane_AMode: unknown amd64 amode tage->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U8typeOfIRExpr(env->type_env, arg1) == Ity_I64typeOfIRExpr(env->type_env, arg2) == Ity_I64typeOfIRExpr(env->type_env, arg2) == Ity_I8vexGetAllocMode() == VexAllocModeTEMPiselIntExpr_R(amd64): cannot reduce treety == Ity_I64 || ty == Ity_I32 || ty == Ity_I16 || ty == Ity_I8hregClass(rm->Arm.Reg.reg) == HRcInt64hregIsVirtual(rm->Arm.Reg.reg)iselIntExpr_RM: unknown amd64 RM tagiselIntExpr_RMI.Iex_Const(amd64)hregClass(ri->Ari.Reg.reg) == HRcInt64hregIsVirtual(ri->Ari.Reg.reg)iselIntExpr_RI: unknown amd64 RI taggenGuestArrayOffset(amd64 host)hregClass(rmi->Armi.Reg.reg) == HRcInt64hregIsVirtual(rmi->Armi.Reg.reg)iselIntExpr_RMI: unknown amd64 RMI tagtypeOfIRExpr(env->type_env,e) == Ity_I1e->Iex.Const.con->tag == Ico_U1e->Iex.Const.con->Ico.U1 == True || e->Iex.Const.con->Ico.U1 == FalseiselCondCode(amd64): CmpXX8(expr,0:I8)iselCondCode(amd64): CmpXX8(expr,expr)cal->Iex.CCall.retty == Ity_I64con->Iex.Const.con->tag == Ico_U64doHelperCall(AMD64): cannot currently handle > 6 argstypeOfIRExpr(env->type_env, args[i]) == Ity_I64typeOfIRExpr(env->type_env, e) == Ity_I64e->Iex.Const.con->tag == Ico_U64typeOfIRExpr(env->type_env,e->Iex.ITE.cond) == Ity_I1e->Iex.Const.con->tag == Ico_V128iselVecExpr (amd64, subarch = %s): can't reduce ! hregIsInvalid(env->vregmapHI[tmp])e->Iex.Const.con->tag == Ico_V256iselDVecExpr (amd64, subarch = %s): can't reduce typeOfIRExpr(env->type_env,e) == Ity_I1280 == (hwcaps_host & ~(VEX_HWCAPS_AMD64_SSE3 | VEX_HWCAPS_AMD64_SSSE3 | VEX_HWCAPS_AMD64_CX16 | VEX_HWCAPS_AMD64_LZCNT | VEX_HWCAPS_AMD64_AVX | VEX_HWCAPS_AMD64_RDTSCP | VEX_HWCAPS_AMD64_BMI | VEX_HWCAPS_AMD64_AVX2 | VEX_HWCAPS_AMD64_F16C | VEX_HWCAPS_AMD64_RDRAND))archinfo_host->endness == VexEndnessLEiselStmt(amd64): Ist_Exit: dst is not a 64-bit value!"#$%&'()*+,-./0123EFGEFGiselNextiselIntExpr_R_wrkiselIntExpr_RiselCondCode_wrkmk_iMOVsd_RRlookupIRTempiselIntExpr_AMode_wrkiselIntExpr_AModeadd_to_rsplookupIRTempPairiselIntExpr_single_instructiondoHelperCallmk_vMOVsd_RRiselDVecExpr_wrkiselDVecExpriselVecExpr_wrkiselVecExpriselFltExpr_wrkiselFltExpriselDblExpr_wrkiselDblExpriselIntExpr_RM_wrkiselIntExpr_RMiselInt128Expr_wrkiselInt128ExpriselIntExpr_RMI_wrkiselIntExpr_RMIhregClassiselIntExpr_RI_wrkiselIntExpr_RIgenGuestArrayOffsetiselStmtmkHRegiselSB_AMD64$Ë4$Ë,$ GNUzR| HAA Av  AAE G KAG F GKAG h+AR KAGPjAA Na  AAE BALHC  AAD AEFAX CD qABH A AK G KAGF G KAGF GKAG\<CF qFABH A AC G KAGF G KAGF GKAG(GCa D G KAG(GCa D G KAG 6AA AFN$U(A,B0K$n(D,B0H$k AA AAK F(A,L0H$O(A,L0H$F AA AAG A(E,F(A$X(A,F(A$`AA ACNEB J$H(A,B0HjK\ AA AAC BA L$HC AA AAB BA L$HJA FAHE FA`0`AC NAJAB Ka  AAB BALHC  AAD AEFApAA FXJAB Ka  AAE AAFAN KAG F BALHA AAAA ACNEB J$H(HjFa HA AAO BA L$HKA L$HJA FAHE FA@AA w AF ` AO G KAGF ipAA CAN[A B$Kc CA AAJ BA L$HG AA AAF G K A$G(N AE FAXP kAE DCN[ E$A(Hk F$F F_ AA AAD B A$L(HC AA AAJ E A$L(HO F$I Cd  A$H D A$F AM A$F AH A$F A  (AC ACNPDTBXFTAP|TAXG\D`PP\ TKXA\G`F eTCXFTFP\ TAXB\A`L IT`P\TJXA\B`VPH AA AAD |TBXQ\KPiTDXB\B`QdBhAlPpDtBxB|HPLTBXA\VPZTPPATPXJ\A`BdThFlApBtMP TBXO OTAXE\HPWTAXA\HPWTAXA\HPTAXB\VPH AA AAI TTAXB\B`OPC TCXFTAPeTHXA\M O TKXA\G`N wTAXA\ZP TLXE FTIXK\B`wdAhBlBpHPOTAXB\B`EPF TIXK\B`wdAhBlBpHPKTE [TAXP\B`BdPhBlBpHPoTAX\TAPPTRPPTRP] TAXB\J ]TAXB\P`AdBh^Pv TDXA\J QTFXA\B`VPATBXP\F`AdBhPPzTBXP\F`AdBhPlBpBtHPe TAXB\c`BdPhFlApBtHPKTBXB\J c TDXB\J | TDXB\Q`FdAhBlPpHPATAXB\J xTBXQPLTGXd\B`BdAhAlBpHPLTIXiTAPJ TF BTAXL\HPXTGXF\E`EdFhElGpNPv TAXB\B`E ATAXB\RPkTAXD\RPFTBXB\P`BdBhRPC TBXB\P`BdB A TAXB\E ETFXA\B`RPJ TD xTKPvTDXA\RPwTBXB\Q`AdEhVP|TGXh\B`BdAhAlBpHPLTIXL\D`BdVPc TCXC\O F TCXF\F`AdBhH nTEXB\RP`TGXF\E`FdEhGlSPiTGXF\E`EdFhElGpNPV TFXA\B`K TAXD\VPh TDXB\B`K A TJXA\B`J a TAXE G TKXA\G`E G TKXA\G`E G TKXA\G`E ATEXFTAPPTEXG\G`EPG TEXB G TEXB ^TGXa\B`DdRPTAXB\S`AdBhSlApAtHPNTAXA\S`JdAhBlVPYTEXG\G`NPd TDXA\J NTBXB\Q`AdAhRPK TBXJ\B`JdBhFlFpBtBxHPLTIXS\J`AdBhQlIpRPATJXA\B`YdBhBlApAtBxHPLTIXP h TGXO\B`FdEhBlBpHPKTEXB\B`J O TEXE h TKXA\G`E iTCXFTAPLTCXFTAPuTAXD\Q`AdEhRPWTAXD\Q`AdDhRPxTGXFTAPWTCXFTAPSTAXE\VPO TAXH\P`EdAhQlApEtJ  TIXb\I`bdBhBlApAtBxHPLTIXR TAXB\RPl TEXB\X`AdAhJ sTIXZ\B`iPTTBXB\S`BdDhPlApBtHPOTAXB\P`BdBhelJpAtBxHP[ TEXE ]TFXA\B`PdAhBlVP TBXB\P`AdBhPlJ TBXB\T`JdAhBlPpHPATAXB\JP TBXB\T`E GTEXD\B`]PBTEXD\B`QdFhAlBpHP[ TKXA\G`E GTEXG\G`EPA TAXA\Q`AdI G TKXA\G`E G TGXFTAPTTCXFTAPdTFXA\B`PdAhBlApBtBxHPqTBXB\P`JdAhBlPpBtBxHPKTFXA\B`J G TEXE GTEXG\G`EPG TEXE G TEXE A TLXK\A`GdE G TKXA\G`E H TAXD\Q`AdE G TEXE G TEXE ATBXB\P`BdBhRPL<3AL e AE I KAGL I KAGL IKAG04AC CNABHVHb C AAK g KA G$F G KA G$F G KA G$F G KA G$F G KA G$F ECF HQ KA G$F G KA G$E GXL6AE ACN$G(B,X$l(F,A0B4K$g(B,B0K$k(F,A0B4K$g(I,A0B4K$g(F$g AA AAD B(A,L0H$K(A,L0H$C AA AAJ B(A,L0H$K(A,L0H$K(A,L0H$K(A,L0H$P (K,A0G4F G (K,A0G4F G (K,A0G4F A(E,F(A$T(E,F(A$T(E,F(A$T(E,F(A$T(A,F(A$H(E,F(A$9AC CNABFA|FG KA G$E PFM A AAJ PFQ KA G$F CFN KA G$F G KA G$F G KA G$F G KA G$E G E G h;AC CCN(G,N(,I0A4B8K(c,I0A4B8K(|,D0E4F8HAA AAK(B,A0L4L(W,A0L4L(W,A0L4H(P ,K0A4G8F G ,K0A4G8F G ,K0A4G8F G ,K0A4G8F A,E0F,A(T,E0F,A(P ,K G ,K0A4G8N A,E0F,A( x>IAA CCN4A8BIj IV{m`` @  F04  ' @6V9eh ~T x    8 $ # <D  U$ n0bw ~         d -x  F _ x    t       >x N#("*(O.dK4O:P@1yG]NUD\cAjqv{'0G\ ^z @ H 0  d    = V t g! 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mtctr r10 ; bctrl [r%d] }(xDirect) if (%s) { imm64 r30,0x%llx; std r30,imm32 r30,0x%llx; stw r30,; mtctr r30; bctrl }(xIndir) imm%s r30,$disp_cp_xindir; mtctr r30; bctr }(xAssisted) cmov (%s) : }l%c%s%s l%carx ,%%r0,st%c%s st%ccx. ; xori ,1mfcr mfence (=sync)lf%c%s stf%c%s stfiwz ,0(frsp fpcmov (%s) if (fr_dst != fr_src) { fmr mtfsf 0xFF,,0, %sfcmpo %%cr1,; mfcr ; rlwinm ,8,28,31 ; lv%sx stv%sx %%r30%s(b) %s(h) %s(w) vperm vsel lvsl lvsr vsldoi ,%dvsplt%s%c , %davcmov (%s) if (v_dst != v_src) { vmr mtvscr drintx drintxq dquaq dxexq diexq dcmpo %%cr1,dcmpoq %%cr1,(evCheck) lwz r30,; addic. r30,r30,-1; ; bge nofail; lwz r30,; mtctr r30; bctr; nofail: ppPPCInstr: No such tag(%d) ppPPCInstrset (%s),: { mfcr r0 ; rlwinm ,r0,%u,31,31: { li ,1 }addRegUsage_PPCRHaddRegUsage_PPCAModeaddRegUsage_PPCRIaddRegUsage_PPCVI5sgetRegUsage_PPCInstrmapRegs_PPCRHmapRegs_PPCAModemapRegs_PPCRImapRegs_PPCVI5smapRegs_PPCInstr!hregIsVirtual(rreg)!mode64nbuf >= 32srcR->Prh.Imm.synedsrcR->Prh.Imm.imm16 != 0x8000!srcR->Prh.Imm.synedsz32n > 0 && n < 32n > 0 && n < 64n >= 0 && n < 32syned == srcR->Prh.Imm.synedimm_srcR != 0x8000!i->Pin.MulL.syneddelta >= 16 && delta <= 32disp_cp_xindir != NULLr_src < 0x20delta >= 8 && delta <= 24cond.flag != Pcf_NONEcc.test != Pct_ALWAYSfreg < 0x20shift <= 0xF!(*is_profInc) => emit_PPCInstrp - &buf[0] <= 64endness_host == VexEndnessBE0 == (3 & (HWord)p)len == (mode64 ? 28 : 16)len == 20len == 8%r0%r1%r2%r3%r4%r5%r6%r7%r8%r9%r10%r11%r12%r13%r14%r15%r16%r17%r18%r19%r20%r21%r22%r23%r24%r25%r26%r27%r28%r29%r30%r31rc >= HRcInt32 && rc <= HrcLASThregClass(r) == (mode64 ? HRcInt64 : HRcInt32)idx >= -0x8000 && idx < 0x8000syned == True || syned == False(Long)imm64 == (Long)(Int)(UInt)imm64sz == 1 || sz == 2 || sz == 4 || sz == 8imm64-fixed5 r30,$disp_cp_chain_me_to_%sEP; imm32-fixed2 r30,$disp_cp_chain_me_to_%sEP; li r31,$IRJumpKind_to_TRCVAL(%d); (profInc) imm64-fixed5 r30,$NotKnownYet; ld r29,(r30); addi r29,r29,1; std r29,(r30)(profInc) imm32-fixed2 r30,$NotKnownYet; lwz r29,4(r30); addic. r29,r29,1; stw r29,4(r30)lwz r29,0(r30); addze r29,r29; stw r29,0(r30)0 == (argir & ~((1<<3)|(1<<4)|(1<<5)|(1<<6) |(1<<7)|(1<<8)|(1<<9)|(1<<10)))genSpill_PPC: unimplemented regclassgenReload_PPC: unimplemented regclassgenMove_PPC: unimplemented regclassdisp_cp_chain_me_to_slowEP != NULLdisp_cp_chain_me_to_fastEP != NULLi->Pin.XDirect.cond.flag != Pcf_NONEi->Pin.XDirect.cond.flag == Pcf_NONE0 == (((ULong)i->Pin.XDirect.dstGA) >> 32)delta >= 16 && delta <= 64 && 0 == (delta & 3)i->Pin.XIndir.cond.flag != Pcf_NONEi->Pin.XIndir.cond.flag == Pcf_NONEdelta >= 16 && delta <= 32 && 0 == (delta & 3)i->Pin.XAssisted.cond.flag != Pcf_NONEi->Pin.XAssisted.cond.flag == Pcf_NONEemit_ARMInstr.Pin_XAssisted: unexpected jump kindi->Pin.CMov.cond.test != Pct_ALWAYS0 == (am_addr->Pam.IR.index & 3)sz == 1 || sz == 2 || sz == 4 || sz == 16sz == 8 || sz == 16 || sz == 32hregClass(i->Pin.AvSplat.src->Pvi.Reg) == HRcVec128ERROR: emit_PPCInstr default case Error: emit_PPCInstr case Pin_DfpExtractExp, case inst Default Error: emit_PPCInstr case Pin_Dfp128Unary, case inst Default ERROR: emit_PPCInstr quad default case %d Pin_DfpQuantize128: default case, couldn't find inst to issue evCheckSzB_PPC() == (UChar*)p - (UChar*)p0(endness_host == VexEndnessBE) || (endness_host == VexEndnessLE)isLoadImm_EXACTLY2or5(p, 30, (Addr)disp_cp_chain_me_EXPECTED, mode64, endness_host)fetch32(p + (mode64 ? 20 : 8) + 0, endness_host) == 0x7FC903A6fetch32(p + (mode64 ? 20 : 8) + 4, endness_host) == 0x4E800421isLoadImm_EXACTLY2or5(p, 30, (Addr)place_to_jump_to_EXPECTED, mode64, endness_host)fetch32(p + (mode64 ? 20 : 8) + 4, endness_host) == 0x4E800420isLoadImm_EXACTLY2or5(p, 30, 0x6555655565556555ULL, True , endness_host)fetch32(p + 20, endness_host) == 0xEBBE0000fetch32(p + 24, endness_host) == 0x3BBD0001fetch32(p + 28, endness_host) == 0xFBBE0000isLoadImm_EXACTLY2or5(p, 30, 0x65556555ULL, False , endness_host)fetch32(p + 8, endness_host) == 0x83BE0004fetch32(p + 12, endness_host) == 0x37BD0001fetch32(p + 16, endness_host) == 0x93BE0004fetch32(p + 20, endness_host) == 0x83BE0000fetch32(p + 24, endness_host) == 0x7FBD0194fetch32(p + 28, endness_host) == 0x93BE0000 J J J HIpatchProfInc_PPCunchainXDirect_PPCchainXDirect_PPCmkFormXFXdo_load_or_store_machine_worddo_load_or_store_word32mkFormMmkFormXfregEnciregEncmkFormZ23mkFormZ22mkFormVXvregEncmkFormBmkFormVAmkFormVXImkLoadImmmkFormVXRmkFormVSXRNDmkFormVX_BX_TXmkFormXFLdoAMode_IRdoAMode_RRmkFormAmkFormVXR0mkFormDmkMoveRegmkFormXOmkFormXSmkFormMDemit_PPCInstrgenReload_PPCgenSpill_PPCgetRegUsage_PPCInstrPPCInstr_AvCMovPPCInstr_FpCMovPPCInstr_FpCftIPPCInstr_FpLdStPPCInstr_StoreCPPCInstr_StorePPCInstr_LoadLPPCInstr_LoadPPCInstr_CMovPPCInstr_CallPPCInstr_MulLPPCInstr_LIPPCVI5s_RegPPCVI5s_ImmPPCRH_ImmPPCAMode_IRinvertCondTestmk_PPCCondCodehregClassppHRegPPC !&+05:?DINS$Ë$Ë4$Ë<$Ë,$ GNUzR| t/AA A|  AAG G KAG N G KAG F G KAG F G KAG F GKAG @0AL y AI I KAGL IKAGhAA AZ  AAA G KAG F G KAG F G KAG F GKAG @DAA F AG G KAGF GKAGP@AA T AI G KAGF G KAGF GKAG@AA AM  AAF G KAG E GX AL Dj  AAC I KAG L I KAG L IKAG h|AA Ah  AAC G KAG F G KAG F G KAG F GKAG XAA AY  AAB G KAG F G KAG F GKAG `D@AA LAQ A AAE I KA G$L I KA G$L IKA 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L$#T$0%T$*!$t$Vt$t$PT$RƋG0P;PY4PEbG0W4P 8[^_]Ít$Pt$PVP<PhGPPvAG4,%@D$GD$9|$%*!Pt$$YXW,G($L$QI9Ћ$Pt$t$VQRƋG0P;PVPXZt$Pt$PVPƋG0P;P4PE]GPVP >GPVP D$,t$ L$t$0%*!$t$$YZtLt$ t$ PVƋG0P;Pt&GPVP ht$t$PVƋG0P;PBt&VPY]>VPXZ<PhPPT$R91D$,t$ L$ ht$t$Vt$@priv/host_generic_regs.hix <= 0xFFFFFenc == 0priv/host_ppc_isel.c!env->mode64tmp < env->n_vregmap n <= 1024 && (n%16) == 0env->mode64hregClass(r_src) == HRcInt64eadvance4(ppc,host)ty == e->Iex.CCall.rettyis_sane_RetLoc(rloc)rloc.pri == RLPri_2IntaddToSp == 0env->mode64 == FalseiselInt64Expr(ppc)hregClass(*rHi) == HRcInt32hregIsVirtual(*rHi)hregClass(*rLo) == HRcInt32hregIsVirtual(*rLo)hregIsVirtual(*rMedHi)hregIsVirtual(*rMedLo)doHelperCall(PPC): invalid IRargreg < PPC_N_REGPARMSarg->tag != Iex_VECRETargreg < PPC_N_REGPARMS-10n_args >= 0 && n_args <= 8!hregIsInvalid(r_vecRetAddr)nVECRETs == 1nVECRETs == 0nGSPTRs == 0 || nGSPTRs == 1*stackAdjustAfterCall == 0is_RetLoc_INVALID(*retloc)ty == Ity_I8!ri->Prh.Imm.synedmode64rloc.pri == RLPri_IntiselIntExpr_R.const(ppc)hregIsVirtual(r)ty == Ity_I64ty == Ity_I32sane_AMode(env, am)iselInt128Expr(ppc64)hregIsVirtual(ri->Pri.Reg)hregClass(vSrc) == HRcVec128ri->Prh.Imm.syned == synedri->Prh.Imm.imm16 != 0x8000iselCondCode(ppc): CmpXX32iselCondCode(ppc): CmpXX64iselCondCode(ppc)ty == Ity_F128hregClass(r) == HRcVec128iselFp128Expr(ppc64)ty == Ity_F64iselDblExpr(ppc): conste->Iex.Load.ty == Ity_F64hregClass(r) == HRcFlt64iselDblExpr_wrk(ppc)ty == Ity_D64e->Iex.Load.ty == Ity_D64shift->tag == Pri_ImmiselDfp64Expr_wrk(ppc)iselDfp128Expr(ppc64)ty == Ity_D32e->Iex.Load.ty == Ity_D32iselDfp32Expr_wrk(ppc)ty == Ity_F32e->Iex.Load.ty == Ity_F32iselFltExpr_wrk(ppc)ty == Ity_V128e->Iex.Load.ty == Ity_V128iselVecExpr_wrk(ppc) -- tyRes == Ity_I1d->tmp == IRTemp_INVALIDrloc.pri == RLPri_Nonerloc.pri == RLPri_V128SpReladdToSp >= 16iselStmt(ppc)(hwcaps_host & mask32) == 0(hwcaps_host & mask64) == 0iselBB(ppc): IRTemp type -- PUT(%d) = ; exit-! hregIsInvalid(env->vregmapMedLo[tmp])rc >= HRcInt32 && rc <= HrcLASThregClass(r_dst) == hregClass(r_src)hregClass(r_src) == HRcInt32 || hregClass(r_src) == HRcInt64hregClass(r_srcHi) == HRcInt32hregClass(r_srcLo) == HRcInt32typeOfIRExpr(env->type_env,e) == Ity_I64e->Iex.Const.con->tag == Ico_U64!(ty == Ity_I32 || (mode64 && ty == Ity_I64))iselInt64Expr(ppc): No such tag(%u) typeOfIRExpr(env->type_env,e) == Ity_I128iselInt128Expr_to_32x4_wrk: Binop case 0x%x not found iselInt128Expr_to_32x4_wrk: e->tag 0x%x not found hregClass(*rMedHi) == HRcInt32hregClass(*rMedLo) == HRcInt32doHelperCall(PPC): cannot currently handle > 8 argsty == Ity_I32 || ty == Ity_I64ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32 || ((ty == Ity_I64) && mode64)ri->Prh.Imm.imm16 >= 1 && ri->Prh.Imm.imm16 <= 31hregClass(ri->Prh.Reg.reg) == HRcGPR(env->mode64)hregIsVirtual(ri->Prh.Reg.reg)iselIntExpr_RH5u: unknown ppc RI tagri->Prh.Imm.imm16 >= 1 && ri->Prh.Imm.imm16 <= 63iselIntExpr_RH6u: unknown ppc64 RI tagvexGetAllocMode() == VexAllocModeTEMPiselIntExpr_R(ppc): cannot reduce treehregClass(r) == HRcGPR(env->mode64)sane_AMode: unknown ppc amode taggenGuestArrayOffset(ppc host)(1)genGuestArrayOffset(ppc host)(2)genGuestArrayOffset(ppc host)(3)genGuestArrayOffset(ppc host)(4)typeOfIRExpr(env->type_env,mode) == Ity_I32typeOfIRExpr(env->type_env, env->previous_rm) == Ity_I32hregClass(r_rmIR) == HRcGPR(env->mode64)iselInt128Expr(ppc64): No such tag(%u) hregClass(*rHi) == HRcGPR(env->mode64)hregClass(*rLo) == HRcGPR(env->mode64)ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32 || ((ty == Ity_I64) && env->mode64)iselIntExpr_RI.Iex_Const(ppch)hregClass(ri->Pri.Reg) == HRcGPR(env->mode64)iselIntExpr_RI: unknown ppc RI tagty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32iselIntExpr_RH.Iex_Const(ppch)iselIntExpr_RH: unknown ppc RH tagtypeOfIRExpr(env->type_env,e) == Ity_I1iselCondCode(ppc): No such tag(%u) mode->Iex.Const.con->tag == Ico_U32mode->Iex.Const.con->Ico.U32 == 0x8iselDblExpr(ppc): No such tag(%u) ERROR: iselDfp64Expr_wrk, UNKNOWN unop case %d typeOfIRExpr(env->type_env,e) == Ity_D128ERROR: iselDfp128Expr_wrk, UNKNOWN binop case %d iselFltExpr(ppc): No such tag(%u) e->Iex.Const.con->tag == Ico_V128iselVecExpr(ppc) (subarch = %s): can't reduce iselStmt(ppc): Ist_Exit: dst is not a 32-bit valueiselStmt(ppc64): Ist_Exit: dst is not a 64-bit valuearch_host == VexArchPPC32 || arch_host == VexArchPPC64(archinfo_host->endness == VexEndnessBE) || (archinfo_host->endness == VexEndnessLE)cdst->tag == (env->mode64 ? Ico_U64 :Ico_U32)iselNextiselWordExpr_RH6u_wrkiselWordExpr_RH6uiselWordExpr_RH5u_wrkiselWordExpr_RH5uiselWordExpr_R_wrkiselWordExpr_RiselWordExpr_RH_wrkiselWordExpr_RHiselCondCode_wrkadd_to_splookupIRTempmk_iMOVds_RRlookupIRTempPairdoHelperCalliselDfp128Expr_wrkiselDfp128ExpriselDfp64Expr_wrkiselDfp64Exprmk_AvDuplicateRIisNaniselVecExpr_wrkiselVecExpriselWordExpr_RI_wrkiselWordExpr_RIiselFp128Expr_wrkiselFp128ExpriselDfp32Expr_wrkiselDfp32ExpriselFltExpr_wrkiselFltExprFPU_rounding_mode_isOddiselDblExpr_wrkiselDblExprlookupIRTempQuadiselInt128Expr_to_32x4_wrkiselInt128Expr_to_32x4iselInt128Expr_wrkiselInt128Exprmk_LoadRR32toFPRmk_LoadR64toFPRroundModeIRtoPPC_set_FPU_rounding_modeiselInt64Expr_wrkiselInt64ExprhregClassiselWordExpr_AMode_wrkiselWordExpr_AModeiselStmtmkHRegiselSB_PPC$Ë4$Ë<$ GNUzR| HAA Av  AAE G KAG F GKAG `hAA LAB A AAD I KA G$L I KA G$L IKA G$ P+AR KAG\|AL CCa A AAI FAL HC A AAG AGFA(PGCa D G KAG(|PGCa D G KAGhAI FjFAA B$HA  AAA G KAG F G KAG E GKAG 0P_AC q AJ GKAGtHAA AkDFA A$B(Ka  AAF AAFALALHA  AAC GKAG ppAC ANEDR A$A(B,Ka A AAG EAL HC A AAH AEFA4 AD ECN i$B(F,B0B4B8K j$B(B,D0K e$F(B,B0B4K d CA AAH E$A(L,H E AA AAE E$A(L,H G$A(L,L K$A(L,H G$A(F$A H$A(F$A H$A(F$A H$A(F$A 0AC CFNI B$P(A,A0B4Kl B$B(B,Kr CA AAF E A$L(HK A$L(HM  K$A(G,F G  K$A(G,F G  K$A(G,F A E$F AL E$F A AC CFN h$B(N$A M$B(N,A0D4B8K q$D(D,B0K e$B(B,B0K q CA AAJ E$A(L,H K$A(L,H G$A(L,L M $K(A,G0F G $K(A,G0F G $K(A,G0F G $K(A,G0F A$A(F$A H$A(F$A H$A(F$A L AA AAN\^`DdF`A\`EdShClLpFtDxA|DK\M`FdDhDlDpb\c AA AAD T `AdFhLlI A`CdI`A\q `KdAhGlN @`N\G`BdGhAlDpBtH\p`BdGhAlDpBtK\l`CdAhGlDpP\T `KdAhGlF O `KdAhGlN `CdJ`A\H`EdBhDlUpDtAxB|BK\M`DdDhBlBpUtFxA|ABK\M`FdEhElBpb\`CdLhDlBpUtAxB|K\t`OdBhJlBpLtAxE|BK\K`AdDhBlSpDtExB|K\`gdBhFlDpLtDxF|JBBK\K`DdDhBlSpAtExB|K\`FdAhAlK\n`FdAhDlK\`CdShClLpDtDxB|BK\M`DdAhBlBpb\`BdN`H\F`BdWhIlEpTtDxA|BH\`FdNhBlRpi\Q`ddGhBlApBtBxV|DBBK\K`AdEhBlSpDtDxB|K\t`EdGhGlN\G `KdAhGlF G `KdAhGlF G `KdAhGlF  `KdAhGlE K `N ]`IdDhBlApElY\D`BdBhAlApDtDx\\ `IdDhBlApEl[ ]`BdN`A\M`BdWhClLpDtAxB|H\\`AdBhBlSpDtDxB|K\K`DdEhBln\w`CdAhElZ\w`CdAhElZ\f`QdBhFlApAtBxB|K\y`QdBhBlAp_\j`PdL`C\K`BdJhGlBp^tDxB|BK\K`AdDhBlSpDtExB|K\n`FdDhDlWpBtFxA|ABBK\K`BdFhAlApBtBxK\ `EdE G `KdAhGlE G `EdO G `KdAhGlF E`AdLhH\K`AdLhH\K`AdLhH\R`EdShClI\i`_dFhDlApAtK\j`FdDhDlDpK\O`AdF`A\R `KdAhGlN E`CdFhJ\Z`AdAhBlK\n`AdDhBlK\^ `KdAhGlN E`AdLhH\E`CdLhFlDpDtBxU|ABK\M`FdAhAlBpStBxF|AABBK\c `KdAhGlF E`AdLhH\K`AdLhH\K`AdLhH\N `FdNhBlRpc\Q`SdAhBlapAtBxB|K\K`DdN F`^dRhGlDpBtBxB|K\U`GdDhBlBpAtf\V`^dP`A\G`AdF`A\H`AdF`A\L`AdLhH\J`AdLhH\L `KdAhGlE G `KdAhGlE G `KdAhGlE G `KdAhGlE E`AdLhH\F`AdF`A\F`EdF`A\J`EdF`A\J`AdF`A\F`AdF`A\F`AdF`A\D`EdF`A\P `EdE G`,4 P*AA CAN^H FAnG HAAG FA AA AAC G K A$G(F G K A$G(F G K A$G(F CH D$LL K A$G(F DG M$C(TP K A$G(N G K A$G(F G K A$G(F G K A$G(F G K A$G(F G K A$G(F G K A$G(F GK A$G(Hd`- AA AAQhJFAKAcCjEGGK@JEGGEG E GEGGEG KAGE IAIHKBAEQAocAIHKALHFAFAc KAGL k KAGE hEGGEdBDJADDNk AA AAA N EE IALHL KAGE AAFAL KAGE R KAGE UBAEQAh KAGE _ EE NBAEQAeFFAPAl UnAIHL EE EAIHJAIH`Uu EE EAIHL KAGE AEFAJEFAJAFAFEFAP EE AEFAJEFAIEFAP0;)8AC ACNLBPA~CAGDP\ KAGO ME^Ap DABP RAIHWADH AA AAD hAAAMMAFAlCFArpvKDDDK[MPAAAKtALHCCIOAAAKg KAGF VGB_BJBLABJBJBJBLABJBMDBBK`DDBRDDBKJDDBRDDBKJDDBRDDBKJDDBRDDBKJDEBTtcFHVAEBWAEBK KAGF G KAGF G KAGE _mJDBaABBKNDEB`jEEDUDBKMFADBSBFEEBBKMFADBSBFEEBBKMFDABSEEDKMDBUFADBKKBFEEBBUHAADBSBFEEBBKMFDABjBFEEBBKKBFAABBUHAAABT^LSBEDUDBKMFADBSBFEEBBKMFADBSBFEEBBKMFDABSBEDKMDBUFADBKKBFEEBBUHAADBSBFEEBBKMFDABTS OPBJAEBKMDABE YqIKBFCEBKOAEmKDDSBFAABBHNBFAABBTgKDDSBFAABBHN BFAABE uHDDX_EJA_EJA_EJAbALA|UABUFAABKvY\BFEDBBRBHAEABBVm mFEDBBRBHAEABBJ o MABJ v {BFDDBUABKMFAABRADKKFADRFDABE P MADJ w MABJ dUABUFAABHk MABJ dNSABUFAABHodFAEBBYi NMBFAABBB d NMBFADBBSBHAAABBJ naFAEBUF LJ F DABK smFLBJEBBTgAEBbqDehBAESYBBEADDX@RRMA DADQ l_FAJRnUVCFAiQHAUDDBDURBHAJ DDBRDDBKJDDBRDDE Z DehBAESYBDE GEGGMEALHKALHUGFEFEGSGFEGFEGNI OBFAABJ hBZCLDABKYABBVDEBKEOAABUM KAGF AAFAHEFAZ KAGF G KAGE G KAGE KCFAiQHAmEGGJGEGGEIEGGEI EB T EE K aNALDABDRJ Y N BaMDAB\RMbBbDEEBUEEBDKRDDBDTKHLBZLETDEBKY ABBSDI QBFCVBFCr OBFAABBJ G KAGE G KAGE GEGGEG EB G EE GEGGEG KAGE G EE G KAGE G EB u ]JALGBBDRSBHAAABE G EE G EE u]LDBBAUKKBFAABTL EE d aMFALBBJ G EE B HBE B HBE G E G EE eHQBWDWFBNBBKMDWDABTLABTAXCIDDDDKK BFDEBBRHADABSBFAEBKKBFEDBBSBHAEEBSBFEEBBKJFDABSBFAABBKKBFAABUFDDBKJFEABJ haRGDBBBKMDDBBDSBHADABBUFAABK\ bIAMEFDDBBWBBAKJFDEBRFI N _hBAEkFABBBKMFADDJ G E U HLBWDQABKYABBWDI G_RDDTL _RDDG G EE G E UHLBWDWCBNBBKUE|%`sAC CCNA B$J Ax V$L(D,Hc M$B(H|  K$A(G,K X AA AAD G  K$A(G,F G  K$A(G,F g  K$A(G,F E N$F(HV 0& vAC CCN(G,P(M,g0B4F8Ap W|e ~` L  ( 8  '  @p I  b  {<     5V2EYȖߟ j )* '0ER "g'( ,H 1p 7i=CI O Up ['a@ gmsy :Vj    0 P  1w  /   i! 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FEM>T[jb4i6p$w~KVZ4l &@-4 ;pB@I0PW^[e'l(sI(z%)(()   &3=IUdt"2JXly)6DUhz!3BXm *<Nf|*>Qm}'$ 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0jV h jV hjV hjV  hjV kwjV -t&wjV :PPt&UWVS|$$|$t$ -2Ap>vl$vWUD$ FvWUD$F[^_]Í&l$vWUD$ Fv WUD$F [^_]Í&l$vWUD$ Fv WUD$F vWUD$F[^_]Ív>D$vWPD$ FXZI&L Ph PPl$vWUD$ Fv YZvWUD$ FXZ[^_]Í&l$vWUD$ Fv 6WUD$l$vWUD$ Fv YX>Y뉍vl$vWUD$ FvYX>cP&fl$v WUD$ F vYX>+ƍvl$v WUD$ F vXZ>P&fl$vWUD$ Fv XZ>ƍvD$vWPD$ FXZt&n}6D$uWPD$ vT$ >UY]vWD$&l$vWUD$ Fv WUD$F v  Pt&l$vWUD$ Fv WUD$F vt&l$v WUD$ F vWUD$FvWUD$Fl$vWUD$ FvYZ`WF l$pD$WUvD$T$ PvWUD$Ft&l$v WUD$ F VPP&UWVS T$,t$(D$0D$$D$ H:mx9=PP,9@9 @@@p@ D$ 8 [^_]Í&fRhh|$, ?P 9h(@9@ @p@D$$)zvD$ciA,$m9#$D$QA$9|$$$AA qI< Ph_ PP< Ph` PP< Pha PP PhPP9v[/D$QA$9v@D$$<$AA qI8< Phf PPt& <$9ol$ml$o;l$sʉ),$fofG fo$;l$s)L$GG GG|$ D$v< Php PP< Phy PP| Ph\PPp PhPPPPfUWVS T$,t$(D$0D$$D$ H:mx9=PP,9@9 @@@p@ D$ 8 [^_]Í&fRhh|$, ?P 9h(@9@ @p@D$$)zvD$ciA,$m9#$D$QA$9|$$$AA qI, Ph PP, Ph PP, Ph PP PhPP9v[/D$QA$9v@D$$<$AA qI8, Ph PPt& <$9ol$ml$o;l$sʉ),$fofG fo$;l$s)L$GG GG|$ D$v, Ph PP, Ph PP| Ph\PPp PhPPPPfWVST$H&wK-p;71t$@PpP [^_Ívp;7\$1@P X@@[^_Í?A9QQ$9sr|$Ay I[^_Ít&p;7sB|$1@PxP [^_Í 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FT$D$|$~$W0>vVFωt w1u 2u T39v {_vÃ{]t$4 % ؁@ @ VH'-++`+F yU'l''p'~t$4  ȉ  G&FJ&P''`)~ j&&&<$p&Vol&&&p&~$ۃ t$4   Ut&FJ%f,,p,n J%-&&`v(Nz%%n&ωʉL$`7(D$ɉ<$y;<$#696; $595ȉD$$\$D$~D$ 1 t$ ˋL$  ً\$4 ыT$  ʋL$@ ʍ 6 4$   ʋL$ @ ʁ S&fF=*>$D$4lt&F |Vx#$&$p:$F t$4  &vF T-1D$4hNjFJu###p#v1҉XzN]" >却&fFJ #))ǃp*V 1~:ŋB,Duƍ % ‹D$4ʀ fD$4~&vu[v Pv^t$4É  y&fVH "%&`:&F z!w%%ƒ`&v42+2 @% t$4 ȉ @ &FQA!!0"`$N z!!!`#v11  t$4 @  t&FQ !!`e#Nrn  ]!`1# t$4 F @ &vFJ #$`=$n Mz p U1)$1Ҁ~‰/?/$ % ʉ ց t$4 vVH `!n Mxp E1)1~/?.  ҋt$4 ȉ t&L$Pz+F (:-D$4hNjFJ  8pHv1҉tL$T .n@/N Z#)r&-- L.+D$4 ʁ &D$H*D$L@+F (t,|$4D$4N }mv1ҹ t]~T$LDT$HT$L?{.T$LL$L@PP Ph<PP Ph- Ph+э PhPP Phߍ PhI  PhPP PhPP PhV PP   PhLd PhPP Ph 4 Ph #@ Ph &fÍUWVS|$ t$D$$\$(??ى ;t' Ph4PP ˁ@;XuxfUWVS|$\$T$ D$(Po?~L$$l$$: 9zzL:9L$$ƉljB= 0 && rD <= 14priv/host_generic_regs.h0hregClass(r) == HRcInt32!hregIsVirtual(r)n <= 15hregClass(r) == HRcFlt64n <= 31hregClass(r) == HRcFlt32hregClass(r) == HRcVec1286432816showARMNeonDataSizerD <= 12am->tag == ARMam1_RIsimm12 >= 0 && simm12 <= 4095r >= 0 && r < 16r%dr >= 0 && r < 32d%ds%dq%dppHRegARMnveqhslomiplvsvchilsgeltgtlealneshowARMCondCode0 <= shift && shift <= 3%d()(,,%u)-255 <= simm9 && simm9 <= 2550 == (simm11 & 3)[], imm8 >= 0 && imm8 <= 255imm4 >= 0 && imm4 <= 15sh >= 0 && sh < 320x%ximm5 > 0 && imm5 <= 31%uARMNImm_to_Imm640x%llX%llX[%u]xoraddadcsubsubssbcandbicorraddsshowARMAluOpshrsarshlshowARMShiftOpnotclznegshowARMUnaryOpumullsmullmulshowARMMulOpdivshowARMVfpOpcpyabssqrtshowARMVfpUnaryOp??invalid??vceqveorvaddvrhaddvextvandvpaddvabdvsubvrecpsvminvtblvqdmullvmaxvqrdmulhvqdmulhvqaddvqsubvpminvcgtvmulvpmaxvmullvcgevmulivorrshowARMNeonBinOp.f.u.s.p.ishowARMNeonBinOpDataTypevabsvrsqrtevrsqrtefpvabsfpvrecipvqmovunvmovvmvnvcntvclsvclzvdupvpaddlvnegvqshlvrecipfvqshluvrev16vrev32vrev64vcvtvqmovnshowARMNeonUnOp.f16.f32.u32.f32.s32.f32.f32.u32.f32.s32.f32.f16showARMNeonUnOpDataTypeshowARMNeonUnarySOpvshlshowARMNeonShiftOpshowARMNeonShiftOpDataTypevzipvuzpvtrnshowARMNeonDualOpicc != ARMcc_NVcond != ARMcc_ALis_sane_RetLoc(rloc)amt >= 1 && amt <= 63cmptst ldrshldrhfastslowbhdr3:dssdfsitodftosidfuitodftouidf64f32vmaxnmvminnm%-4s %s mov imm , 0x%xldr%s str%s %s%s%sstrh%s ldrb%s strb%s ldrsb%s (xDirect) if (%%cpsr.%s) { movw r12,0x%x; movt r12,0x%x; str r12,blx r12 }(xIndir) str (xAssisted) mov%s call%s 0x%x [nArgRegs=%d, %-5s r0, r2, r3r1:r0, r2, r3ldrex%s %sr2, [r4]strex%s r0, %sr2, [r4]fldd fstd flds fsts f%-3sd f%-3ss fcmpd ; fmstatfcpyd%s fcpys%s fcvt%s vmov -lo64, ; vmov -hi64, -lo64-hi64vmov %s vrintr.%s.%s %s.%s fmxr fpscr, fmrx , fpscr(mfence) dsb sy; dmb sy; isbclrexvld1.32 {vst1.32 {} %s%s%s , #0, #%uvshl.i64 vmov%s add32 (evCheck) ldr r12,; subs r12,r12,$1; str r12,; bpl nofail; ldr r12,; bx r12; nofail:ppARMInstr(1)mode64 == FalseaddRegUsage_ARMRI84addRegUsage_ARMRI5addRegUsage_ARMAmode1addRegUsage_ARMAmode2getRegUsage_ARM:Call:regparmsgetRegUsage_ARMInstrmapRegs_ARMRI84mapRegs_ARMRI5mapRegs_ARMAmode1mapRegs_ARMAmode2mapRegs_ARMInstroffsetB >= 0!hregIsVirtual(rreg)offsetB <= 40950 == (offsetB & 3)offsetB <= 1020nbuf >= 320 == (((HWord)buf) & 3)imm5 >= 1 && imm5 <= 31simm8 >= 0 && simm8 <= 255!(bL == 0 && bS == 1)delta > 0 && delta < 40(delta & 3) == 0notCond <= 13disp_cp_xindir != NULL0 == (off8 & 3)0 == (off8 & 0xFFFFFF00)cc < 16 && cc != ARMcc_ALqDhi != dHi && qDhi != dLoqDlo != dHi && qDlo != dLosz1 + sz2 < 2ARMin_NeonImmregD != regN!(*is_profInc)emit_ARMInstr((UChar*)p) - &buf[0] <= 32endness_host == VexEndnessLE0 == (3 & (HWord)p)p[2] == 0xE12FFF3C0 == (delta & (Long)3)uimm24 == simm24validp[2] == 0xE59CB000p[3] == 0xE29BB001p[4] == 0xE58CB000p[5] == 0xE59CB004p[6] == 0xE2ABB000p[7] == 0xE58CB004rc >= HRcInt32 && rc <= HrcLAST0 == (ri->ARMri84.I84.imm4 & ~0x0F)0 == (ri->ARMri84.I84.imm8 & ~0xFF)-4095 <= simm13 && simm13 <= 4095simm11 >= -1020 && simm11 <= 1020szB == 8 || szB == 4 || szB == 2 || szB == 1; movw r12,LO16($disp_cp_chain_me_to_%sEP); movt r12,HI16($disp_cp_chain_me_to_%sEP); ; movw r12,LO16($disp_cp_xindir); movt r12,HI16($disp_cp_xindir); movw r8,$IRJumpKind_to_TRCVAL(%d); movw r12,LO16($disp_cp_xassisted); movt r12,HI16($disp_cp_xassisted); (profInc) movw r12,LO16($NotKnownYet); movw r12,HI16($NotKnownYet); ldr r11,[r12]; adds r11,r11,$1; str r11,[r12]; ldr r11,[r12+4]; adc r11,r11,$0; str r11,[r12+4]ppARMInstr: unhandled case (tag %d)genSpill_ARM: unimplemented regclassgenReload_ARM: unimplemented regclassgenMove_ARM: unimplemented regclassdisp_cp_chain_me_to_slowEP != NULLdisp_cp_chain_me_to_fastEP != NULLi->ARMin.XDirect.cond != ARMcc_NVi->ARMin.XIndir.cond != ARMcc_NVi->ARMin.XAssisted.cond != ARMcc_NVemit_ARMInstr.ARMin_XAssisted: unexpected jump kindhregClass(regDreg) == HRcFlt64hregClass(regMreg) == HRcFlt64cc < 16 && cc != ARMcc_AL && cc != ARMcc_NVevCheckSzB_ARM() == (UChar*)p - (UChar*)p0is_imm32_to_ireg_EXACTLY2( p, 12, (UInt)(Addr)disp_cp_chain_me_EXPECTED)is_imm32_to_ireg_EXACTLY2(p, 12, 0x65556555)  patchProfInc_ARMunchainXDirect_ARMis_imm32_to_ireg_EXACTLY2chainXDirect_ARMimm32_to_ireg_EXACTLY2do_load_or_store32imm32_to_iregiregEncqregEncdregEncfregEncskeletal_RI84skeletal_RI5emit_ARMInstrgenReload_ARMgenSpill_ARMmapRegs_ARMInstrgetRegUsage_ARMInstrppARMInstrARMInstr_NShl64ARMInstr_NCMovQARMInstr_VCMovSARMInstr_VCMovDARMInstr_StrEXARMInstr_LdrEXARMInstr_CallARMInstr_CMovARMInstr_Ld8SARMInstr_LdSt8UARMInstr_LdSt16ARMInstr_LdSt32ppARMRI5ARMRI5_I5ROR32ppARMRI84ARMRI84_I84mkARMAModeVppARMAMode2ARMAMode2_RIppARMAMode1ARMAMode1_RRSARMAMode1_RIhregClassppHRegARM$Ë$Ë4$Ë<$ GNUzR| XAA ALq A AAE  A AAH YKA G$ x+AR KAG +AR KAG +AR KAGT Cq D G  KAGN G  KAGF G  KAGF G KAGT<Ew D G  KAGF G  KAGF G  KAGF G KAGTEw D G  KAGF G  KAGF G  KAGF G KAGT`Cq D G  KAGN G  KAGF G  KAGF G KAG@D LA E AE t AC r AM b N AA AAN AA AAG W  K$A(G,F G  K$A(G,F G  K$A(G,F G  K$A(G,F G  K$A(G,F G  K$A(G,F G K$A(G,p0P/Ar E |  KAGI G  KAGF G  KAGF G  KAGF G  KAGF G KAG< EA ] AD AeC AA EX AF AA J ` AF AA G A FA H W AF AA H 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==N D$D$荬ND$|$T$H+  R RPWj~w u?YZ=G= -= -wWv~wuD$ wuD$?u#|$u=7 -VP&FU* PRYZǍT$ D$v*N D$tD$T$$D$ ~UYNjB;B+ <B$T$ 0GUNjB;B <B$T$@MQ;Q9Q<$bjt&~G i PuD$ XZ=@D$T$ D$D$ D$$wt$7wbT$ L$$B|$D$==-mD$G U;E \ &vF85Vw?ǃ vhD$ F 6 -w>t&#PhPP=4OD$7L$PgV ɉL$ W !UD$G;E M L$ʉD$ UB;B2 B$ WY>W?t$t$RjPt&ƋEP;P&|$kD$}=G U;E EU D$D$rt$jD$(PPhVjUNjB;B <B$VPt$ jUƋB;Bo 4B$PD$=jPZYPhhjt&UƃB;B) 4BvD$T$H 3v Wt$ Rt&ƋEP;P;VPY_8  D$/#Ph%PP#PhbPPvND$D$D$N D$D$D$D$D$ t1D@D$T$ UNjB;B <B$ T$ @qNjEP;P'<P$_ t$UYB;B <B$ ~WuYZƋE;} kD$jjXZQL$ ht$ jUL$ƋB;B":4B$ QD$PPjt&E;} 捴&vֹ|$4t$ 9$ut$V t$@ht$LhPWNjFP;PB<P$|$D$0l$01H ~t&E9} D$0@D$D$0xh$} 0 >ֹzֹ]ֹL$ zt5։}щ\#PhPP#PhPP#PhPPWPD$$l$Pn|t$hWjPUNjFP;P<P$FV P [^_]Ít$PUPWP PhlPPt&1U:T$t$h~XZT$B1;FRjWPNjFP;PWPY]D$|$PH!t$h~ZYEjPW NjFP;P냍&t$PUPWPNjFP;P<P$1WP_]WPY_WPXZWP]X"PhPP!Ph,PP!Ph+PPhjPW6WPXZ Ph)PPD$T$H9nGhjWRpriv/host_generic_regs.hix <= 0xFFFFFenc == 0priv/host_arm_isel.ctmp < env->n_vregmap hregClass(src) == HRcInt32hregClass(dst) == HRcInt32hregClass(r) == HRcInt32hregIsVirtual(r)ty == Ity_I32 || ty == Ity_I8ty == Ity_I32index < 8index < 4index < 20con->tag == Ico_U8index < 16cc != ARMcc_NVty == e->Iex.CCall.rettyis_sane_RetLoc(rloc)rloc.pri == RLPri_IntaddToSp == 0iselIntExpr_R.Iex_Const(arm)didInv != NULLdidInvsane_AMode2(am)sane_AMode1(am)sane_AModeV(am)ee->Iex.Load.ty == Ity_I64hregClass(r) == HRcFlt64tyC == Ity_I1iselInt64ExprhregClass(*rHi) == HRcInt32hregIsVirtual(*rHi)hregClass(*rLo) == HRcInt32hregIsVirtual(*rLo)iselCondCode(arm): CmpXX32iselCondCodety == Ity_I64imm6 <= 32 && imm6 > 0iselNeon64Exprty == Ity_F64e->Iex.Load.ty == Ity_F64hregClass(r) == HRcFlt32iselDblExpr_wrkty == Ity_F32e->Iex.Load.ty == Ity_F32iselFltExpr_wrkty == Ity_V128Illegal element size in VADDIllegal element size in VSUBIllegal element size in VMAXUiselNeonExpr_wrkhregClass(r) == HRcVec128*stackAdjustAfterCall == 0is_RetLoc_INVALID(*retloc)nextArgReg <= ARM_N_ARGREGSnGSPTRs == 0 || nGSPTRs == 1 -- d->tmp == IRTemp_INVALIDrloc.pri == RLPri_Nonerloc.pri == RLPri_2Intrloc.pri == RLPri_V128SpRelrloc.spOff < 256addToSp >= 16addToSp <= 2560 == (rloc.spOff % 8)0 == (addToSp % 8)tyd == Ity_I64ty == Ity_I1iselStmtarch_host == VexArchARMiselBB: IRTemp type -- PUT(%d) = ; exit-cdst->tag == Ico_U32rc >= HRcInt32 && rc <= HrcLASTty == Ity_I32 || ty == Ity_I16 || ty == Ity_I8iselIntExpr_RI5.Iex_Const(armh)hregClass(ri->ARMri5.R.reg) == HRcInt32hregIsVirtual(ri->ARMri5.R.reg)iselIntExpr_RI5: unknown arm RI5 tagARM target supports GetElem with constant second argument only (neon) iselIntExpr_R: cannot reduce treeiselIntExpr_RI84.Iex_Const(armh)hregClass(ri->ARMri84.R.reg) == HRcInt32hregIsVirtual(ri->ARMri84.R.reg)iselIntExpr_RI84: unknown arm RI84 tagsane_AMode: unknown ARM AMode2 tagsane_AMode: unknown ARM AMode1 tagtypeOfIRExpr(env->type_env,e) == Ity_I64e->Iex.Const.con->tag == Ico_U64! hregIsInvalid(env->vregmapHI[tmp])typeOfIRExpr(env->type_env,e) == Ity_I1e->Iex.Const.con->tag == Ico_U1e->Iex.Const.con->Ico.U1 == True || e->Iex.Const.con->Ico.U1 == Falseenv->hwcaps & VEX_HWCAPS_ARM_NEONARM target supports Iop_QShlNsatUUAxB with constant second argument only ARM target supports Iop_QShlNsatSUAxB with constant second argument only ARM target supports Iop_QShlNsatSSAxB with constant second argument only e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U8ARM supports FP <-> Fixed conversion with constant second argument less than 33 only vexGetAllocMode() == VexAllocModeTEMPARM target supports Iop_Extract64 with constant third argument less than 16 only ARM target supports SetElem with constant second argument only 128-bit constant is not implementedIllegal element size in VQADDUIllegal element size in VQADDSIllegal element size in VQSUBUIllegal element size in VQSUBSARM target supports Iop_ExtractV128 with constant third argument less than 16 only nVECRETs == ((retTy == Ity_V128 || retTy == Ity_V256) ? 1 : 0)lg->cvt == ILGop_16Sto32 || lg->cvt == ILGop_16Uto32isel_arm: Ist_Exit: dst is not a 32-bit valuearchinfo_host->endness == VexEndnessLE^dyiselNextiselIntExpr_RI5_wrkiselIntExpr_RI5iselIntExpr_R_wrkiselIntExpr_RiselCondCode_wrkiselCondCodelookupIRTempmk_iMOVds_RRiselInt64Expr_wrkiselInt64ExprlookupIRTemp64doHelperCallWithArgsOnStackdoHelperCalliselNeonExpr_wrkiselNeonExpriselFltExpr_wrkiselFltExpriselDblExpr_wrkiselDblExpriselNeon64Expr_wrkiselNeon64ExpriselIntExpr_RI84_wrkiselIntExpr_RI84iselIntExpr_AMode2_wrkiselIntExpr_AMode2iselIntExpr_AMode1_wrkiselIntExpr_AMode1hregClassiselIntExpr_AModeV_wrkiselIntExpr_AModeViselStmtmkHRegiselSB_ARM$Ë4$ GNUzR| HAA Av  AAE G KAG F GKAG h+AR KAGPjAA Na  AAE ALFAC  AAG AEFAX AH qFAH A AE G KAGF G KAGF GKAG(<GCa D G KAG(h GCa D G KAG(pGCa D G KAG(GCa D G KAGAA AAN_A KeB FF` AA AAD AL FAC AA AAE AL FAK K A$G(F AE FALA FA(0AC ACN8Dl! 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V PhuPP PhgPP Phg PP Phh PP PhPP Ph PP Ph Ph O Phi iL Ph PP Ph@PP PhbPP PhQPP Ph L Ph PP Ph  Ph PP PhPP Pht PPx Ph PP PhT  PhD ΍ Ph^ PP Ph_ PPx Ph. ߍ PhU PPx Ph PP Ph6  PhQ PP PhS `x Ph" O Phj k Phe Ph T Ph C Ph 2 Phz !PPt&ÍUWVS|$ \$$D$(ك$D$% ҅tcO  9uE{ ?D$,1҉щ‰+SD$C ։@[^_]t&;u\됍& PhPP& PhPP& PhPP& PhPP&&UWVS|$ \$$D$(ك$D$% ҅tcO  9uE{ D$,1҉щ‰QD$C ?։@[^_]t&;u\됍& PhPP& PhPP& PhPP& PhPP&&S PhPPnveqcsccmiplvsvchilsgeltgtlealneshowARM64CondCodepriv/host_arm64_defs.cf3 < (1<<1)f4 < (1<<6)f5 < (1<<6)f6 < (1<<5)f7 < (1<<5)f5 < (1<<5)f4 < (1<<12)f2 < (1<<8)f3 < (1<<5)f3 < (1<<8)priv/host_generic_regs.hhregClass(r) == HRcInt64!hregIsVirtual(r)n <= 30hregClass(r) == HRcFlt64n <= 31hregClass(r) == HRcVec128r >= 0 && r < 31x%dr >= 0 && r < 32d%dq%dppHRegARM64%d()%u((,0i < 4wD <= 30-256 <= simm9 && simm9 <= 255scale == 4do_load_or_store32xD <= 30scale == 8do_load_or_store64(S-reg)uimm12 >= 0 && uimm12 <= 4095imm12 < 4096shift == 0 || shift == 12bitN < 2immR < 64immS < 64imm6 > 0 && imm6 < 64hregClass(src) == HRcInt64hregClass(dst) == HRcInt64is_sane_RetLoc(rloc)-4096 < simm && simm < 40960 == (simm & 0xF)armRM <= 3amt >= minSh && amt <= maxShamtB >= 1 && amtB <= 15laneNo <= 1hregClass(src) == HRcVec128hregClass(dst) == HRcVec128hregClass(src) == HRcFlt64hregClass(dst) == HRcFlt64ARM64Instr_VMovaddsub (w)orreorandlsrasrlslnotclznegfastslow umulhsmulhmul b hs2dd2sh2ss2hh2dd2hrecpxneg sqrt rintiabs muldiv4sfrsqrts2dadd 8h16bsub mul fadd fsub fmul fdiv fmax fmin umax umin smax smin and orr eor cmeq cmhi cmgt fcmeq fcmge fcmgt tbl uzp1 uzp2 zip1 zip2 pmul 8hbbpmull 2dssumull 4shhsmull sqadd uqadd sqsub uqsub sqdmullsqdmulhsqrdmulhsqshl uqshl sqrshluqrshlsshl ushl srshl urshl frecpsusqaddsuqaddfsqrtfneg fabs allnot cls clz cnt rbit rev16rev32rev64urecpeursqrtefrecpefrsqrtesqxtn uqxtn xtn sqxtun??sqshluushr sshr shl 2sdsqshrn4hs8bhuqshrnsqshrunsqrshrnuqrshrnsqrshrun%s , #%ucmp%s showARM64LogicOp#nrs(%u,%u,%u)tst showARM64ShiftOpshowARM64UnaryOpmov imm64 , 0x%llxldr str ldruw strw ldruh strh ldrub strb (xDirect) if (%%pstate.%s) { imm64 x9,0x%llx; str x9,blr x9 }(xIndir) str ; imm64 x9,$disp_cp_xindir; br x9 }(xAssisted) imm64 x9,$disp_cp_xassisted; csel , %scall%s 0x%llx [nArgRegs=%d, ]%s xsp, xsp, #%d, xspshowARM64MulOp%s ldxr%s %c2, [x4]stxr%s w0, %c2, [x4]x1 = cas(%dbit)(x3, x5 -> x7)(mfence) dsb sy; dmb sy; isbclrex #15(H-reg), %u(), ld1.2d {st1.2d {}, [characteriseARM64CvtOp%ccvtf (%c-reg)(%c-reg), fcvt%s showARM64FpUnaryOpf%s showARM64FpBinOpf%s fcmp fcsel msr fpcr, mrs , fpcrmsr fpsr, , fpsrshowARM64VecBinOp%s .%s, .%sshowARM64VecModifyOpshowARM64VecUnaryOp8b4h2sshowARM64VecNarrowOpshowARM64VecShiftImmOp.%s, #%uext .16b, .16b, #%uqimm , Bits16toBytes16(0x%x)fmov .d[0], qFromXX .d[%u]mov(%c) (evCheck) ldr w9,; subs w9,w9,$1; str w9,; bpl nofail; ldr x9,; br x9; nofail:ppARM64Instr(1)fcvt%c%c npmzmode64 == TrueaddRegUsage_ARM64RIAaddRegUsage_ARM64RILaddRegUsage_ARM64RI6addRegUsage_ARM64AmodegetRegUsage_ARM64InstrmapRegs_ARM64RIAmapRegs_ARM64RILmapRegs_ARM64RI6mapRegs_ARM64AmodemapRegs_ARM64InstroffsetB >= 0!hregIsVirtual(rreg)0 == (offsetB & 7)offsetB < 40960 == (offsetB & 15)nbuf >= 320 == (((HWord)buf) & 3)opc != 0rM < 31rD < 31sh > 0 && sh < 64scale == 2xN <= 30do_load_or_store16scale == 1do_load_or_store8delta > 0 && delta <= 40(delta & 3) == 0notCond <= 13ptmp != NULLdelta > 0 && delta < 40dist >= 2 && dist <= 5f2 < (1<<19)f4 < (1<<4)ptmp == NULL0 == (simm12 & 0xF)dd < 31 && nn < 31 && mm < 31hD < 32sD < 32dD < 32rQ < 32cond < 16dszBlg2 >= 0 && dszBlg2 <= 2imm4 >= 1 && imm4 <= 15xx < 31xhi < 31 && xlo < 31laneNo < 2!(*is_profInc)emit_ARM64Instr((UChar*)p) - &buf[0] <= 40endness_host == VexEndnessLE0 == (3 & (HWord)p)p[4] == 0xD63F0120p[4] == 0xD61F0120sizeof(ULong*) == 8s???d???????q@ @ ?@ @ @ @ @ @ ???patchProfInc_ARM64unchainXDirect_ARM64chainXDirect_ARM64do_load_or_store64do_load_or_store32X_3_8_5_6_5_5dregEncqregEnciregEncX_2_6_2_12_5_5X_3_6_7_6_5_5X_3_5_8_6_5_5X_8_19_1_4X_3_6_2_16_5imm64_to_iregdo_load_or_store8X_2_6_3_9_2_5_5do_load_or_store16X_3_6_1_6_6_5_5emit_ARM64InstrgenReload_ARM64genSpill_ARM64mapRegs_ARM64InstrgetRegUsage_ARM64InstrppARM64AModeppARM64RI6ppARM64RILppARM64RIAppARM64InstrARM64Instr_VMovARM64Instr_VXfromQARM64Instr_VImmQARM64Instr_VExtVARM64Instr_VShiftImmVARM64Instr_VNarrowVARM64Instr_VCvtF2IARM64Instr_VLdStDARM64Instr_VLdStSARM64Instr_VLdStHARM64Instr_CASARM64Instr_StrEXARM64Instr_LdrEXARM64Instr_AddToSPARM64Instr_CallARM64Instr_MovIARM64RI6_I6ARM64RIL_I13ARM64RIA_I12ARM64AMode_RI12ARM64AMode_RI9hregClassppHRegARM64rc >= HRcInt32 && rc <= HrcLASTszB == 8 || szB == 4 || szB == 2 || szB == 1uimm12 < 8192 && 0 == (uimm12 & 1)uimm12 < 16384 && 0 == (uimm12 & 3)uimm12 < 32768 && 0 == (uimm12 & 7)dszBlg2 == 0 || dszBlg2 == 1 || dszBlg2 == 2; imm64-exactly4 x9,$disp_cp_chain_me_to_%sEP; ; movw x21,$IRJumpKind_to_TRCVAL(%d); (profInc) imm64-fixed4 x9,$NotKnownYet; ldr x8,[x9]; add x8,x8,#1, str x8,[x9]ppARM64Instr: unhandled case (tag %d)getRegUsage_ARM64:Call:regparmsoffsetB >= 0 && offsetB < 32768genSpill_ARM: unimplemented regclassgenReload_ARM: unimplemented regclassgenMove_ARM64: unimplemented regclassdisp_cp_chain_me_to_slowEP != NULLdisp_cp_chain_me_to_fastEP != NULLi->ARM64in.XDirect.cond != ARM64cc_NVemit_ARM64Instr.ARM64in_XAssisted: unexpected jump kinddd < 31 && nn < 31 && mm < 31 && cond < 16-4096 < simm12 && simm12 < 4096evCheckSzB_ARM64() == (UChar*)p - (UChar*)p0is_imm64_to_ireg_EXACTLY4( p, 9, (Addr)disp_cp_chain_me_EXPECTED)is_imm64_to_ireg_EXACTLY4( p, 9, (Addr)place_to_jump_to_EXPECTED)$Ë$Ë4$ GNUzR| $An A G I G I G I G I G I G I G I G I G I G I G I G I G I G I G A G l0AA _ AF G KAGN G KAGF G KAGF G KAGF GKAG@@AL n AD I KAGL IKAGL\AL | AF I KAGL I KAGL IKAGlAA U AH G KAGF G KAGF G KAGF G KAGF GKAGDA H G  KAGN G  KAGF G KAGTdPCn G G  KAGN G  KAGF G  KAGF G KAGTCq D G  KAGN G  KAGF G  KAGF G KAGTCq D G  KAGN G  KAGF G  KAGF G KAG4l[AD AEx A AAJ >E~  M P GF AA A W AF AA H W AF AA H A FA H G  KAGF G  KAGF G EGGFG E`<0 AC c KAGF IGHLH A AB C M GHLHL H AAp ~AA ALC,u 0K4A8G E L 'S Y ` f m t {      D  +  | ` h @ H / 7      L b N % ., 63 !: A wH O V ] c i p w p~ x P   [ a  U a O I       )   J C ; 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PPuD$W$ $F="ƋE P;P\4P$tVPY[([^_]Ít&PVP ffvuZ~Y= = =zND$ɛt$~vPVj‹E p Nv~WuB E;}  NvD$tT$Hw8Gv Wt$ RƋE P;PpPhPP=7T$ D$D$D$ ND$$wt$QwD$0L$4vtPwtt$I P D$pPhPPPhPP&f|$ D$ = G U;E vU$D$D$lt$VU YNjB;B <B$ jD$(PjPVVU NjB;B <B$n Vt$j ƋE P;Pi 4P$i t$_ƋE P;P'&== =v= = =T$ D$v,Y;}  E8O U4t$PjM Q;Q 9Q<$^ t$ VjƋE P;PQ?ND$Jt$kPVj‹E e t& D$8 G U;E Lh PM ]^Q;Q 1Q<$qPXvU$D$T$ D$iD$T$ D$D$wiL$EL$;} <|$ jjt$ U NjB;B <B$jjt$U NjB;BB <B$VBYPt$t$t$)fPhPPhPjvPPPhPPt&PhPPD$T$ D$ t$D$$whPwD$0wjjT$$Y{ND$ʎt$hPVj‹E c Ot& PhPPvNQL$RZYǍEL$;M N D$D$D$w\Ph @ U NjB;B <B$VM _Q;Q1Q<$h t$\}FCPM@9EQWt$ RPƋE P;P)=u+t'ND$'t$ePVj=u= =uM?xD$vUPWhP!t$(j‹E aOt&=8, ND$/WhP!t$ j&fD$vUPWhP!t$(j‹E `&ND$D$~t$D$jt$VjBt&N D$躋V|$WPWj&fXPhPPN D$bV|$PWjPD$-hWt$t$(t&N D$V|$蟼PWjWu$D$ gD$|$ PhIPP&fD$vUP"UD$ ^Y;} PRjN D$VV|$PWjWPXZN D$D$蚳|$D$Nt$WjU ƃ B;B8VRXZYL$VPXZL$D$vUPUD$ ^Y;} ,PRj돍D$v UPD$ ND$ |$ Wjt$$WjU ƋB;BXWPXZyWPXZVPXZ~PPXZ(WPXZWPXZ;PP_XRND$3T$E;} RPL$VPXZL$PPY_ Ph~ PPND$肱T$E;} RPj‹E <\ o Ph OPh3PPPh4PPPhPPWP_XAWPY_VP^_VP^_PhPPPh PhPPVPXZPhPPWRYXZPhPPL$VRY_L$^WRYX)VPY_WRYXOWRYXPD$ QY^D$%WRYX\Pj~PD$QXZD$hPhPPPjPPh Ut$bD$ ZY~PD$Q^_D$fL$VRY_L$PD$QXZD$jPhPPVRXZVPXZWRXZWRXZuVRYXPPh&vUWVSD$H|$4T$8D$D$LD$z7F,;E4F$T$ mF D$0T$AF D$$9V‹$9D$׉VT$ FD$VT$PF(VF$t$1ɉ$14$, >t&Ϳt$,<9D$ut$N$t$@hP!t$LhP!PWNjF P;P<P$k|$+D$0l$01@ ~&E9} D$0@D$D$0xh$} >vxͿ[ytV́8yt3́Ϳ|$PhPP,Ph#PP,Ph&PPUPD$Tal$PZD$ZWjPUNjF P;P <P$F V$P [^_]Ít$PUPWP@PhPP&f1n_vregmap off < (1 << 12)off < (8 << 12)(off & 7) == 0off < (4 << 12)(off & 3) == 0off < (2 << 12)(off & 1) == 0off < (1<<12)con->tag == Ico_U64ri->ARM64riL.I13.bitN < 2ri->ARM64riL.I13.immR < 64ri->ARM64riL.I13.immS < 64arg1con->tag == Ico_U32ehregClass(r) == HRcInt64hregIsVirtual(r)iselInt128Expr(arm64)hregClass(*rHi) == HRcInt64hregIsVirtual(*rHi)hregClass(*rLo) == HRcInt64hregIsVirtual(*rLo)cc != ARM64cc_NV0onety == e->Iex.CCall.rettyis_sane_RetLoc(rloc)rloc.pri == RLPri_IntaddToSp == 0ty == Ity_I64 || ty == Ity_I8ri->ARM64ri6.I6.imm6 < 64ri->ARM64ri6.I6.imm6 > 0ri->ARM64riA.I12.imm12 < 4096ril_one && ril_twoty == Ity_V128ril_onehregClass(r) == HRcVec128iselV128Expr_wrkty == Ity_V256iselV256Expr_wrkhregClass(*rHi) == HRcVec128hregClass(*rLo) == HRcVec128ty == Ity_I64sane_AMode(am)iselCondCode(arm64): CmpXX64iselCondCode(arm64): CmpXX32iselCondCode(arm64): CmpXX16iselCondCode(arm64): CmpXX8iselCondCodenGSPTRs == 0 || nGSPTRs == 1retTy != Ity_V256nVECRETs == 0!hregIsInvalid(r_vecRetAddr)!(hregIsInvalid(tmpregs[i]))*stackAdjustAfterCall == 0is_RetLoc_INVALID(*retloc)ty == Ity_F64e->Iex.Load.ty == Ity_F64hregClass(r) == HRcFlt64iselDblExpr_wrkty == Ity_F32e->Iex.Load.ty == Ity_F32iselFltExpr_wrkty == Ity_F16iselF16Expr_wrk -- d->tmp == IRTemp_INVALIDrloc.pri == RLPri_Nonerloc.pri == RLPri_V128SpRelrloc.spOff < 256addToSp >= 16addToSp < 256ty == Ity_I1cas->expdHi == NULLcas->dataHi == NULLiselStmtarch_host == VexArchARM64iselBB(arm64): IRTemp type -- PUT(%d) = ; exit-cdst->tag == Ico_U64n < 2 && imm_s < 64 && imm_r < 64ty == Ity_I64 || ty == Ity_I32 || ty == Ity_I16 || ty == Ity_I8ty == Ity_I64 || ty == Ity_I32e->Iex.Const.con->tag == Ico_U64e->Iex.Const.con->tag == Ico_U32rc >= HRcInt32 && rc <= HrcLASThregClass(ri->ARM64riL.R.reg) == HRcInt64hregIsVirtual(ri->ARM64riL.R.reg)iselIntExpr_RIL: unknown arm RIL tagtypeOfIRExpr(env->type_env,e) == Ity_I128iselIntExpr_R.Iex_Const(arm64)iselIntExpr_R: cannot reduce treehregClass(ri->ARM64ri6.R.reg) == HRcInt64hregIsVirtual(ri->ARM64ri6.R.reg)iselIntExpr_RI6: unknown arm RI6 tagiselIntExpr_RIA.Iex_Const(arm64)ri->ARM64riA.I12.shift == 0 || ri->ARM64riA.I12.shift == 12hregClass(ri->ARM64riA.R.reg) == HRcInt64hregIsVirtual(ri->ARM64riA.R.reg)iselIntExpr_RIA: unknown arm RIA tagtypeOfIRExpr(env->type_env,mode) == Ity_I32typeOfIRExpr(env->type_env, env->previous_rm) == Ity_I32e->Iex.Const.con->tag == Ico_V128! hregIsInvalid(env->vregmapHI[tmp])sane_AMode: unknown ARM64 AMode1 tagtypeOfIRExpr(env->type_env,e) == Ity_I1retTy == Ity_V128 || retTy == Ity_V256retTy != Ity_V128 && retTy != Ity_V256nVECRETs == ((retTy == Ity_V128 || retTy == Ity_V256) ? 1 : 0)isel_arm: Ist_Exit: dst is not a 64-bit valuearchinfo_host->endness == VexEndnessLE @ @ @ @ @ @/.-,3210iselNextiselInt128Expr_wrkiselInt128ExpriselIntExpr_RI6_wrkiselIntExpr_RI6iselIntExpr_RIL_wrkiselIntExpr_RILisZeroU64iselIntExpr_R_wrkiselIntExpr_Rmk_baseblock_64bit_access_amodeiselIntExpr_RIA_wrkiselIntExpr_RIAiselCondCode_wrkiselCondCodelookupIRTempmb_mkARM64RIL_IdoHelperCalllookupIRTempPairiselV256Expr_wrkiselV256ExpriselV128Expr_wrkiselV128ExpriselF16Expr_wrkiselF16ExpriselFltExpr_wrkiselFltExprset_FPCR_rounding_modeiselDblExpr_wrkiselDblExprmk_baseblock_128bit_access_addrmk_baseblock_8bit_access_amodemk_baseblock_16bit_access_amodemk_baseblock_32bit_access_amodehregClassiselIntExpr_AMode_wrkiselIntExpr_AModeiselStmtmkHRegiselSB_ARM64$Ë4$Ë<$ GNUzR| HAA Av  AAE G KAG F GKAG h(AR HAGPjAA Na  AAE ALFAC  AAG AEFAp AF LACH AA AAH gLAPATLHC AA AAD K LKPATGXJ 4TGAT AEHA D G KAG(0GCa D G KAG(GCa D G KAG(GCa D G KAG@ oA[ AEHA E G  KAGF G KAG@ToA[ AEHA E G  KAGF G KAG@oAZ AEHA F G  KAGF G KAGpEA AANTG A$F(B,LiA B$B(N_ CA AAI AL FAML FAE AA AAC AE FALA FAAA CANcB B$G(A,E0A4Kc CA AAC AL FAE CA AAA G K A$G(F AE FAp EA AANfB B$G(A,D0A4Kd CA AAF AL FAE CA AAI G K A$G(F AE FA` AA CANcB B$G(A,E0A4Kc CA AAC AL FAE CA AAA G K A$G(F AE FA@@ AA AANnA G$A(E,A0Kg CA AAI AL FAE CA AAA G K A$G(F G K A$G(F AE FAP AA CCN@DDBHFDA@wDAHBLM@q AA AAA ] AA AAG UDDHBLM@u AA AAG x DAHALN DEHDLAPM@MDAHFDA@QDEHGLDPH@h DKHALGPI DBHH@~ DAHDLAPR S DLHI DAHGLGPQTAXE\V@d DKHALGPJ G DKHALGPF ADLHFDA@MDLHFDA@^DAHALEHBLDPDTK@w DAHALEHBLB BDBHDLK@oDBHDLK@{DDHDLDPK@hDGHALEPATM@fDGHALEPATM@DBHDLQPBTDX\@JDDHDLAPR@VDAHALEHFLAPDTK@n DGHALEPATJ dDDHDLM@MDAHFDA@mDAHDLK@n DGHALEPATJ hDAHDLK@ODEHFDA@d DDHDLJ TDAHALEHKDA@mDKHALAPATK@oDDHALAPK@X DE `DAHALEHKDA@QDBHFDA@ DKHALGPE DAHELDPM@MDAHFDA@~DAHDLEHEDA@FDAHALAPV@R DEHDLAPM ADAHDLEHEDA@DAHALFHYLDPATEXV@DGHMLDPQTIXK\D`H@LDDHBLEPATBXQ\I`J@DDAHVDA@Q DKHALGPM oDAHBLV@w DAHBLN o DAHBLN G DAHELDPO bDDHFDF@ADF@v DKHALGPN RDEHALV@Q DKHALGPN G DKHALGPF M DDHBLM M DDHBLM G DHHALGPI G DKHALGPF M DDHBLJ G DKHALGPE ADLHFDA@L DKHALGPI o DDHDLJ ADLHFDA@L DKHALGPE O DLHL ADLHFDA@FDLHFDA@FDLHFDA@DDHDLDPH@DDHDLDPH@b DKHALGPJ ADAHFDA@\ DKHALGPE G DKHALGPE kDAHALAPR@FDLHFDA@L DKHALGPE ADLHFDA@FDLHFDA@L DKHALGPE ADLHFDA@FDAHFDA@L DKHALGPE h DAHBLJ ADEHFDA@JDEHFDA@q DAHBLJ G DKHALGPE G DKHALGPE iDAHDLBH\LAPATBPTTAXD\A`H@UDEHFDA@JDEHFDA@JDEHFDA@P DKHALGPE G DKHALGPE [DAHALEHKLAPATEPo@D DDHNLBPATQXB\A`H@LDAHALAPQTBXA\Q`AdAhAlH@LDBHALQPATAXA\Q`BdAhH@LDAHALAPJ ADAHFDA@FDLHFDA@FDLHFDA@|DGHALDPQTAXD\A`H@| DAHALEHXLGPATDXA\T`H@BDAHALAPJ IDAHALEHKLAPATEPo@L DKHALGPE G DKHALGPE G DKHALGPE M DKHALGPE ADEHFDA@J DLHE ADAHFDA@L DKHALGPE VDL @,AL e AE I KAGL I KAGL IKAG , AC CNABFA]F{ KA G$H W A AAF QFP KA G$N G KA G$F G KA G$F G KA G$F G KA G$F G KA G$F G KA G$E G/wAA CCNAB FAF{ AA AAJ ` K A$G(M fA FAQ K A$G(N G K A$G(F BA FAM K A$G(F G K A$G(F G K A$G(F G K A$G(F G K A$G(E G E G1AC ACN0A4B8F4A04G8AR bAX CA^ T P P P P mS cS YS OS ES ;S 1S 'S S S S R R R R$ R+ R2 R9 R@ RG RN RU R\ Rc }Rj sRq iRx _R UR KR AR 7R -R #R S wS R R R Q Q Q Q Q Q Q QQ QQQ Q'yQ.oQ5eQ<[QCQQJGQQ=QX3Q_)QfQmQt Q{PPOOOOOO:P0P&PPNPDPXPOOOOO\OUTT#T*T1T8pT?OFSMUTU[UbUixUpiUwZU~KU+D+ K+ qW+ ]+h+ ++ ++ + + q+ ++++ +++ , q, ,,+,, 2,B,H, z, , n, ,, , q, ,, , q, ,,,  -m-- - q- -- . . q. #.2. 9. nE. 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@PhN*PPxPhw+PPUt$t$ jRT$ VPh T$ j jjjXPh*,Ph_PPPh$D$ j jjjD$ D$ Rj RhD$ AD$j jjjD$$Rj ^]$Phh*jVPhۍD$SjRhD$ PhPPD$ jjRhD$ $j jjj$!L$PVjt$ UPh{L$a$j jjjjRh$bjjPh.Ph'PPt$jQL$jPhD$\$h1҃L$  S$ T$ t$jQjRhD$\$hD$‹D$$C؃ iL$ jjPhL$ ƉL$PRT$jjlL$T$ Ph+ʼnPRT$jjl$ Ph*Ph 'XPhPPPh*hPhƉ $Pjjjl $L$T$SjPhL$T$jt$PhD$QL$jVUt$jRhq D$L$L$SjPhL$oUPVt$ Ph+/UPVt$ Ph+bL$SjPhL$$t$ jUVt$jRhq $L$SjPhL$u Ph(,PPjVPhL$(D$$jjt$t$t$t$Rh] L$(D$$4$PD$URT$VQhD$ T$ L$(D$$jjt$t$t$t$Rh] L$(D$$'D$P|+D$PL$(D$$t$t$t$ t$ Rh L$(D$$jj jjjPh{0Ph:!PPPhRVPhzPh~PVQL$ Ph+" $jt$jQL$$RT$ Ph{L$T$ mPVQL$ RVPhW1t$Pf-QL$jVt$jPh $RPD$UVt$ jRT$ t$Ph T$ ]QL$jVUt$jPhq $UVt$ jRT$ t$Ph T$ PhRPD$Rh+$t$ jUVt$jPhq gt$ jPt$jPhUVt$ jRT$ t$Ph T$ QL$VPh $UVt$ jRT$ t$Ph T$ QL$PVjt$ UPh{L$VUPQL$Ph+ $VUt$RT$QL$Ph+T$ L$VUt$RT$QL$Ph+T$ L$VUPQL$Ph+ $QVPh+L$PȉQ PPPPPPUPPPPPP&&%Í&fS Ph-PPUWVS|$0|$,t$4$D$81҉щ‰8t&Ph6-PP&xuԋD$<5w)l$ʚ;T$ $; $T$D$ttD$1ɉl$D$D$fFF t&D҃9r)7G[^_]D$<1҉щ‰ԍt&Ph,-PPt$ t$ jjjlHt&UWVS|$ |$t$$,>t?D$(1҉щ‰^8Ph-PP~uFF9D$(F҃Tt&9tdxtPh-PPt&xiT$,11ۉf^輢<&vD$,1E1fNщ‰艢Eub1f)7G[^_]vPh-PP&fPh-PP$j jjj$농$T$jjQh1T$fFD$щ‰ԡC$L$jjPhT$L$fF蛡size=%d lgrlghilraebrsebrmeebrdebradbrsdbrmdbrddbraxbrsxbrmxbrdxbrs390_insn_bfp_binop_emitlpebrlpdbrlpxbrlnebrlndbrlnxbrlcebrlcdbrlcxbrsqebrsqdbrsqxbrs390_insn_bfp_unop_emitpriv/host_s390_defs.cs390_host_has_dfpsldtsrdtiedtrslxtsrxtiextrs390_insn_dfp_intop_emitadtradtrasdtrsdtramdtrmdtraddtrddtraqadtraxtraxtrasxtrsxtramxtrmxtradxtrdxtraqaxtrs390_insn_dfp_binop_emitcode[0] == 0xC0code[1] == (0x08 | regmask)code[6] == 0xC0code[7] == (0x09 | regmask)code[0] == 0xA5code[1] == (0x03 | regmask)code[2] == (hw >> 8)code[3] == (hw & 0xFF)code[4] == 0xA5code[5] == (0x02 | regmask)code[6] == (hw >> 8)code[7] == (hw & 0xFF)code[8] == 0xA5code[9] == (0x01 | regmask)code[10] == (hw >> 8)code[11] == (hw & 0xFF)code[12] == 0xA5code[13] == (0x00 | regmask)code[14] == (hw >> 8)code[15] == (hw & 0xFF)vfpsos390_host_has_fpextcfdtrcfxtrcgdtrcgxtrclfdtrclfxtrclgdtrclgxtrcdftrcxftrcdgtrcdgtracxgtrcdlftrcdlgtrcxlftrcxlgtrldetrlxdtrledtrldxtrs390_insn_dfp_convert_emitcfebrcfdbrcfxbrcgebrcgdbrcgxbrclfebrclfdbrclfxbrclgebrclgdbrclgxbrcefbrcefbracdfbrcxfbrcegbrcegbracdgbrcdgbracxgbrcelfbrcdlfbrcxlfbrcelgbrcdlgbrcxlgbrldebrlxebrlxdbrledbrledbralexbrlexbraldxbrldxbrafiebrfidbrfixbrs390_insn_bfp_convert_emitipmsrliihfs390_host_has_eimmiilfiilliilhiihliihhlhillilflgfillilhstglglhysrlgsllglgdrstdyldgrldyxcmvimvhhimvhimvghisthsts390_insn_mimm_emits390_amode_get_reg_usages390_opnd_RMI_get_reg_usages390_amode_map_regss390_opnd_RMI_map_regs(r1 & 0x1) == 0r1p1 == r1 + 1s390_insn_clz_emitflogrltgrllillaghiiclhlvlicylys390_emit_load_memslfisrdrdlrs390_insn_div_emitdlgrddldlgltrltltgs390_insn_test_emitpriv/host_generic_regs.hstesteystds390_insn_store_emitinsn->size == 16vststcstcysthystycrclrcgrclgrcclcyclycgclgcficlficgficlgfis390_insn_compare_emitmrmlrs390_insn_mul_emitmlgrmmlmfymlglocgrs390_host_has_lscloclocginsn->size == 8s390_insn_cond_move_emitarmsrnrorxrsllsraagrsgrmsgrngrogrxgrsragdst != 15ahshmhahyshymhyasmsnoxaysymsynyoyxyagsgmsgngogxgahimhinilloillafimsfinilfoilfxilfagfislgfimsgfinihfoihfxihfs390_insn_alu_emitlbrllcrlgbrllgcrlhrllhrlghrllghrlgfrllgfrlbllclgbllgcllhllghlghlgfllgfs390_widen_emitlcrlcgrs390_negate_emitvgbmvrepinsn->size < 8vuphvuplhvlpvclzvctzvpopctvfsqs390_insn_unop_emitix >= 0ix <= 0xFFFFFenc <= 0x7F%%vR%u%%vF%u%%vV%ur < 16r < 32s390_hreg_as_stringfits_unsigned_12bit(d)fits_signed_20bit(d)hregNumber(b) != 0hregNumber(x) != 0invalid guest state offsetinvalid stack pointer offset%d(%s)%d(%s,%s)s390_amode_as_stringalwaysnevergreater thannot low or equalless thannot high or equallow or highnot equalequalnot low or highgreater or equalnot lowless or equalnot highnot overflowoverflowSys_syscallBoringReturnClientReqYieldEmWarnEmFailNoDecodeMapFailInvalidateNoRedirSigTRAPSigFPESigSEGVSigBUSCall%s%-8sguest[%u]s390_cc_as_strings390_jump_kind_as_string, r%u%lld%llu0x%llxs390_printfs390_amode_is_sanegpr_index[i] >= 0vr_index[i] >= 0s390_insn_get_reg_usages390_insn_map_regsoffsetB >= 0!hregIsVirtual(rreg)src->tag == S390_AMODE_B12dst->tag == S390_AMODE_B12! hregIsVirtual(dst_hi)! hregIsVirtual(dst_lo)size == 4 || size == 8! hregIsVirtual(op1_hi)! hregIsVirtual(op1_lo)size == 8! hregIsVirtual(op1)! hregIsVirtual(rem)! hregIsVirtual(num_bits)! hregIsVirtual(clobber)hregNumber(op2->x) == 0hregNumber(scratch) == 1is_sane_RetLoc(rloc)size == 16hregIsInvalid(op_lo)s390_host_has_giesize == 4v-rshav-addv-mulv-andv-orv-xorv-lshv-rshv-subv-mulsv-muluv-divsv-divuv-vfloatabsv-zeroxv-negv-vfillv-vdupv-vunpacksv-vunpackuv-vfloatnegv-vfloatsqrtv-signxv-cmpsv-cmpuv-fmaddv-fmsubv-faddv-fsubv-fmulv-fdivv-fabsv-fnabsv-fnegv-fsqrtv-f2fiv-i2fv-f2iv-f2uv-f2fv-u2fv-dquav-daddv-dmulv-ddivv-dsubv-d2expv-d2sigv-dshrv-diexpv-dshlv-dcmpv-dcmpexpv-d2uv-d2dv-u2dv-d2iv-i2dv-f2dv-d2ffastslowv-vgetelemv-veshlv-veshrav-veshrlv-vfloatcmplv-vpackv-vpacksaturuv-vcmpeqv-vorv-vxorv-vandv-vmergelv-vmergehv-vnorv-vintaddv-vintsubv-vmaxuv-vmaxsv-vminuv-vminsv-vavguv-vavgsv-vcmpgtsv-vcmpgtuv-vintmulhisv-vintmulhiuv-vintmullov-vintmulevensv-vintmulevenuv-velemshlv-vshravv-vshrlvv-vrollvv-vshlbitsv-vshrlbitsv-vshrabitsv-vshlbytesv-vshrlbytesv-vshrabytesv-vpwsumwv-vpwsumdwv-vpwsumqwv-vinitfromgprsv-vfloataddv-vfloatsubv-vfloatmulv-vfloatdivv-vfloatcmpeqv-vfloatcmplev-vpacksatursv-vfloatmaddv-vfloatmsubv-vpermv-load%M %R,%Av-storev-move%M %R,%Rv-memcpy%M %A,%A%M if (%C) %R,%Ov-loadi%M %R,%I%M %R,%Ov-divsiv-clzv-test%M %Ov-cc2b%M %R,%Cv-cas%M %R,%A,%R,%Rv-cdas%M %R,%R,%A,%R,%R,%R,%Rv-call%M if (%C) %s{%I}(%L)%M %R,%R,%Rv-fcmpv-drrndv-mfence%Mv-mimm%M %A,%Iv-madd%M %A += %I (= %I)v-set-fpc-bfprm%M %Rv-set-fpc-dfprmv-evcheckv-profincv-xdirect%M if (%C) %A = %I %sv-xindir%M if (%C) %A = %Rv-xassisted%M if (%C) %J %A = %R%M %R, %R, %Av-vsetelem%M %R, %A, %R%M %R, %R, %R%M %R, %R, %R, %R 1 -> 2 -> 4 -> 8 -> 16 -> %u bytess390_insn_as_stringvpkvpklsvpksvceqvovxvnvmrlvmrhvnovavsvmxlvmxvmnlvmnvavglvavgvchvchlvmhvmlhvmlvmevmleveslvvesravvesrlvverllvvslvsrlvsravslbvsrlbvsrab(size == 1) || (size == 2)vsum(size == 2) || (size == 4)vsumg(size == 4) || (size == 8)vsumqvlvgpvfavfsvfmvfdvfcevfchvfches390_insn_vec_binop_emitleleylds390_insn_load_emitldrvlrs390_insn_move_emitmvcvalue == 0lzerlzdrs390_insn_load_immediate_emitdsgrdsgs390_insn_divs_emitcscsycsgs390_insn_cas_emitscratch == 1cdscdsycdsgs390_insn_cdas_emitstfpcbasrlfpcmaebrmsebrmadbrmsdbrs390_insn_bfp_triop_emitcebrcdbrcxbrs390_insn_bfp_compare_emiteedtreextresdtresxtrs390_insn_dfp_unop_emitcdtrcedtrcxtrcextrs390_insn_dfp_compare_emitrrdtrrrxtrs390_insn_dfp_reround_emitrm < 2 || rm > 7s390_host_has_pfpopfpos390_insn_fp_convert_emitasiagsisfpc*is_profinc == Falseamode->tag == S390_AMODE_B12disp_cp_xindir != NULLfits_unsigned_12bit(op2->d)vlgvveslvesravesrls390_insn_vec_amodeop_emitvlvgvpermvfmavfmss390_insn_vec_triop_emitemit_S390Instrend - buf <= nbufsizeof(ULong *) == 8endness_host == VexEndnessBEp[6+i] == 0x00s390_getM_from_size: unknown sizem4 == 0 || s390_host_has_fpext*(const UInt *)&code[2] == (value >> 32)*(const UInt *)&code[8] == (value & 0xFFFFFFFF)s390_host_has_fpext || m3 < 1 || m3 > 7m3 == 0 || s390_host_has_fpextbuf - begin == s390_tchain_load64_len()rc >= HRcInt32 && rc <= HrcLASTs390_insn_store_emit: unknown dst->tag for HRcVec128am->tag == S390_AMODE_B12 || am->tag == S390_AMODE_B20insn->size == 4 || insn->size == 8delta > 0 && delta < (1 << 16)insn->variant.unop.src.tag == S390_OPND_IMMEDIATEinsn->variant.unop.src.tag == S390_OPND_REGgenSpill_S390: unimplemented regclassgenReload_S390: unimplemented regclasssize == 1 || size == 2 || size == 4 || size == 8 || size ==16genMove_S390: unimplemented regclasssize == 1 || size == 2 || size == 4 || size == 8 || size == 16size == 1 || size == 2 || size == 4 || size == 8op2->tag == S390_AMODE_B12 || op2->tag == S390_AMODE_B20is_valid_fp128_regpair(dst_hi, dst_lo)is_valid_fp128_regpair(op2_hi, op2_lo)is_valid_fp128_regpair(op_hi, op_lo)is_valid_fp128_regpair(op1_hi, op1_lo)hregIsInvalid(op_lo) || is_valid_fp128_regpair(op_hi, op_lo)is_valid_fp128_regpair(op3_hi, op3_lo)dst->tag == S390_AMODE_B12 || dst->tag == S390_AMODE_B20guest_IA->tag == S390_AMODE_B12counter->tag == S390_AMODE_B12fail_addr->tag == S390_AMODE_B12%M counter = %A, fail-addr = %As390_insn_helper_call_emit: invalid conditional RetLoc.evCheckSzB_S390() == code_end - code_begindisp_cp_chain_me_to_slowEP != NULLdisp_cp_chain_me_to_fastEP != NULLs390_insn_xassisted_emit: unexpected jump kinds390_insn_is_BR(next, S390_REGNO_TCHAIN_SCRATCH)p + delta == place_to_jump_to_EXPECTED            unchainXDirect_S390s390_tchain_verify_load64chainXDirect_S390patchProfInc_S390s390_insn_vec_triop_emits390_insn_vec_binop_emits390_insn_vec_amodeintop_emits390_insn_vec_amodeop_emits390_insn_xassisted_emits390_insn_xindir_emits390_insn_xdirect_emits390_insn_evcheck_emits390_tchain_load64s390_emit_AGSIs390_emit_ASIs390_emit_PFPOs390_insn_fp_convert_emits390_emit_RRXTRs390_emit_RRDTRs390_emit_LDXTRs390_emit_LEDTRs390_emit_LXDTRs390_emit_LDETRs390_emit_CXLGTRs390_emit_CXLFTRs390_emit_CDLGTRs390_emit_CDLFTRs390_emit_CXGTRs390_emit_CDGTRAs390_emit_CXFTRs390_emit_CDFTRs390_emit_CLGXTRs390_emit_CLGDTRs390_emit_CLFXTRs390_emit_CLFDTRs390_emit_CGXTRs390_emit_CGDTRs390_emit_CFXTRs390_emit_CFDTRs390_emit_CXTRs390_emit_CDTRs390_emit_SRXTs390_emit_SLXTs390_emit_SRDTs390_emit_SLDTs390_emit_QAXTRs390_emit_DXTRAs390_emit_MXTRAs390_emit_SXTRAs390_emit_AXTRAs390_emit_QADTRs390_emit_DDTRAs390_emit_MDTRAs390_emit_SDTRAs390_emit_ADTRAs390_emit_FIXBRAs390_emit_FIDBRAs390_emit_FIEBRAs390_emit_LDXBRAs390_emit_LEXBRAs390_emit_LEDBRAs390_emit_CXLGBRs390_emit_CDLGBRs390_emit_CELGBRs390_emit_CXLFBRs390_emit_CDLFBRs390_emit_CELFBRs390_emit_CDGBRAs390_emit_CEGBRAs390_emit_CEFBRAs390_emit_CLGXBRs390_emit_CLGDBRs390_emit_CLGEBRs390_emit_CLFXBRs390_emit_CLFDBRs390_emit_CLFEBRs390_insn_helper_call_emits390_insn_cdas_emits390_insn_cas_emits390_insn_unop_emits390_insn_clz_emits390_emit_XILFs390_emit_OILFs390_emit_NILFs390_insn_alu_emits390_insn_load_immediate_emits390_emit_IILFs390_emit_LOCGRs390_insn_cond_move_emits390_insn_store_emitemit_S390Instrs390_insn_vec_binops390_insn_vec_amodeintops390_insn_vec_amodeops390_insn_evchecks390_insn_xassisteds390_insn_xindirs390_insn_xdirects390_insn_set_fpc_dfprms390_insn_set_fpc_bfprms390_insn_madds390_insn_mimms390_insn_dfp128_rerounds390_insn_dfp128_converts390_insn_dfp128_compares390_insn_dfp128_intops390_insn_dfp128_unops390_insn_dfp128_binops390_insn_fp128_converts390_insn_fp_converts390_insn_dfp_rerounds390_insn_dfp_converts390_insn_dfp_compares390_insn_dfp_intops390_insn_dfp_unops390_insn_dfp_binops390_insn_bfp128_converts390_insn_bfp128_compares390_insn_bfp128_unops390_insn_bfp128_binops390_insn_bfp_converts390_insn_bfp_compares390_insn_bfp_unops390_insn_bfp_binops390_insn_bfp_triops390_insn_helper_calls390_insn_compares390_insn_cdass390_insn_cass390_insn_tests390_insn_clzs390_insn_divss390_insn_divs390_insn_muls390_insn_cond_moves390_insn_memcpys390_insn_moves390_insn_stores390_insn_loadgenReload_S390genSpill_S390getRRegUniverse_S390s390_amode_bx20s390_amode_bx12s390_amode_b20s390_amode_b12hregClass%v0%v1%v2%v3%v4%v5%v6%v7%v8%v9%v10%v11%v12%v13%v14%v15%v16%v17%v18%v19%v20%v21%v22%v23%v24%v25%v26%v27%v28%v29%v30%v31%f0%f1%f2%f3%f4%f5%f6%f7%f8%f9%f10%f11%f12%f13%f14%f15%r0%r1%r2%r3%r4%r5%r6%r7%r8%r9%r10%r11%r12%r13%r14%r15s390_hreg_as_strings390_hreg_vrs390_hreg_fprmkHRegs390_hreg_gpr$Ë$Ë$Ë4$Ë<$Ë,$ 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P7D$ÍZYv t$djVOW\$ D$hD$4s YD$lٍ$L$D$ $qHt$ QPL$ q$$  PhPPt&v>V \$dND$@&D$dND$DT$dN؉T$HL$d؉\$L$LN\$dVG\$P_9) :_ L$`9 8C T$Tjt$ D$hD$j t$T$lT$ t$Tt$ j‹GXt$dt$0j ‹GXj t$ L$hL$4j t$D$lD$@t$Lt$v 7~D$XZuVoD$ X>FD$P7XZ (D>v7D$FD$ TUXZtF8 D$t1Det$D$ XD$- |>|$uʍ ߋA$Q(D$0D$T$4PBRA$Q(T$ TeD$Dett\$0D$43\$3D$ tX\$\$8t9D$+D$0ËT$ T$4D$8T$XOۍAGD$dML$dVQL$ S‹G'M L$ (PhPPunL$xuEt$0t$j‹GL eVt$ S‹GL CPhPPPhPPPhPPPhPPqt$Vt$P‹GKA0R>D$IX L$0\$t$\$YL$09sP9sINt$ht$t$T$HRVP‹G9KT$QPt$T$ R‹G KXډ\$ T$$t$t$(t$(t$P‹GJy@˜D$ T$$@D$ T$$@T$ T$$댋P@T$$D$ yPA0w⋴> 3\$xPhXډ\$(T$,t$t$0t$0 @˜D$(T$,@D$(T$,@T$(T$,릋P@T$,D$(떋D$Pt$ D$`t$\t$`t$`PjPpartial update of this guest state register is not allowed! hregIsInvalid(env->vregmap[tmp])ty == Ity_F32 || ty == Ity_F64s390_isel_float_expr: invalid constantcannot load immediate floating point constantirrm->Iex.Const.con->tag == Ico_U32s390_isel_float_expr: cannot reduce treerc >= HRcInt32 && rc <= HrcLAST! hregIsInvalid(env->vregmapHI[tmp])s390_isel_dfp128_expr_wrk: cannot reduce treehregClass(*dst_hi) == HRcFlt64hregClass(*dst_lo) == HRcFlt64ty == Ity_D64 || ty == Ity_D32s390_isel_dfp_expr: cannot reduce trees390_isel_float128_expr: cannot reduce treety == Ity_I8 || ty == Ity_I16 || ty == Ity_I32 || ty == Ity_I64s390_isel_int_expr: impossible Iop_GetElem types390_isel_int_expr: unhandled V128toSMTH operations390_isel_int_expr: invalid constanttypeOfIRExpr(env->type_env, cond_expr) == Ity_I1s390_isel_int_expr: cannot reduce treetypeOfIRExpr(env->type_env, expr) == Ity_I64s390_amode_is_sane(am) && (am->tag == S390_AMODE_B12 || am->tag == S390_AMODE_B20)typeOfIRExpr(env->type_env, irrm) == Ity_I32expr->Iex.Const.con->tag == Ico_V128s390_isel_vec_expr: cannot reduce treehregClass(*dst_hi) == HRcInt64hregClass(*dst_lo) == HRcInt64typeOfIRExpr(env->type_env, cond) == Ity_I1cond->Iex.Const.con->tag == Ico_U1cond->Iex.Const.con->Ico.U1 == True || cond->Iex.Const.con->Ico.U1 == Falses390_isel_cc: unexpected operatordoHelperCall: too many argumentscalling %s: argument #%u has type ; Ity_I64 or Ity_V128 is required cannot continue due to errors in argument passing; an integer type is required (VEX_HWCAPS_S390X(hwcaps_host) & ~(VEX_HWCAPS_S390X_ALL)) == 0archinfo_host->endness == VexEndnessBEIst_Store with 128-bit floating point dataIst_Put with 128-bit floating point datad->fxState[i].nRepeats == 0 && d->fxState[i].repeatLen == 0s390_isel_stmt: invalid return type from dirty helpers390_isel_stmt: Ist_Exit: dst is not a 64-bit value  iselNexts390_isel_int_expr_wrks390_isel_int_exprs390_isel_cclookupIRTemps390_isel_amode_b12_b20add_to_SPsub_from_SPdoHelperCalls390_isel_vec_expr_wrks390_isel_vec_exprlookupIRTemp128s390_isel_dfp128_expr_wrks390_isel_dfp128_exprs390_isel_dfp_expr_wrks390_isel_dfp_exprs390_isel_float128_expr_wrks390_isel_float128_exprset_bfp_rounding_mode_in_fpcget_bfp_rounding_modeset_dfp_rounding_mode_in_fpcget_dfp_rounding_modes390_isel_float_expr_wrks390_isel_float_exprhregClasss390_isel_int_expr_RMIs390_isel_int128_expr_wrks390_isel_int128_exprs390_isel_amodes390_isel_stmtmkHRegiselSB_S390s390_opnd_copypriv/host_s390_isel.ctmp < env->n_vregmap%s priv/host_generic_regs.hix <= 0xFFFFFn < 256 && (n%8) == 0get_bfp_rounding_modehregClass(dst) == HRcFlt64hregIsVirtual(dst)ty == Ity_D128Iex_Get with D128 dataIex_Qop with D128 datahregIsVirtual(*dst_hi)hregIsVirtual(*dst_lo)ty == Ity_F128Iex_Get with F128 dataIex_Qop with F128 datas390_expr_is_const_zerosize <= 8is_sane_RetLoc(rloc)rloc.pri == RLPri_IntaddToSp == 0hregClass(dst) == HRcInt64s390_amode_is_sane(am)ty == Ity_V128hregClass(dst) == HRcVec128get_dfp_rounding_modes390_isel_int_expr_RMIty == Ity_I128s390_isel_int128_exprnGSPTRs == 0 || nGSPTRs == 1nVECRETs == 1nVECRETs == 0*stackAdjustAfterCall == 0is_RetLoc_INVALID(*retloc)calling %s: return type is 0bb->tyenv->types_used >= 0iselSB_S390: IRTemp type -- get_const_value_as_ulongrloc.pri == RLPri_Nonerloc.pri == RLPri_V128SpReladdToSp == sizeof(V128)s390_isel_stmt -- PUT(%d) = ; exit-cdst->tag == Ico_U64iselNext$Ë4$Ë<$Ë,$ GNUzR| PFh B F J F J F J F J F A G  J C E FTp{Ad  K G DAAHA J G AAHA F G AAHA@ oAA ` AE G KAGN GKAGP jAA Na  AAE AFGHC  AAE AEFA(`GAa F G KAGPAC AANXC A$B(B,Kd CA AAG AF G$HH AA AAF G K A$G(N AE FA0AC ACN$w(D,B0A4B8B W e   ` (   {  ! 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X Ph j?1Pt$T$D$8M+D$8 Ph5 j<1Pt$T$D$8oM+D$8 PhW PP PhPPFJ$F J $3PhPPPhX JPhPPjjt$T$D$8L+D$8 jjt$T$D$8lL+D$8 jjt$T$D$8IL+D$8 jjt$T$D$8&L+D$8 jjt$T$D$8L+D$8 ejjt$T$D$8K+D$8 BURD$41U+D$4XZ#URD$49aU+D$4Y^#;+ Ph PhURD$45U+D$4]XURD$4=T+D$4XZAINjF wM PhPP Phߍ Ph1PP PhPP PhPP PhPP Ph Phэ PhPP Ph뤍 Phэ PhG PhPP Phj Ph Phnj1jjjD$<\F+D$<j1jjjD$<;F+D$<j11jUjD$<F+D$<j11jUjD$PPPh/PPPh5PPPh-PPPh4PPrs = %u priv/host_mips_defs.crs < 0x20rt < 0x20rd < 0x20sa < 0x20!hregIsVirtual(r)n <= 31addRegUsage_MIPSAModemapRegs_MIPSAModerRD < 0x20rRS < 0x20rRT < 0x20sa >= 0 && sa <= 0x3Fp == (UChar*)&expect[2]p == (UChar*)&expect[6]priv/host_generic_regs.hn <= 32r_dst < 0x200 == (am->Mam.IR.index & 3)am->Mam.IR.index < 0x100000am->tag == Mam_IRam->tag == Mam_RRr >= 0 && r < 32%sppHRegMIPSNVLEGELTMIPLVSVCHILSEQALGTNEQshowMIPSCondCodec.ngt.dadd.dmul.ddiv.dmadd.dmsub.dmadd.smsub.sadd.ssub.smul.sdiv.ssqrt.ssqrt.dabs.sabs.dneg.sneg.dmov.smov.dround.w.sround.w.dround.l.dfloor.w.sfloor.w.dcvt.d.wcvt.d.lcvt.d.scvt.s.dcvt.s.wcvt.w.srint.srint.dcvt.w.dcvt.l.dcvt.l.strunc.w.dtrunc.w.strunc.l.dtrunc.l.sceil.w.sceil.w.dceil.l.sceil.l.dc.un.dc.eq.dc.lt.dsub.dUnknown op: %dshowMIPSFpOpmfc1dmfc1mtc1dmtc1showMIPSFpGpMoveOpsel.dmovn.smovnseleqzselnezsel.smovn.dshowMIPSFpMoveCondOpdopyMIPSAModenextMIPSAModeFloatnextMIPSAModeInt0(%d(), ppMIPSAModeimm16 != 0x8000%d%uppMIPSRHdclzclonopdcloclzshowMIPSUnaryOpsubusltiadduandorinorxordadddsubdsubidaddiuxoriorandiaddiusltimmR == FalseshowMIPSAluOpdsrasrlvdsrldsllvsrlsllvsllsradsravsravdslldsrlvshowMIPSShftOpmsubmaddumaddmsubushowMIPSAccOpldstshowMsaMI10opmove.vcfcmsacopy_ucopy_ssldiinsveinsertctcmsashowMsaElmOpfillpcntnlocnlzcshowMsa2ROprotx32rotx64showRotxOpflog2ftrunc_sffint_sffint_ufsqrtfrsqrtfrcpfexuprftint_uftint_sftrunc_ushowMsa2RFOpvshfmax_uaver_uclt_usubs_sadd_amax_sadds_uilvlsplatsubs_uceqclt_silvoddivsmin_silvevmin_uaddvaver_silvrdivusldsubvmulvadds_sshowMsa3ROpnor.vor.vand.vxor.vshowMsaVecOpsrlisraisat_ssllisrarishowMsaBitOpfexdofmulfmsubfmaddfcltfmaxfcunfdivfaddfclemul_qftqfmin_afceqfsubfminfexp2mulr_qshowMsa3RFOp0 == (argiregs & ~mask)is_sane_RetLoc(rloc)mode64sz == 4 || sz == 8udmultmultsfastslowxscscdmtlrmflrli ,0x%016llx%s ,rotx word_compare = %s ( )mul %s%s i->Min.Ext.pos < 32i->Min.Ext.size > 0i->Min.Ext.size <= 32dext , %u, %umulmuhu dmuldmuhmthi mtlo mfhi mflo ddivmoddmodddivcall: if (%s) { addiu $29, $29, -16 ; jarl $31, $25; # args [$%d] nop; addiu $29, $29, 16; ](xDirect) if (guest_COND.%s) { move $9, 0x%x,; sw $9, (xIndir) if (guest_COND.%s) { sw (xAssisted) sw l%c%s s%c%s ll cas: , 0() movn end:sc lwc1 swc1 ldc1 sdc1 ctc1 , $31cfc1 (evCheck) lw $9, ; addiu $9, $9, -1; bgez $t9, nofail; jalr *; nofail:%s.%c , (%d)move.v [%u][%u], [0]cfcmsa , $1ctcmsa $1, , %d ppMIPSInstrllbne , end nop , 1 lldaddRegUsage_MIPSRHgetRegUsage_MIPSInstrmapRegs_MIPSRHmapRegs_MIPSInstroffsetB >= 0!hregIsVirtual(rreg)!mode64nbuf >= 32srcR->Mrh.Imm.synedsrcR->Mrh.Imm.imm16 != 0x8000!srcR->Mrh.Imm.syned!immRrDF < 0x04opc < 0x10rWD < 0x20s10 < 0x400ws < 0x20wd < 0x20op < 0x3800040df < 0x40wt < 0x20op < 0x20op < 0x3C0001Dsz32n >= 0 && n <= 32n >= 0 && n < 32delta >= 20 && delta <= 32delta > 0 && delta < 40disp_cp_xindir != NULLr_src < 0x20!(*is_profInc) => emit_MIPSInstrp - &buf[0] <= 1280 == (3 & (HWord)p)sizeof(ULong*) == 8$w0$w1$w2$w3$w4$w5$w6$w7$w8$w9$w10$w11$w12$w13$w14$w15$w16$w17$w18$w19$w20$w21$w22$w23$w24$w26$w27$w28$w29$w30$w31$d0$d1$d2$d3$d4$d5$d6$d7$d8$d9$d10$d11$d12$d13$d14$d15$f0$f1$f2$f3$f4$f5$f6$f7$f8$f9$f10$f11$f12$f13$f14$f15$f16$f17$f18$f19$f20$f21$f22$f23$f24$f25$f26$f27$f28$f29f30$f31$0$1$2$3$4$5$6$7$8$9$10$11$12$13$14$15$16$17$18$19$20$21$22$23$24$25$26$27$28$29$30$31%32%33%34rc >= HRcInt32 && rc <= HrcLASThregClass(r) == (mode64 ? HRcInt64 : HRcInt32)hregClass(reg) == HRcInt32 || hregClass(reg) == HRcInt64 || hregClass(reg) == HRcFlt32 || hregClass(reg) == HRcFlt64 || hregClass(reg) == HRcVec128syned == True || syned == Falsesz == 1 || sz == 2 || sz == 4 || sz == 8; move $9, $disp_cp_chain_me_to_%sEP; jalr $9; nop}; move $9, $disp_indir; jalr $9; nop}; move $9, $IRJumpKind_to_TRCVAL(%d); move $9, $disp_assisted; jalr $9; nop; }(profInc) move $9, ($NotKnownYet); ld $8, 0($9); daddiu $8, $8, 1; sd $8, 0($9); (profInc) move $9, ($NotKnownYet); lw $8, 0($9); addiu $8, $8, 1; sw $8, 0($9); sltiu $1, $8, 1; lw $8, 4($9); addu $8, $8, $1; sw $8, 4($9); 0 == (argir & ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11)))genSpill_MIPS: unimplemented regclassgenReload_MIPS: unimplemented regclassgenMove_MIPS: unimplemented regclass(n >= 0 && n < 32) || (n > 31 && n < 64)disp_cp_chain_me_to_slowEP != NULLdisp_cp_chain_me_to_fastEP != NULLi->Min.XDirect.cond != MIPScc_NVi->Min.XIndir.cond != MIPScc_NVi->Min.XAssisted.cond != MIPScc_NVemit_MIPSInstr.Min_XAssisted: unexpected jump kind0 == (am_addr->Mam.IR.index & 3)evCheckSzB_MIPS() == (UChar*)p - (UChar*)p0endness_host == VexEndnessLE || endness_host == VexEndnessBEisLoadImm_EXACTLY2or6(p, 9, (UInt)(Addr)disp_cp_chain_me_EXPECTED, mode64)fetch32(p + (mode64 ? 24 : 8) + 0) == 0x120F809isLoadImm_EXACTLY2or6(p, 9, (Addr)place_to_jump_to_EXPECTED, mode64)isLoadImm_EXACTLY2or6((UChar *)p, 9, mode64 ? 0x6555655565556555ULL : 0x65556555, mode64)fetch32(p + 8 + 0) == 0x8D280000 bhwdpatchProfInc_MIPSunchainXDirect_MIPSisLoadImm_EXACTLY2or6chainXDirect_MIPSmkFormImkFormRdo_load_or_store_machine_worddo_load_or_store_word32fregNoiregNodregNomkFormSdoAMode_RRdoAMode_IRmkMoveRegmkLoadImmmkForm3RFqregEncmkFormBITmkFormVECmkForm3RmkFormELMmkFormMI10emit_MIPSInstrgenReload_MIPSgenSpill_MIPSgetRegUsage_MIPSInstrppMIPSInstrMIPSInstr_FpLdStMIPSInstr_StoreCMIPSInstr_CasMIPSInstr_LoadLMIPSInstr_StoreMIPSInstr_LoadMIPSInstr_CallAlwaysMIPSInstr_CallshowMIPSAluOpMIPSRH_ImmhregClassppHRegMIPS1      ! & + 0 5 : : ? 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== 0priv/host_mips_isel.ctmp < env->n_vregmap n < 256 && (n % 8) == 0!env->mode64ee->Iex.CCall.retty == Ity_I64is_sane_RetLoc(rloc)rloc.pri == RLPri_2IntaddToSp == 0has_msaUNARY: No such op: iselInt64Expr(mips)hregClass(*rHi) == HRcInt32hregIsVirtual(*rHi)hregClass(*rLo) == HRcInt32hregIsVirtual(*rLo)argreg < MIPS_N_REGPARMS0cc != MIPScc_NVnGSPTRs == 0 || nGSPTRs == 1*stackAdjustAfterCall == 0is_RetLoc_INVALID(*retloc)ty == Ity_I8!ri->Mrh.Imm.synedmode64env->mode64iselIntExpr_R.const(mips)ty == e->Iex.CCall.rettyrloc.pri == RLPri_Int---------------> Iex_RdTmp hregIsVirtual(r)ri->Mrh.Imm.syned == synedri->Mrh.Imm.imm16 != 0x8000iselInt128Expr(mips64)ty == Ity_I64ty == Ity_I32sane_AMode(env, am)ty == Ity_F64e->Iex.Load.ty == Ity_F64!mode64hregClass(r) == HRcFlt64iselDblExpr_wrk(mips)fp_mode64iselFltExpr_wrk(mips)ty == Ity_V128e->Iex.Load.ty == Ity_V128!(e->Iex.Get.offset & 7)iselV128Expr.const(mips)iselV128Expr(mips)hregClass(r) == HRcVec128iselCondCode(mips) -- !(stmt->Ist.Put.offset & 7)d->tmp == IRTemp_INVALIDrloc.pri == RLPri_Nonerloc.pri == RLPri_V128SpReladdToSp >= 16stmt_fail tag: 0x%x iselStmt: iselBB(mips): IRTemp type -- PUT(%d) = ; exit-rc >= HRcInt32 && rc <= HrcLASThregClass(r_dst) == hregClass(r_src)hregClass(r_src) == HRcInt32 || hregClass(r_src) == HRcInt64hregClass(r_srcHi) == HRcInt32hregClass(r_srcLo) == HRcInt32typeOfIRExpr(env->type_env, e) == Ity_I64! hregIsInvalid(env->vregmapHI[tmp])e->Iex.Const.con->tag == Ico_U64typeOfIRExpr(env->type_env, e->Iex.ITE.cond) == Ity_I1iselInt64Expr(mips): No such tag(%u) doHelperCall(MIPS): cannot currently handle > 4 or 8 argsnVECRETs == ((retTy == Ity_V128 || retTy == Ity_V256) ? 1 : 0)ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32 || ty == Ity_I1 || ty == Ity_F32 || (ty == Ity_I64 && mode64) || (ty == Ity_I128 && mode64)ri->Mrh.Imm.imm16 >= 1 && ri->Mrh.Imm.imm16 <= 31hregClass(ri->Mrh.Reg.reg) == HRcInt32hregIsVirtual(ri->Mrh.Reg.reg)iselIntExpr_RH5u: unknown mips RH tagiselCondCode(mips): CmpXX32 or CmpXX64iselWordExpr_R(mips): cannot reduce treehregClass(r) == HRcGPR(env->mode64)ri->Mrh.Imm.imm16 >= 1 && ri->Mrh.Imm.imm16 <= 63hregClass(ri->Mrh.Reg.reg) == HRcGPR(env->mode64)iselIntExpr_RH6u: unknown RI tagty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32 || ((ty == Ity_I64) && env->mode64)iselIntExpr_RH.Iex_Const(mips)iselIntExpr_RH: unknown mips RH tagtypeOfIRExpr(env->type_env, e) == Ity_I128iselInt128Expr(mips64): No such tag(%u) hregClass(*rHi) == HRcGPR(env->mode64)hregClass(*rLo) == HRcGPR(env->mode64)ri->Mrh.Imm.imm16 >= 1 && ri->Mrh.Imm.imm16 <= 127iselIntExpr_RH7u: unknown RI tagsane_AMode: unknown mips amode tagiselDblExpr(mips): No such tag(%u) ty == Ity_F32 || (ty == Ity_F64 && fp_mode64)e->Iex.Load.ty == Ity_F32 || (e->Iex.Load.ty == Ity_F64 && fp_mode64)iselFltExpr(mips): No such tag(0x%x) iselV128Expr_wrk: Unsupported unop: %u e->Iex.Binop.arg2->tag == Iex_Conste->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U8e->Iex.Binop.arg2->Iex.Const.con->Ico.U8 <= 63iselV128Expr_wrk: unsupported binop: %x iselV128Expr_wrk: unsupported triop: %x iselV128Expr_wrk: Unsupported tag: %x typeOfIRExpr(env->type_env, e) == Ity_I1iselCondCode(mips): No such tag(%u) (rloc.spOff < 512) && (rloc.spOff > -512)iselStmt(mips32): Ist_Exit: dst is not a 32-bit valueiselStmt(mips64): Ist_Exit: dst is not a 64-bit valuearch_host == VexArchMIPS32 || arch_host == VexArchMIPS64VEX_PRID_COMP_MIPS == VEX_MIPS_COMP_ID(hwcaps_host) || VEX_PRID_COMP_CAVIUM == VEX_MIPS_COMP_ID(hwcaps_host) || VEX_PRID_COMP_BROADCOM == VEX_MIPS_COMP_ID(hwcaps_host) || VEX_PRID_COMP_NETLOGIC == VEX_MIPS_COMP_ID(hwcaps_host) || VEX_PRID_COMP_INGENIC_E1 == VEX_MIPS_COMP_ID(hwcaps_host) || VEX_PRID_COMP_LEGACY == VEX_MIPS_COMP_ID(hwcaps_host)archinfo_host->endness == VexEndnessLE || archinfo_host->endness == VexEndnessBEcdst->tag == (env->mode64 ? Ico_U64 :Ico_U32)iselNextiselWordExpr_RiselWordExpr_RH5u_wrkiselWordExpr_RH5uiselWordExpr_R_wrkiselCondCode_wrkiselCondCodelookupIRTempmk_iMOVds_RRiselWordExpr_AMode_wrkiselWordExpr_AModeadd_to_splookupIRTemp64doHelperCalliselWordExpr_RH7u_wrkiselWordExpr_RH7uiselV128Expr_wrkiselV128ExpriselDblExpriselDblExpr_wrkmk_LoadRR32toFPRiselFltExpr_wrkiselFltExprlookupIRTempPairiselInt128Expr_wrkiselInt128ExprhregClassiselWordExpr_RH_wrkiselWordExpr_RHiselWordExpr_RH6u_wrkiselWordExpr_RH6uiselInt64Expr_wrkiselInt64ExpriselStmtmkHRegiselSB_MIPS$Ë4$Ë,$ GNUzR| HAA Av  AAE G KAG F GKAG h+AR KAGPrAA Na  AAE HALHC  AAF AEFAh0AI FjFAA B$HA  AAA G KAG F G KAG E GKAG (LGCa D G KAG(x0GCa D G KAG0_AC q AJ GKAG0_AC q AJ GKAG @AC A|BFA A$B(Ka  AAE A BFA A$B(C HALHA  AAH G KAG N AAFA0NAA ACQe B$M(A,A0B4Ky M$A(B,He AA AAD H A$L(HS A$L(HC AA AAD A E$F AL A$F AD5AA ACQe B$M(A,A0B4Kq Fa AA AAJ H A$L(HC AA AAD H A$L(HL A$F AH E$F AxAC NJBFE E$B(Ka  AAB A BFE E$B(K HALHC  AAF AEFA`AD CCN$F(I,M0A4D8BAE ACN$A(B,F0A4D8B- L MЌ_pAk ~(  @  0W4 P!PN0 I bn      x d 6H a z p $   X  H *  C \, u-~  0      .6 6Rggh'jej6p  CA!(/p6=+D}2KK/RGYH`ej'o0tFy[~  H ]  u  x ';W @   k" (.4 :O@eFt L R6X^ dL j pv| w $    , P     @ h       $[*B0 6:< B{H0 NqT` Z`f l| r x~  L   ( - 2N~gP  |     % , 3 ( : ""@ F L R UX M^ d :3j 4p 1v -| .+ . & * % ]$ # R R hR Q R [ `X Z Z PZ X Y W 2[ bd 7f d d d& e- b4 g; xfB cI 9cP eW `b^ ae al as xaz |` N` a ` Ia _ >_ ^ ^ h i h j ph g h 3k Vk k :k k uk k k" k) k0 sj7 k> BpE kpL pS pZ pa zph _po qpv p} p    ( b >   ®  u A ϻ ] Ϲ T  _    Y % , 3 (: A H O V ] kd Pk r y X    B  G   e #        -   g % ! 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