! / 0 0 0 0 368 ` &&&&&&&&&&&&&&&&s390_host_hwcapsLibVEX_default_VexControlLibVEX_InitLibVEX_FrontEndLibVEX_TranslateLibVEX_ChainLibVEX_UnChainLibVEX_evCheckSzBLibVEX_PatchProfIncLibVEX_EmNote_stringLibVEX_ppVexArchLibVEX_ppVexEndnessLibVEX_ppVexHwCapsLibVEX_default_VexArchInfoLibVEX_default_VexAbiInfos390x_vec_op_t// 54 ` libvexmultiarch_amd64_linux_a-multiarch_main_main.o/ /0 0 0 0 644 59208 ` ELF>@@f.AWAVAUATUHSHHHcH>%=-H=H= H= H=HHcHDH%= tkH= t]HctFH=u8@HH@HEHHHD@HH=1=L-HҀ=L-H뵀=L-H똀=L%Hx=L%txH\=L%t H@LH1?H5ItHH5L1HH5L1L-H AM}@%= `-H% ti=tbH iftD1H Hz9t,t 9tHH9B 9uHA @ NE4tttH?r@8h7WH^fD8%{/=v%wH@Hf%)u=- bHif= ==HDgHfD?tHfDH=%tVzH=-HL@@$H+=tH@t=OH=HHHHH{HjHYHHH7H&HH@PXH=1HH H5H=ff.ff.S HCHHHxHCH< HCC[H=H=H5]HtHAЅAA = A!d8QM9ey{A~dgdO7oD1oI HfDH H5H=fH H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H H5H=H !H5H=AWAVAUATUSH8- HHIHHcH>@AAG@- HHcH>D$= II /IIH1IAA@u AGHA? HHcH>DADD$;HKIvH \H5H=f.AG -HD$L%AHD$HD$HD$(H$HD$ fDAwHHCE-HMHS HD$IHsPAVD$ PD$ PIAAAUPIGPAPAPAGLPAAAMHIMIrFf7ML9G1 H9<f|B'vH QH5H=@A HD$L%AHD$HD$HD$(H$HD$ mDAG -HD$L%AHD$HD$`HD$(H$XHD$ fA #HD$L%AHD$HD$HD$(H$HD$ DA HD$L%AHD$HD$`HD$(H$XHD$ EDA HD$L%ADHD$HD$tHD$(H$pHD$ DA HD$L%AHD$HD$pHD$(H$hHD$ DA H yH5H=AG -HD$L%AHD$HD$XHD$(H$PHD$ H XH5H=H=1DE-tfH=1LDH51EMLMHT$(Ht$ I@IHt-HLMGHE\$IISHT$(Y^IIHt-HLMGHE\$IISHT$(IXZ uILLIHDLH5H8L[]A\A]A^A_ÐH SH5H=H TH5H=H UH5H=I;hDDr1LH=IDEtQAFL$$E1HDHl$HHDe1EHH=DE1H9uL$$Hl$DH=1H [H5H=DH -H5H=fH YH5H=H NH5H=H OH5H=H=1LH=19H=1LH=1H=1LH=1bH UH5H=H H5H=H H5H=H H5H=H H5H=H H5H=xH5H=H H5H=H H5H=H H5H=yH=ff.fAWfAVAUIATUSHxHT$|H$D$|)$= I ' HAIDd$|ItAH I$AE-PHHcH>H I$tH H5H=f.D$ L51D$(AE@- HHcH>D1E1HD$AEL- HD$`HHD$HHD$0HHD$hHHD$HHD$XHHD$PHHD$HHHD$@HHD$8AuHA}@uDLHIIHtHH  }$ HAu@HIUHATAIAPD$PDD$@HD$PH HHD$D$H$HD$8H$HD$@H$HD$HH$HD$PH$HD$XH$HD$`H$D$($HD$H$HD$hH$H$HH!S  AE11M$HD${L$HD$HN,D${LEOLLA AAADD$ H|$8HD$0H AB|-A;|${RIE~"Au1H)@A  HHH9uID9c fHc6fDA}LHD$ HAHD$`HD$HHD$0HHD$hHHD$HHD$XHHD$PHHD$HHHD$@HHD$8AHD$AEL-bH H5H=f.D$ L51D$(fD$ L51D$(hfD$ L51D$(fD$ L51D$(rfD$ L51D$(RfD$ L51D$(2fD$ L51D$(fD$ $L5(D$(0A}LHD$HAHD$`HD$HHD$0HHD$hHHD$HHD$XHHD$PHHD$HHHD$@HHD$8A}LHD$HE1HD$`HD$HHD$0HHD$hHHD$HHD$XHHD$PHHD$HHHD$@HHD$8yA}LHD$HAHD$HHD$0HHD$hHHD$HHD$`HHD$XHHD$PHHD$HHHD$@HHD$8DA}LHD$THE1HD$HHD$0HHD$hHHD$HHD$`HHD$XHHD$PHHD$HHHD$@HHD$8>AHD$AEL-HD$`HHD$HHD$0HHD$hHHD$HHD$XHHD$PHHD$HHHD$@HHD$81E1A}LHD$bH H5H=@H H5H=fH$HHbH=1EE1K H-~LL,$MELd$DH1HDJH5H=H=H=AHHLLIcL>E1DDADfDDDDE1DDADfDPH H5H=AHHLLIcL>E1DDADfDDDDE1DDADfDPH H5H=tÐHwoHHcH>HH 3H5H=AHHH HcH>1DfDDDDDD1DfDDDPH [H5H=[HHcH>HHHHHHHHHHHHHHHHHHHHHPH=ff. HHcH>@HHHHHHHHHHHHt'HtHHHDDAVAUATUSHHcH>fHH H HHHcHDDH tmH t^HctGHu8@HH@HE@HHHD[]A\A]A^=L%[H]A\A]A^@=L%L[H]A\A]A^@=L%[H]A\A]A^@=H-H\=H-|H<=H-t[H]A\A]A^ÉHH1?H5HtHH5H1HH5H1AIH-L5Lm= 0vcon->iropt_verbosity >= 0vcon->iropt_level >= 0vcon->iropt_level <= 2vcon->guest_max_insns >= 1vcon->guest_max_insns <= 100vcon->guest_chase_thresh >= 0udiv32(100, 7) == 14sdiv32(100, 7) == 14sdiv32(-100, 7) == -14sdiv32(100, -7) == -14sdiv32(-100, -7) == 14vex_initdonevta->needs_self_check != NULLvta->disp_cp_xindir != NULLvta->disp_cp_xindir == NULLGuestBytes %lx %u %02x %08x initial IR irsb->offsIP >= 16%3d %02x vta->addProfIncres->offs_profInc == -1out_used >= 0noneUnmasking SSE FP exceptionsUnmasking x87 FP exceptionsVexArch???INVALIDAMD64ARMARM64PPC32PPC64S390XMIPS32MIPS64X86VexEndness???BigEndianLittleEndian11LibVEX_PatchProfIncLibVEX_evCheckSzBLibVEX_UnChainLibVEX_Chainlibvex_BackEnd@ldispeimmgiedfpfgxstfleetf2 etf3@stckffpextlscpfpos390xneonvfpARM@FXGX vmxDFPISA2_07@ISA3_0ppc64-int-fltfltvmxFXGXVXDFPISA2_07 ISA3_0ppc32-int@cx16lzcntrdtscp sse3ssse3avxavx2bmi@f16c rdrandamd64mmxextsse1sse2sse3 lzcntx86arch_word_sizeLibVEX_FrontEndLibVEX_InitSupport for SSSE3 requires SSE3 capabilities Support for AVX requires SSSE3 capabilities Support for AVX2 requires AVX capabilities Support for BMI requires AVX capabilities Missing floating point capability DFP requires VMX and FX and GX capabilities VX requires VMX and FX and GX capabilities ISA2_07 requires VMX and FX and GX capabilities ISA 3.0 not supported in 32-bit mode ISA2_07 requires VX capabilities ISA2_07 requires DFP capabilities ISA3_0 requires ISA2_07 capabilities ISA3_0 requires VMX and FX and GX capabilities NEON instructions are not supported for ARMv5. NEON instructions are not supported for ARMv6. NEON and VFP3 are required for ARMv8. ARM architecture level is not supported. Unsupported hardware capabilities. Host does not have long displacement facility. Fatal: unknown arch in arch_word_size vcon->iropt_unroll_thresh >= 0vcon->iropt_unroll_thresh <= 400vcon->guest_chase_thresh < vcon->guest_max_insnsvcon->guest_chase_cond == True || vcon->guest_chase_cond == Falsevcon->regalloc_version == 2 || vcon->regalloc_version == 3vta->disp_cp_xassisted != NULLvta->disp_cp_chain_me_to_fastEP != NULLvta->disp_cp_chain_me_to_fastEP == NULLvta->archinfo_guest.endness == VexEndnessLE0 == sizeof(VexGuestX86State) % LibVEX_GUEST_STATE_ALIGNvta->archinfo_guest.endness == VexEndnessBEvta->archinfo_guest.endness == VexEndnessBE || vta->archinfo_guest.endness == VexEndnessLEvta->archinfo_guest.endness == VexEndnessLE || vta->archinfo_guest.endness == VexEndnessBELibVEX_Translate: unsupported guest insn set ------------------------ Front end ------------------------ *pxControl >= VexRegUpdSpAtMemAccess && *pxControl <= VexRegUpdAllregsAtEachInsnvta->guest_extents->n_used >= 1 && vta->guest_extents->n_used <= 3vta->guest_extents->base[0] == vta->guest_bytes_addrvta->guest_extents->len[i] < 10000can't show code due to extents > 1 ------------------------ After pre-instr IR optimisation ------------------------ ------------------------ After instrumentation ------------------------ after post-instrumentation cleanup ------------------------ After post-instr IR optimisation ------------------------ LibVEX_Codegen: unsupported guest insn setvta->archinfo_host.endness == VexEndnessLEvta->archinfo_host.endness == VexEndnessBEvta->archinfo_host.endness == VexEndnessBE || vta->archinfo_host.endness == VexEndnessLEvta->archinfo_host.endness == VexEndnessLE || vta->archinfo_host.endness == VexEndnessBELibVEX_Translate: unsupported host insn set ------------------------ After tree-building ------------------------ ------------------------ Instruction selection ------------------------ ------------------------ Register-allocated code ------------------------ ------------------------ Assembly ------------------------ VexExpansionRatio %d %d %d :10 Encountered an instruction that requires the vector facility. That facility is not available on this hostSelection of non-80-bit x87 FP precisionSetting %mxcsr.fz (SSE flush-underflows-to-zero mode)Setting %mxcsr.daz (SSE treat-denormals-as-zero mode)Setting %eflags.ac (setting noted but ignored)Unmasking PPC32/64 FP exceptionsPPC64 function redirection stack overflowPPC64 function redirection stack underflowThe specified rounding mode cannot be supported. That feature requires the floating point extension facility which is not available on this host. Continuing using the rounding mode from FPC. Results may differ!The specified rounding mode is invalid. Continuing using 'round to nearest'. Results may differ!Instruction stfle is not supported on this hostInstruction stckf is not supported on this hostInstruction ecag is not supported on this hostInstruction pfpo is not supported on this hostDFP instructions are not supported on this hostEncountered an instruction that requires the floating point extension facility. That facility is not available on this hostThe rounding mode in GPR 0 for the PFPO instruction is invalidThe function code in GPR 0 for the PFPO instruction is invalidLibVEX_EmNote_string: unknown warningGNUzRx 00BHB B(A0D8D@ zRx @( J D  F 3AAMHEB HE K ( FBB B(A0A8DpxZBEENGBAEDIEGGGPpx]HxApXx]KxApc 8D0A(B BBBB xFFB E(A0A8GMSFP8GGGUH 8A0A(B BBBE PhZe A ui;LBB A(A0+ (A BBBD U (H BBBE U (H BBBE U (H BBBE Q (H BBBA zRx 0(PEJ2ElS!E+ [5`W?-ISX`@r<@x0`H  ` !.; 3QkP ~0  x h P'0AY_ed0iTns x@}w<  P  0        HR ! ' 0- 3 9 ? E `K `QgWx]cziou{N  0   Pcx  0   B    3#9) / 5; (A pG MMS Y P_ pe k q w `}    @ b li   Or P   p    x     h  8' . 5 < C ` J 8 Q  X _ fm h t{  (!D:,    ,3>N` Hhr ~ &9Gt CZl # 0 Z o       + ; G V _ f w           ! 9 N ] i t         " / ; H V f u            . D T a m z        &7CQ^o+(I]p8)G[n*%5DS0+gy,u- P.;.1 4PLp42fsdiv32invalid_hwcapsbuf.14274buf.14288buf.14320buf.14260buf.14246buf.14302prefix.14297hwcaps_list.14301prefix.14241hwcaps_list.14245prefix.14255hwcaps_list.14259prefix.14315hwcaps_list.14319prefix.14283hwcaps_list.14287prefix.14269hwcaps_list.14273invalid_hwcaps.coldcheck_hwcapsextras.14356arch_word_size.part.0__PRETTY_FUNCTION__.14237udiv32.constprop.0__PRETTY_FUNCTION__.13918__PRETTY_FUNCTION__.13944__PRETTY_FUNCTION__.14044__PRETTY_FUNCTION__.14116__PRETTY_FUNCTION__.14134cached.14138__PRETTY_FUNCTION__.14150__PRETTY_FUNCTION__.14167LibVEX_ppVexHwCaps.cold.LC12.LC6.LC3.LC5.LC2.LC1.LC4.LC13.LC11.LC0.LC20.LC18.LC16.LC14.LC15.LC19.LC10.LC9.LC8.LC7.LC17.LC42.LC26.LC36.LC33.LC41.LC31.LC37.LC38.LC22.LC32.LC34.LC30.LC43.LC39.LC29.LC24.LC23.LC40.LC28.LC27.LC25.LC44.LC45.LC46.LC53.LC47.LC48.LC49.LC50.LC51.LC52.LC62.LC54.LC55.LC56.LC57.LC58.LC59.LC60.LC61.LC63.LC64.LC65.LC66.LC73.LC84.LC75.LC70.LC80.LC85.LC89.LC93.LC67.LC68.LC69.LC86.LC87.LC88.LC72.LC81.LC71.LC82.LC83.LC90.LC91.LC94.LC92.LC76.LC77.LC78.LC74.LC79.LC99.LC97.LC105.LC104.LC106.LC108.LC107.LC102.LC101.LC112.LC103.LC109.LC110.LC111.LC96.LC98.LC100.LC95.LC132.LC131.LC130.LC129.LC128.LC127.LC126.LC125.LC124.LC123.LC122.LC121.LC120.LC119.LC118.LC117.LC116.LC115.LC133.LC114.LC113.LC134.LC145.LC136.LC144.LC137.LC142.LC143.LC138.LC139.LC140.LC141.LC135.LC148.LC147.LC146_GLOBAL_OFFSET_TABLE_vfatalvex_sprintfs390_host_hwcapsvpanicvex_printfvex_assert_failLibVEX_default_VexControlvex_bzeroLibVEX_Initvex_initdonevex_failure_exitvex_log_bytesvex_debuglevelvex_controlvexSetAllocModeLibVEX_FrontEndvexSetAllocModeTEMP_and_clearvexAllocSanityCheckvex_traceflagsmips32Guest_layoutdisInstr_MIPSguest_mips32_state_requires_precise_mem_exnsguest_mips32_spechelperbb_to_IRs390xGuest_layoutdisInstr_S390guest_s390x_state_requires_precise_mem_exnsguest_s390x_spechelperppc64Guest_layoutdisInstr_PPCguest_ppc64_state_requires_precise_mem_exnsguest_ppc64_spechelperppc32Guest_layoutguest_ppc32_state_requires_precise_mem_exnsguest_ppc32_spechelperarm64Guest_layoutdisInstr_ARM64guest_arm64_state_requires_precise_mem_exnsguest_arm64_spechelperarmGuest_layoutdisInstr_ARMguest_arm_state_requires_precise_mem_exnsguest_arm_spechelperamd64guest_layoutdisInstr_AMD64guest_amd64_state_requires_precise_mem_exnsguest_amd64_spechelpermips64Guest_layoutguest_mips64_state_requires_precise_mem_exnsguest_mips64_spechelpersanityCheckIRSBdo_iropt_BBdo_deadcode_BBcprop_BBppIRSBLibVEX_TranslategetRRegUniverse_MIPSemit_MIPSInstriselSB_MIPSppHRegMIPSppMIPSInstrgenMove_MIPSgenReload_MIPSgenSpill_MIPSmapRegs_MIPSInstrgetRegUsage_MIPSInstrado_treebuild_BBdoRegisterAllocation_v2getRRegUniverse_S390emit_S390InstriselSB_S390ppHRegS390ppS390InstrgenMove_S390genReload_S390genSpill_S390mapRegs_S390InstrgetRegUsage_S390Instrguest_x86_state_requires_precise_mem_exnsgetRRegUniverse_ARM64emit_ARM64InstriselSB_ARM64ppHRegARM64ppARM64InstrgenMove_ARM64genReload_ARM64genSpill_ARM64mapRegs_ARM64InstrgetRegUsage_ARM64InstrgetRRegUniverse_ARMemit_ARMInstriselSB_ARMppHRegARMppARMInstrgenMove_ARMgenReload_ARMgenSpill_ARMmapRegs_ARMInstrgetRegUsage_ARMInstrgetRRegUniverse_AMD64emit_AMD64InstriselSB_AMD64ppHRegAMD64ppAMD64InstrdirectReload_AMD64genMove_AMD64genReload_AMD64genSpill_AMD64mapRegs_AMD64InstrgetRegUsage_AMD64InstrgetRRegUniverse_X86emit_X86InstriselSB_X86ppHRegX86ppX86InstrdirectReload_X86genMove_X86genReload_X86genSpill_X86mapRegs_X86InstrgetRegUsage_X86InstrgetRRegUniverse_PPCemit_PPCInstriselSB_PPCppHRegPPCppPPCInstrgenMove_PPCgenReload_PPCgenSpill_PPCmapRegs_PPCInstrgetRegUsage_PPCInstrdoRegisterAllocation_v3LibVEX_ChainLibVEX_UnChainunchainXDirect_MIPSunchainXDirect_X86unchainXDirect_AMD64unchainXDirect_ARMunchainXDirect_ARM64unchainXDirect_PPCunchainXDirect_S390LibVEX_evCheckSzBevCheckSzB_PPCevCheckSzB_MIPSevCheckSzB_AMD64evCheckSzB_ARM64evCheckSzB_S390evCheckSzB_ARMevCheckSzB_X86LibVEX_PatchProfIncpatchProfInc_MIPSpatchProfInc_X86patchProfInc_AMD64patchProfInc_ARMpatchProfInc_ARM64patchProfInc_PPCpatchProfInc_S390LibVEX_EmNote_stringLibVEX_ppVexArchLibVEX_ppVexEndnessLibVEX_ppVexHwCapsLibVEX_default_VexArchInfoLibVEX_default_VexAbiInfos390x_vec_op_t3X(j)|*+,-)*-,./-041F2MS[hpx[\\{||T39L@4JSZ5dkr4645<4"43,?5FKZ45\45 #4Rh7o4y89:;<@4& c==[>?@"0ABCD+EFFGH7 I< C JT Ke Kv L M N H @ O P O Q R '  3 S: T? n         , S U# 3 ,? SF VK S ,_ Sf Wk s , S X  , S Y  , S Z  , S [  , S \  , S& ]+ 3 ,? SF ^K S ,_ Sf _k s , S `  , S a  , S b  , S c  , Sd ,S&e+3,?SFfKS,_Sfgks,ShDh ^cxSi%4*F*Z*(4Sj***,*>*R*******AP*b*v**** Sk5D*V*j*Slmno'3qp#/S6q;COSVr[coSvs{tuv'3S:w?KWS^xcsSySzS{|}~ } 3:BI}PZfrSyx~SSSS S%S,18DSKPWcSjovS"_Si*%*1*=*I*U*a*m*y**#)6*.*:* F* R* ^* j* v**S* *+*K*k**** * ** *6 *B *N *Z *f *r *  * * * * *  *! *" *#!*$!%3!*&E!*'Q!*(]!*)i!**u!*+!*,!*-!*.!*/!0!*1!*2!*3!*4"*5"*6"*7*"*86"*9B"*:\";"*<"*="*>"*?"*@"*A"*B"*C"*D";#$#S+#0#;#G#SN#yS#u#E}#######}#$}$$$$$V$a$t${$$$$}$5%}:%@%X%y%%}%%}%%%%%%%}%%&&S&&q+&3&?&SF&sK&a&f&l&&&&&&S&&''S'l'#'/'S6';'C'O'SV'['c'o'Sv'{'''S'w'''S''''S''''S'(((S( ('(3(S:(?(F(R(SY(^(e(q(Sx(}(((S(T((((((|)t)S)T))\*dh*So*Tt***@*W**X**Y**Z**[**\*+]++L+S$+T)+O+d+,+S+T, ,3,C,S,c,s,,,,,,,,,--#-3-C-S-c-s-|--------..#.3.C.K.W.f.{....(.).*/+)/,0/-M/)b/*s/-/,/.///0/1///0 00*020@0R0[Z0\g0\r0z000{0|0|0T0300L0401 151)1514i1{11511@1411,25 2224P2e2l25t22\242225222403K37R34\3m38393:3;3<343363@344.4~4, (G )G)H$)I4)JD)KW)Lj)Lt)M)O)O)P*Q*R$*S7*TJ*TT*Uf+_y+_+`+a+b+c+d+d+e.< / 4a_ $(,x04P8<8@TDHLPTX\`dhlptx | 8,@$Hl!! #d")$)8)L) `)t)) ) ) )$*(*,,*0@*4T*8h*<)@*D+H*L*P*T*X*\*`*d*h+l+p+t+x+|++|++`-T-H-<-0-$-- --,,,,,,,,,,|,----.0.D.X. . .-p0 T00//0 @0$.(h/ 4 P `  ,T(l)*0+,-P.. 4p4.symtab.strtab.shstrtab.rela.text.data.bss.rodata.str1.1.rela.text.unlikely.rela.rodata.rodata.str1.8.note.GNU-stack.note.gnu.property.rela.eh_frame @4@xxK&4,5 125QEQ9@@0Y`9< T@  a2>pOO O@( S8" vu